JP2010258761A - Clock frequency divider circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain an output clock signal by frequency-dividing an input clock signal in a frequency dividing ratio, that is represented with optional rational numbers, by enabling an output clock signal to rise in falling of the input clock signal. <P>SOLUTION: An clock frequency divider circuit includes at least a computing unit 11, a computing unit 12a, and a comparator 108. An input clock signal 109 is frequency-divided in a frequency dividing ratio that is a value obtained by dividing a numerator setting value 112 by a denominator setting value 111. The computing unit 11 records the value of the input signal in synchronization with the input clock signal 109. Then, a generated computing unit output value 120 is output in response to the input clock signal 109. The computing unit 12a outputs the computing unit output value 120. The comparator 108 compares the computing unit output value 120 with the numerator setting value 112, and outputs a high signal or a low signal as an output clock signal 121. The computing unit output value 120 is fed back and input to the computing unit 11. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a clock divider circuit, and more particularly to a clock divider circuit that generates an output clock signal obtained by dividing an input clock signal by a division ratio represented by an arbitrary rational number.

  In the emulator, when a circuit to be emulated uses a plurality of clocks, emulation is performed using a plurality of frequency dividing circuits. Since the clock divider circuit that generates the output clock signal obtained by dividing the input clock signal by the division ratio represented by an arbitrary rational number does not have the same rise timing with the output clock signal having a different division ratio, Operation and emulator operation may be different, which may cause problems on actual machines. Therefore, it is desired to improve the frequency dividing accuracy of the clock frequency dividing circuit.

  FIG. 5 is a diagram illustrating a configuration of the clock frequency dividing circuit 300 disclosed in Patent Document 1. In FIG. The clock frequency dividing circuit 300 divides the input clock signal 302 by N / D. Here, N / D is the frequency division ratio, N is the numerator setting value, and D is the denominator setting value. However, N and D are arbitrary natural numbers, respectively, and N ≦ D and D! = 0.

  First, the configuration of the clock frequency dividing circuit 300 will be described. As shown in FIG. 5, the clock divider circuit 300 includes a selector 307, an adder 308, a subtractor 316, a register 309, a latch 313, and an AND circuit 314.

  The selector 307 receives the input signal 301 corresponding to the denominator setting value D, the input signal 304 corresponding to the value “0”, and the most significant bit output signal 311. Here, the most significant bit output signal 311 is an output signal corresponding to the most significant bit of the register output signal 310 output from the register 309. The selector 307 outputs the input signal 301 corresponding to the denominator setting value D as the selector output 305 when the value of the most significant bit output signal 311 is “1”. On the other hand, when the value of the most significant bit output signal 311 is “0”, the input signal 304 is output as the selector output 305.

  The adder 308 receives the input signal 320 and the register output signal 310 corresponding to the numerator set value N, and outputs an adder output signal 315 corresponding to the addition result.

  The subtractor 316 receives the adder output signal 315 and the selector output 305, and subtracts the output corresponding to the value obtained by subtracting the value corresponding to the selector output 305 from the value corresponding to the adder output signal 315. The signal 306 is output.

  The register 309 includes a subtracter output signal 306, an input signal 317 corresponding to a predetermined initial value “2R−1” (where the variable R represents a value obtained by equation (1) described later), and a reset. The signal 318 and the input clock signal 302 are input, and the register output signal 310 is output. The most significant bit of the register output signal 310 is output as the most significant bit output signal 311.

  That is, the initial value “2R−1” is set in the register 309 by the reset signal 318. Further, a subtracter output signal 306 is input in synchronization with the input clock signal 302, and a value corresponding to the subtracter output signal 306 is stored.

  In the latch 313, the most significant bit output signal 311 is input to the D terminal, and the input clock signal 302 is input to the G terminal. The most significant bit output signal 311 is output as the latch output signal 312 while the value of the input clock signal 302 is “0”.

  On the other hand, while the value of the input clock signal 302 is “1”, the most significant bit output signal 311 input when the value of the input clock signal 302 transitions from “0” to “1” is held and latched. Output as an output signal 312.

  The AND circuit 314 receives the latch output signal 312 and the input clock signal 302, takes a logical product (AND) of the latch output signal 312 and the input clock signal 302, and outputs an output clock signal 303 corresponding to the result. Generate and output.

Here, the bit width of each part is set based on the value of the variable R calculated from Expression (1).

R = ceil (log (d) / log (2)) (1)

The variable d is the minimum bit width that can be expressed. Further, ceil is a function that returns a minimum integer value that is not smaller than an argument, and log is a function that returns a natural logarithm.

  Therefore, from equation (1), the adder 308 is configured with (R + 1) bit width, the subtractor 316 is configured with (R + 1) bit width, the selector 307 is configured with R bit width, and the register 309 is (R + 1). ) Consists of bit width.

  The input signal 320 corresponding to the numerator set value N is configured with an R bit width. The input signal 301 corresponding to the denominator setting value D is configured with an R bit width.

  The adder output signal 315 has a (R + 1) bit width. The subtracter output signal 306 has a (R + 1) bit width. The selector output 305 has an R bit width. The register output signal 310 has a (R + 1) bit width. The most significant bit output signal 311 has a 1-bit width.

  Next, the operation of the clock frequency dividing circuit 300 will be specifically described. FIG. 6 is a timing chart showing an operation when N = 3 and D = 5 and N / D = 3/5 frequency division is performed in the clock frequency dividing circuit 300 shown in FIG. In this case, R = 3 (= ceil (log (5) / log (2))) from equation (1). In the following, one cycle is defined as one cycle from the rising edge of the input clock signal 302, and each cycle is described as t1, t2, t3,.

  First, the reset signal 318 becomes high, and an initial value “7” (= 2R−1, R = 3) is set in the register 309 by the input signal 317.

  In the cycle t1, the register 309 outputs the register output signal 310 corresponding to the above-described initial value “7” (“0111” in binary notation). At this time, the value of the most significant bit output signal 311 is “0”.

  The latch 313 captures and holds the value “0” of the most significant bit output signal 311 when the input clock signal 302 transitions to “1”. Then, while the value of the input clock signal 302 is “1”, the latch output signal 312 corresponding to the held value “0” is output.

  The adder 308 adds the value “7” of the register output signal 310 and the value “3” of the input signal 320 corresponding to the numerator setting value N, and adds the value “10” (“1010” in binary notation). The adder output signal 315 corresponding to “)” is output.

  Since the value of the most significant bit output signal 311 is “0”, the selector 307 selects the value “0” of the input signal 304 and outputs it as the selector output 305.

  The subtractor 316 subtracts the value “0” of the selector output 305 from the value “10” of the adder output signal 315, and outputs a subtracter output signal 306 corresponding to the value “10” as a subtraction result.

  In the next cycle t2, the register 309 stores the value “10” of the subtracter output signal 306 and outputs the register output signal 310 corresponding to the value “10”. At this time, the value of the most significant bit output signal 311 is “1”.

  The latch 313 captures and holds the value “0” of the most significant bit output signal 311 when the input clock signal 302 transitions to “1”. Then, while the value of the input clock signal 302 is “1”, the held value “0” is output as the latch output signal 312.

  Since the value of the most significant bit output signal 311 is “1” while the value of the input clock signal 302 is “0”, the value of the latch output signal 312 is “1”.

  The adder 308 adds the value “10” of the register output signal 310 and the value “3” of the input signal 320 corresponding to the numerator setting value N, and adds the output signal 315 corresponding to the value “13” as the addition result. Is output.

  Since the value of the most significant bit output signal 311 is “1”, the selector 307 selects the value “5” of the input signal 301 corresponding to the denominator setting value D and outputs it as the selector output 305.

  The subtractor 316 subtracts the value “5” of the selector output 305 from the value “13” of the adder output signal 315, and the subtracter corresponding to the value “8” (“1000” in binary notation) that is the subtraction result. An output signal 306 is output.

  In the next cycle t3, the register 309 stores the value “8” of the subtracter output signal 306 from the subtractor 316 and outputs the register output signal 310 corresponding to the value “8”. At this time, the value of the most significant bit output signal 311 is “1”.

  The latch 313 captures and holds the value “1” of the most significant bit output signal 311 when the input clock signal 302 transitions to “1”. Then, while the value of the input clock signal 302 is “1”, the latch output signal 312 corresponding to the held value “1” is output.

  Since the value of the most significant bit output signal 311 is “1” while the value of the input clock signal 302 is “0”, the value of the latch output signal 312 is “1”.

  The adder 308 adds the value “8” of the register output signal 310 and the value “3” of the input signal 320 corresponding to the numerator set value N, and the adder output signal 315 corresponding to the value “11” as the addition result. Is output.

  Since the value of the most significant bit output signal 311 is “1”, the selector 307 selects the value “5” of the input signal 301 corresponding to the denominator setting value D and outputs it as the selector output 305.

  The subtracter 316 subtracts the value “5” of the selector output 305 from the value “11” of the adder output signal 315, and the subtracter corresponding to the value “6” (“0110” in binary notation) that is the subtraction result. An output signal 306 is output.

  In the next cycle t4, the register 309 stores the value “6” of the subtracter output signal 306 and outputs the register output signal 310 corresponding to the value “6”. At this time, the value of the most significant bit output signal 311 is “0”.

  The latch 313 captures and holds the value “1” of the most significant bit output signal 311 when the input clock signal 302 transitions to “1”. Then, while the value of the input clock signal 302 is “1”, the latch output signal 312 corresponding to the held value “1” is output.

  Since the value of the most significant bit output signal 311 is “0” while the value of the input clock signal 302 is “0”, the value of the latch output signal 312 is “0”.

  The adder 308 adds the value “6” of the register output signal 310 and the value “3” of the input signal 320 corresponding to the numerator setting value N, and adds the output signal 315 corresponding to the value “9” as the addition result. Is output.

  Since the value of the most significant bit output signal 311 is “0”, the selector 307 selects the value “0” of the input signal 304 indicating the denominator setting value D and outputs it as the selector output 305.

  The subtracter 316 subtracts the value “0” of the selector output 305 from the value “9” of the adder output signal 315, and the subtracter corresponding to the value “9” (“1001” in binary notation) that is the subtraction result. An output signal 306 is output.

  In the next cycle t5, the register 309 stores the value “9” of the subtracter output signal 306 and outputs the register output signal 310 corresponding to the value “9”. At this time, the value of the most significant bit output signal 311 is “1”.

  The latch 313 captures and holds the value “0” of the most significant bit output signal 311 when the input clock signal 302 transitions to “1”. Then, while the value of the input clock signal 302 is “1”, the latch output signal 312 corresponding to the held value “0” is output.

  Since the value of the most significant bit output signal 311 is “1” while the value of the input clock signal 302 is “0”, the value of the latch output signal 312 is “1”.

  The adder 308 adds the value “9” of the register output signal 310 and the value “3” of the input signal 320 corresponding to the numerator set value N, and adds the output signal corresponding to the value “12” as the addition result. 315 is output.

  Since the value of the most significant bit output signal 311 is “1”, the selector 307 selects the value “5” of the input signal 301 corresponding to the denominator setting value D and outputs it as the selector output 305.

  The subtractor 316 subtracts the value “5” of the selector output 305 from the value “12” of the adder output signal 315, and the subtracter corresponding to the value “7” (“0111” in binary notation) that is the subtraction result. An output signal 306 is output.

  In the next cycle t6, the register 309 stores the value “7” of the subtracter output signal 306 from the subtractor 316 and outputs the register output signal 310 corresponding to the value “7”. At this time, the value of the most significant bit output signal 311 is “0”.

  The latch 313 captures and holds the value “1” of the most significant bit output signal 311 when the input clock signal 302 transitions to “1”. Then, while the value of the input clock signal 302 is “1”, the latch output signal 312 corresponding to the held value “1” is output.

  Since the value of the most significant bit output signal 311 is “0” while the value of the input clock signal 302 is “0”, the value of the latch output signal 312 is “0”.

  The adder 308 adds the value “7” of the register output signal 310 and the value “3” of the input signal 320 corresponding to the numerator setting value N, and adds the output signal 315 corresponding to the value “10” as the addition result. Is output.

  Since the value of the most significant bit output signal 311 is “0”, the selector 307 selects the value “0” of the input signal 304 and outputs it as the selector output 305.

  The subtractor 316 subtracts the value “0” of the selector output 305 from the value “10” of the adder output signal 315, and performs subtraction corresponding to the value “10” (“1010” (binary notation)) that is the subtraction result. Device output signal 306 is output.

  In the next cycle t7, the register 309 stores the value “10” of the subtracter output signal 306 from the subtractor 316 and outputs the register output signal 310 corresponding to the value “10”. At this time, the value of the most significant bit output signal 311 is “1”.

  Thereafter, a series of operations described in cycles t1 to t5 are repeatedly executed. As a result, the output pattern {7, 10, 8, 6, 9} is repeated as the value of the register output signal 310 as shown in FIG.

  Further, as the value of the most significant bit output signal 311, the output pattern {0, 1, 1, 0, 1} is repeated as shown in FIG. 6.

JP 2006-148807 A

  However, in the above-described clock frequency dividing circuit 300, when generating an output clock signal obtained by dividing the input clock signal by a frequency dividing ratio represented by an arbitrary rational number, a desired output clock signal may not be output. The reason will be described below.

  In the clock frequency dividing circuit 300, as shown in FIG. 5, the output clock signal 303 is an output of the AND circuit 314 that receives the latch output signal 312 and the input clock signal 302 as inputs.

  Therefore, the AND circuit 314 outputs a signal in the same state as the input clock signal 302 as the output clock signal 303 when the latch output signal 312 is high. Therefore, the rising timings of the output clock signal 303 and the input clock signal 302 are the same.

  Therefore, in principle, the output clock signal 303 cannot be raised at the timing when the input clock signal 302 falls. Therefore, there is a frequency division ratio that cannot be realized in practice.

  The clock frequency dividing circuit which is one embodiment of the present invention records the value of the input signal in synchronization with the input clock signal, and is generated based on the input signal, the first set value, and the second set value. A first arithmetic unit that outputs a value of 1 according to the input clock signal, and a second value generated based on the first value, the third set value, and the fourth set value. At least a second computing unit and a comparator that compares the second value with a fifth set value and outputs a high signal or a low signal as an output clock signal; The output clock obtained by dividing the input clock signal by a division ratio that is a value obtained by dividing the fifth set value by the first set value. A signal is output.

  According to the present invention, the output clock signal can be raised when the input clock signal falls. Thereby, an output clock signal obtained by dividing the input clock signal by an arbitrary division ratio can be obtained.

  According to the present invention, the output clock signal can be raised when the input clock signal falls. As a result, an output clock signal obtained by dividing the input clock signal by a division ratio represented by an arbitrary rational number can be obtained.

3 is a block diagram of a clock frequency divider circuit according to the first exemplary embodiment; FIG. FIG. 3 is a timing diagram illustrating an operation of the clock divider circuit according to the first exemplary embodiment; FIG. 6 is a block diagram of a clock divider circuit according to a second exemplary embodiment. FIG. 9 is a timing diagram illustrating an operation of the clock frequency divider circuit according to the second exemplary embodiment. 10 is a block diagram of a clock divider circuit disclosed in Patent Document 1. FIG. FIG. 10 is a timing diagram illustrating an operation of a clock frequency dividing circuit disclosed in Patent Document 1.

Embodiments of the present invention will be described below with reference to the drawings.
Embodiment 1
First, the clock frequency dividing circuit 100 according to the first embodiment will be described. The clock frequency dividing circuit 100 can obtain an output clock signal obtained by dividing the input clock signal by a frequency division ratio A / B, where A is a numerator setting value and B is a denominator setting value. That is, when the frequency of the input clock signal is FI and the frequency of the output clock signal is FO, the relationship of Expression (2) is established.

FO = FI × B / A (2)

Note that the numerator set value A and the denominator set value B are arbitrary natural numbers, and satisfy the conditions of B ≦ A and A> 0.

  The clock frequency dividing circuit 100 will be described. FIG. 1 is a block diagram showing a configuration of the clock frequency dividing circuit 100. As shown in FIG. 1, the clock frequency dividing circuit 100 includes a calculator 11, a calculator 12 a, and a comparator 108.

  The arithmetic unit 11 includes a register 101, a selector 103, and a subtracter 104.

  In the register 101, the reset signal 110 is input to the R terminal. An input clock signal 109 is input to the clock terminal. The calculator output value 120 is input to the D terminal. The register output value 113 is output from the Q terminal to the subtractor 104.

  The selector 103 receives a denominator set value 111 and a value 114 that is twice the denominator set value. An input clock signal 109 is input to the S terminal. Then, the selector output value 115 is output to the subtracter 104.

  The subtracter 104 receives the register output value 113 and the selector output value 115 and outputs the calculator output value 116 to the calculator 12a.

  The computing unit 12a is composed of an adder 106 and a selector 107.

  The adder 106 receives the calculator output value 116 and the value 117 that is twice the numerator set value, and outputs the adder output value 118 to the selector 107.

  The selector 107 receives the calculator output value 116 and the adder output value 118, and outputs the calculator output value 120 to the D terminal of the register 101 and the comparator 108.

  The comparator 108 receives the calculator output value 120 and the numerator set value 112 and outputs an output clock signal 121.

  Next, the operation of the clock frequency dividing circuit 100 will be described. The operation principle of the clock frequency dividing circuit 100 is that the output clock signal 121 obtained by dividing the input clock signal 109 by the frequency division ratio A / B can be obtained by repeating the following first to fourth processes. Here, (denominator setting value 111) = B and (numerator setting value 112) = A. Therefore, (a value 114 that is twice the denominator setting value) = 2B and (a value 117 that is twice the numerator setting value) = 2A.

  The first process is performed in the calculator 11. When the reset signal 110 is high, the register 101 records the value of the arithmetic unit output value 120 input to the register 101 and outputs it as the register output value 113 when the input clock signal 109 falls. . On the other hand, when the reset signal 110 is low, the register 101 records the value “0” and outputs it as the register output value 113.

  When the input clock signal 109 is low, the selector 103 outputs the denominator setting value 111 to the subtracter 104 as the selector output value 115. On the other hand, when the input clock signal 109 is high, the selector 103 outputs a value 114 that is twice the denominator setting value as the selector output value 115 to the subtractor 104.

  The subtractor 104 outputs a value obtained by subtracting the selector output value 115 from the register output value 113 to the arithmetic unit 12a as the arithmetic unit output value 116.

Therefore, when the input clock signal 109 is low, the arithmetic unit output value 116 is expressed by equation (3).

(Calculator output value 116) = (Register output value 113) − (Denominator set value 111)
= (Register output value 113) -B (3)

On the other hand, when the input clock signal 109 is high, the arithmetic unit output value 116 is expressed by equation (4).

(Calculator output value 116) = (Register output value 113) − (value 114 that is twice the denominator set value)
= (Register output value 113) -2B (4)

  The second process is performed in the computing unit 12a. The adder 106 outputs a value obtained by adding the value 117, which is twice the numerator set value, to the computing unit output value 116, as an adder output value 118, to the selector 107.

The selector 107 outputs the adder output value 118 as the calculator output value 120 when the calculator output value 116 is less than zero. Accordingly, the arithmetic unit output value 120 in this case is expressed by Expression (5).

(Calculator output value 120) = (Calculator output value 116) + (Value 117 that is twice the numerator set value)
= (Calculator output value 116) + 2A (5)

  On the other hand, when the calculator output value 116 is 0 or more, the selector 107 outputs the calculator output value 116 as the calculator output value 120.

  The third process is performed in the comparator 108. The comparator 108 compares the calculator output value 120 with the numerator set value 112, and the output clock signal 121 becomes high when (calculator output value 120) ≧ A. On the other hand, when (calculator output value 120) <A, the output clock signal 121 is low.

  In the fourth process, the register 101 records the calculator output value 120 when the input clock signal 109 falls. Then, the recorded value is output as a register output value 113.

  Further, the operation of the clock frequency dividing circuit 100 will be specifically described. FIG. 2 is a timing diagram in the case of generating an output clock signal obtained by dividing the input clock signal by 7/2 in the clock frequency dividing circuit 100. Regarding the operating condition of the clock divider circuit 100, the register output value 113, the selector output value 115, the calculator output value 116, the adder output value 118, the calculator output value 120, the denominator set value 111, and twice the denominator set value. The bit width of the value 114, the numerator set value 112, and the value 117 that is twice the numerator set value is 5 bits.

  Here, since the frequency division ratio is 7/2, A = 7 and B = 2. Therefore, the value of the denominator setting value 111 is “2”, the value of the numerator setting value 112 is “7”, the value 114 that is twice the denominator setting value is “4”, and the value 117 that is twice the numerator setting value is “14”. "

  Further, assuming that the half cycle of the input clock signal 109 is one cycle, the reset signal 110 is changed from low to high before the cycle T1 shown in FIG. 2 starts, and an initial value “0” is set in the register 101. Further, the reset signal 110 after the cycle T1 is high.

  The arithmetic unit output value 120 in each cycle shown in FIG. 2 is classified into the following classifications 1 to 4 according to the combination of the state of the input clock signal 109 and the state of the arithmetic unit output value 116. Each can be expressed using mathematical formulas.

  Class 1 is a case where the input clock signal 109 is high and the arithmetic unit output value 116 is less than 0, which corresponds to the cycles T1, T7 and T15 shown in FIG. Here, the operation will be described by taking the cycle T1 as an example.

  The calculator 11 performs the first process. Here, since the initial value of the register 101 is “0”, the register output value is “0”. Therefore, the arithmetic unit output value 116 is “−4” according to the equation (4).

  The calculator 12a performs the second process. Since the calculator output value 116 is “−4”, the calculator output value 120 is “10” according to the equation (5).

That is, the arithmetic unit output value 120 in category 1 is obtained by subtracting “4” that is a value 114 that is twice the denominator setting value from the register output value 113, and further, “14” that is a value 117 that is twice the numerator setting value. Since it is the added value, it is expressed by equation (6).

(Calculator output value 120) = (Register output value 113) +10 (6)

  Class 2 is a case where the input clock signal 109 is low and the arithmetic unit output value 116 is 0 or more, and the cycles T2, T4, T6, T8, T10, T12 and T16 shown in FIG. Here, the operation will be described by taking the cycle T2 as an example.

  The calculator 11 performs the first process. Here, since the value recorded in the register 101 is “10”, the register output value 113 is “10”. Therefore, the calculator output value 116 is “8” according to the equation (3).

  The calculator 12a performs the second process. Since the calculator output value 116 is “8”, the calculator output value 120 is also “8”.

That is, the arithmetic unit output value 120 in category 2 is a value obtained by subtracting “2”, which is the denominator setting value 111, from the register output value 113, and therefore is represented by Expression (7).

(Calculator output value 120) = (Register output value 113) -2 (7)

  The classification 3 is a case where the input clock signal 109 is high and the arithmetic unit output value 116 is 0 or more, and corresponds to cycles T3, T5, T9, T11, and T13 shown in FIG. Here, the operation will be described by taking the cycle T3 as an example.

  The calculator 11 performs the first process. Here, since the value recorded in the register 101 is “10”, the register output value 113 is “10”. Therefore, the calculator output value 116 is “6” according to the equation (4).

  The calculator 12a performs the second process. Since the value of the calculator output value 116 is “6”, the calculator output value 120 is also “6”.

That is, the arithmetic unit output value 120 in category 3 is a value obtained by subtracting “4”, which is a value 114 that is twice the denominator setting value, from the register output value 113, and therefore is represented by Expression (8).

(Calculator output value 120) = (Register output value 113) -4 (8)

  Class 4 is a case where the input clock signal 109 is low and the arithmetic unit output value 116 is less than 0, which corresponds to the cycle T14 shown in FIG. Hereinafter, the operation will be described by taking the cycle T14 as an example.

  The calculator 11 performs the first process. Here, since the value recorded in the register 101 is “0”, the register output value 113 is “0”. Therefore, the calculator output value 116 is “−2” according to the equation (3).

  The calculator 12a performs the second process. Since the calculator output value 116 is “−2”, the calculator output value 120 is “12” according to the equation (5).

That is, the arithmetic unit output value 120 in classification 4 is a value obtained by subtracting “2” that is the denominator setting value 111 from the register output value 113 and adding “14” that is a value 117 that is twice the numerator setting value. Therefore, it is expressed by equation (9).

(Calculator output value 120) = (Register output value 113) +12 (9)

  Next, the operation in each cycle will be described. First, in the cycle T1, as exemplified in the description of the classification 1, the arithmetic unit output value 120 is “10”. Since the third processing is performed by the comparator 108 ((10) that is the arithmetic unit output value 120)> (7 that is the numerator setting value 112), the output clock signal 121 becomes high.

  In the next cycle T2, a classification 2 operation is performed. As illustrated in the description of the classification 2, the value of the arithmetic unit output value 120 is “8”. Since the third processing is performed by the comparator 108 ((8) that is the arithmetic unit output value 120)> (“7” that is the numerator setting value 112), the output clock signal 121 becomes high.

  In the next cycle T3, the operation of classification 3 is performed. As illustrated in the explanation of the classification 3, the value of the arithmetic unit output value 120 is “6”. Since the third processing is performed by the comparator 108 ((6) which is the arithmetic unit output value 120) <(7 which is the numerator setting value 112), the output clock signal 121 becomes low.

  In the next cycle T4, the operation of classification 2 is performed. Since “6” is recorded in the register 101, the value of the arithmetic unit output value 120 is “4” from the equation (7). Since the third processing is performed by the comparator 108 ((4) as the calculator output value 120) <(7 as the numerator setting value 112), the output clock signal 121 becomes low.

  In the next cycle T5, the operation of classification 3 is performed. Since “6” is recorded in the register 101, the value of the calculator output value 120 is “2” from the equation (8). Since the third processing is performed by the comparator 108 ((2) which is the arithmetic unit output value 120) <(7 which is the numerator setting value 112), the output clock signal 121 becomes low.

  In the next cycle T6, the operation of classification 2 is performed. Since “2” is recorded in the register 101, the value of the arithmetic unit output value 120 is “0” from the equation (7). The third processing is performed by the comparator 108, and (the calculator output value 120 is “0”) <(the numerator setting value 112 is “7”), so the output clock signal 121 is low.

  In the next cycle T7, the operation of classification 1 is performed. Since “2” is recorded in the register 101, the value of the arithmetic unit output value 120 is “12” from the equation (6). Since the third processing is performed by the comparator 108 ((12) that is the calculator output value 120)> (7 that is the numerator setting value 112), the output clock signal 121 becomes high.

  In the next cycle T8, the operation of classification 2 is performed. Since “12” is recorded in the register 101, the value of the arithmetic unit output value 120 is “10” from the equation (7). Since the third processing is performed by the comparator 108 ((10) that is the arithmetic unit output value 120)> (7 that is the numerator setting value 112), the output clock signal 121 becomes high.

  In the next cycle T9, the operation of classification 3 is performed. Since “12” is recorded in the register 101, the value of the arithmetic unit output value 120 is “8” according to the equation (8). Since the third processing is performed by the comparator 108 ((8) that is the arithmetic unit output value 120)> (“7” that is the numerator setting value 112), the output clock signal 121 becomes high.

  In the next cycle T10, the operation of classification 2 is performed. Since “8” is recorded in the register 101, the value of the arithmetic unit output value 120 is “6” from the equation (7). Since the third processing is performed by the comparator 108 ((6) which is the arithmetic unit output value 120) <(7 which is the numerator setting value 112), the output clock signal 121 becomes low.

  In the next cycle T11, the operation of classification 3 is performed. Since “8” is recorded in the register 101, the value of the arithmetic unit output value 120 is “4” from the equation (8). Since the third processing is performed by the comparator 108 ((4) as the calculator output value 120) <(7 as the numerator setting value 112), the output clock signal 121 becomes low.

  In the next cycle T12, the operation of classification 2 is performed. Since “4” is recorded in the register 101, the value of the arithmetic unit output value 120 is “2” from the equation (7). Since the third processing is performed by the comparator 108 ((2) which is the arithmetic unit output value 120) <(7 which is the numerator setting value 112), the output clock signal 121 becomes low.

  In the next cycle T13, the operation of classification 3 is performed. Since “4” is recorded in the register 101, the value of the arithmetic unit output value 120 is “0” from Expression (8). The third processing is performed by the comparator 108, and (the calculator output value 120 is “0”) <(the numerator setting value 112 is “7”), so the output clock signal 121 is low.

  In the next cycle T14, the operation of classification 4 is performed. As illustrated in the description of the classification 4, the value of the arithmetic unit output value 120 is “12”. Since the third processing is performed by the comparator 108 ((12) that is the calculator output value 120)> (7 that is the numerator setting value 112), the output clock signal 121 becomes high.

  Since the next cycle T15 is in the same state as the cycle T1, the operations of the cycles T1 to T14 are repeated in the subsequent cycles. Therefore, the output clock signal outputs a clock of one cycle divided by 7/2 during seven cycles of the input clock signal.

  Therefore, according to the clock frequency dividing circuit 100 of this configuration, the output clock signal can be raised when the input clock signal falls. As a result, an output clock signal obtained by dividing the input clock signal by a division ratio represented by an arbitrary rational number can be obtained.

Embodiment 2
A configuration of the clock frequency dividing circuit 200 according to the second exemplary embodiment will be described. FIG. 3 is a block diagram illustrating a configuration of the clock frequency dividing circuit 200. As shown in FIG. 3, the clock frequency dividing circuit 200 is provided with a computing unit 12b instead of the computing unit 12a in FIG.

  The arithmetic unit 12 b is configured by a selector 123 and an adder 125.

  The selector 123 receives a value 117 that is twice the numerator set value and a “0” value 122. The calculator output value 116 is input to the S terminal. Then, the selector output value 124 is output to the adder 125.

  The adder 125 receives the calculator output value 116 and the selector output value 124, and outputs the calculator output value 120 to the D terminal of the register 101 and the comparator 108. Other configurations are the same as those in FIG.

  Next, the operation of the clock frequency dividing circuit 200 will be described. The operation principle of the clock divider circuit 200 is that the output clock signal 121 obtained by dividing the input clock signal by the division ratio A / B can be obtained by repeating the following fifth to eighth processes.

  Since the fifth process is the same as the first process in the first embodiment, a description thereof will be omitted.

  The sixth process is performed in the calculator 12b. The selector 123 outputs the “0” value 122 as the selector output value 124 when the arithmetic unit output value 116 is 0 or more.

  On the other hand, when the calculator output value 116 is less than 0, the selector 123 outputs a value 117 that is twice the numerator set value as the selector output value 124.

  The adder 125 outputs a value obtained by adding the calculator output value 116 and the selector output value 124 as the calculator output value 120.

  That is, the arithmetic unit 12b outputs the arithmetic unit output value 116 as the arithmetic unit output value 120 when the arithmetic unit output value 116 is 0 or more.

  On the other hand, when the computing unit output value 116 is less than 0, the computing unit output value 120 represented by the above equation (5) is output.

  Accordingly, the sixth process and the second process according to the first embodiment perform the same process as a result.

  Since the seventh process is the same as the third process in the first embodiment, a description thereof will be omitted.

  Since the eighth process is the same as the fourth process in the first embodiment, a description thereof will be omitted.

  That is, the clock divider circuit 200 performs the same operation as the clock divider circuit 100 according to the first embodiment.

  Further, the operation of the clock frequency dividing circuit 200 will be specifically described. FIG. 4 is a timing chart in the case where the clock dividing circuit 200 generates an output clock signal obtained by dividing the input clock signal by 7/2. Regarding the operating condition of the clock frequency divider circuit 200, the bit width of the selector output value 124 and the 0 value 122 is 5 bits. Since other conditions are the same as those in the first embodiment, description thereof is omitted.

  The arithmetic unit output value 120 in each cycle is classified into classifications 5 to 8 depending on the combination of the state of the input clock signal 109 and the state of the arithmetic unit output value 116, and an equation is used for each classification. Can be expressed.

  Classification 5 is a case where the input clock signal 109 is high and the arithmetic unit output value 116 is less than 0, as in classification 1 in the first embodiment, and corresponds to cycles T1, T7, and T15 shown in FIG. Here, taking the cycle T1 as an example, an operation that differs in process from the first embodiment will be described.

  Since the calculator output value 116 is “−4”, the selector 123 outputs “14”, which is a value 117 that is twice the numerator set value, to the adder 125 as the selector output value 124.

  The adder 125 uses the value “10” obtained by adding “14” as the selector output value 124 to “−4” as the calculator output value 116 as the calculator output value 120, and sets the D in the comparator 108 and the register 101. Output to the terminal.

  That is, the arithmetic unit output value 120 in category 5 is obtained by subtracting “4”, which is a value 114 that is twice the denominator setting value, from the register output value 113 and further, “14” that is a value 117 that is twice the numerator setting value. Since it is the added value, it is expressed by the above-described equation (6). That is, classification 1 and classification 5 output the same arithmetic unit output value 120.

  Classification 6 is the case where the input clock signal 109 is low and the calculator output value 116 is 0 or more, as in classification 2 in the first embodiment, and the cycles T2, T4, T6, T8, T10, shown in FIG. T12 and T16 are applicable. Here, the operation different from that of the first embodiment will be described by taking the cycle T2 as an example.

  Since the calculator output value 116 is “8”, the selector 123 outputs “0” that is the zero value 122 to the adder 125 as the selector output value 124.

  The adder 125 adds a value “8” obtained by adding “0” that is the selector output value 124 to “8” that is the calculator output value 116 to the D terminal of the comparator 108 and the register 101 as the calculator output value 120. Output.

  That is, the arithmetic unit output value 120 in classification 6 is a value obtained by subtracting “2”, which is the denominator setting value 111, from the register output value 113, and thus is represented by the above-described equation (7). That is, classification 2 and classification 6 output the same arithmetic unit output value 120.

  The classification 7 is a case where the input clock signal 109 is high and the arithmetic unit output value 116 is 0 or more, as in the classification 3 in the first embodiment. The cycles T3, T5, T9, T11 and T13 shown in FIG. Applicable. Here, the operation different from that of the first embodiment will be described by taking the cycle T3 as an example.

  Since the calculator output value 116 is “6”, the selector 123 outputs “0” that is the zero value 122 to the adder 125 as the selector output value 124.

  The adder 125 adds the value “6” obtained by adding the value “0” of the selector output value 124 to the value “6” of the calculator output value 116 to the D terminal of the comparator 108 and the register 101 as the calculator output value 120. Output.

  That is, the arithmetic unit output value 120 in the classification 7 is a value obtained by subtracting “4”, which is the value 114 that is twice the denominator setting value, from the register output value 113, and is represented by the above-described equation (8). That is, classification 3 and classification 7 output the same arithmetic unit output value 120.

  Classification 8 is a case where the input clock signal 109 is low and the arithmetic unit output value 116 is less than 0, as in classification 4 in the first embodiment, and corresponds to cycle T14 shown in FIG. Here, the operation different from the process of the first embodiment will be described by taking the cycle T14 as an example.

  Since the calculator output value 116 is “−2”, the selector 123 outputs “14”, which is a value 117 that is twice the numerator set value, to the adder 125 as the selector output value 124.

  The adder 125 adds the value “12” obtained by adding the value “14” of the selector output value 124 to the value “−2” of the calculator output value 116 as the calculator output value 120, and the D terminal of the comparator 108 and the register 101. Output to.

  That is, the arithmetic unit output value 120 in classification 8 is a value obtained by subtracting “2” as the denominator setting value 111 from the register output value 113 and adding “14” as the value 117 that is twice the numerator setting value. Therefore, it is represented by the above-mentioned formula (9). That is, classification 4 and classification 8 output the same calculator output value 120.

  Next, the operation in each cycle will be described. First, in cycle T1, the operation of classification 5 is performed. Since “0” is recorded in the register 101, the value of the arithmetic unit output value 120 is “10” from the equation (6). The comparator 108 compares the computing unit output value 120 with the numerator set value 112 and (calculator output value 120 “10”)> (numerator set value 112 “7”). 121 goes high.

  In the next cycle T2, the operation of classification 6 is performed. Since “10” is recorded in the register 101, the value of the calculator output value 120 is “8” from the equation (7). The comparator 108 compares the arithmetic unit output value 120 with the numerator set value 112 and (the arithmetic unit output value 120 is “8”)> (numerator set value 112 is “7”). 121 goes high.

  In the next cycle T3, the operation of classification 7 is performed. Since “10” is recorded in the register 101, the value of the arithmetic unit output value 120 is “6” from the equation (8). The comparator 108 compares the arithmetic unit output value 120 with the numerator set value 112 and (calculator output value 120 “6”) <(numerator set value 112 “7”). 121 becomes low.

  In the next cycle T4, the operation of classification 6 is performed. Since “6” is recorded in the register 101, the value of the arithmetic unit output value 120 is “4” from the equation (7). The comparator 108 compares the calculator output value 120 with the numerator set value 112, and (the calculator output value 120 is “4”) <(numerator set value 112 is “7”). 121 becomes low.

  In the next cycle T5, the operation of classification 7 is performed. Since “6” is recorded in the register 101, the value of the calculator output value 120 is “2” from the equation (8). The comparator 108 compares the calculator output value 120 with the numerator set value 112, and (the calculator output value 120 is “2”) <(numerator set value 112 is “7”). 121 becomes low.

  In the next cycle T6, the operation of classification 6 is performed. Since “2” is recorded in the register 101, the value of the arithmetic unit output value 120 is “0” from the equation (7). The comparator 108 compares the calculator output value 120 with the numerator set value 112, and (the calculator output value 120 is “0”) <(numerator set value 112 is “7”). 121 becomes low.

  In the next cycle T7, the operation of classification 5 is performed. Since “2” is recorded in the register 101, the value of the arithmetic unit output value 120 is “12” from the equation (6). The comparator 108 compares the computing unit output value 120 with the numerator set value 112 and (calculator output value 120 “12”)> (numerator set value 112 “7”). 121 goes high.

  In the next cycle T8, the operation of classification 6 is performed. Since “12” is recorded in the register 101, the value of the arithmetic unit output value 120 is “10” from the equation (7). The comparator 108 compares the computing unit output value 120 with the numerator set value 112 and (calculator output value 120 “10”)> (numerator set value 112 “7”). 121 goes high.

  In the next cycle T9, the operation of classification 7 is performed. Since “12” is recorded in the register 101, the value of the arithmetic unit output value 120 is “8” according to the equation (8). The comparator 108 compares the arithmetic unit output value 120 with the numerator set value 112 and (the arithmetic unit output value 120 is “8”)> (numerator set value 112 is “7”). 121 goes high.

  In the next cycle T10, the operation of classification 6 is performed. Since “8” is recorded in the register 101, the value of the arithmetic unit output value 120 is “6” from the equation (7). The comparator 108 compares the arithmetic unit output value 120 with the numerator set value 112 and (calculator output value 120 “6”) <(numerator set value 112 “7”). 121 becomes low.

  In the next cycle T11, the operation of classification 7 is performed. Since “8” is recorded in the register 101, the value of the arithmetic unit output value 120 is “4” from the equation (8). The comparator 108 compares the calculator output value 120 with the numerator set value 112, and (the calculator output value 120 is “4”) <(numerator set value 112 is “7”). 121 becomes low.

  In the next cycle T12, the operation of classification 6 is performed. Since “4” is recorded in the register 101, the value of the arithmetic unit output value 120 is “2” from the equation (7). The comparator 108 compares the calculator output value 120 with the numerator set value 112, and (the calculator output value 120 is “2”) <(numerator set value 112 is “7”). 121 becomes low.

  In the next cycle T13, the operation of classification 7 is performed. Since “4” is recorded in the register 101, the value of the arithmetic unit output value 120 is “0” from Expression (8). The comparator 108 compares the calculator output value 120 with the numerator set value 112, and (the calculator output value 120 is “0”) <(numerator set value 112 is “7”). 121 becomes low.

  In the next cycle T14, the operation of classification 8 is performed. Since “0” is recorded in the register 101, the value of the arithmetic unit output value 120 is “12” from the equation (9). The comparator 108 compares the computing unit output value 120 with the numerator set value 112 and (calculator output value 120 “12”)> (numerator set value 112 “7”). 121 goes high.

  Since the next cycle T15 is in the same state as the cycle T1, cycles T1 to T14 are repeated in the subsequent cycles. Therefore, the output clock signal outputs a clock of one cycle divided by 7/2 during seven cycles of the input clock signal.

  Therefore, the calculator output value 120 in the clock divider circuit 200 is the same value as that of the clock divider circuit 100 according to the first exemplary embodiment.

  Therefore, according to the clock frequency dividing circuit 200 of this configuration, the output clock signal can be raised when the input clock signal falls. As a result, an output clock signal obtained by dividing the input clock signal by a division ratio represented by an arbitrary rational number can be obtained.

  Furthermore, according to the clock frequency dividing circuit 200 of this configuration, either the value 117 that is twice the numerator set value or the “0” value 122 is selected by the selector 123 and output to the adder 125. Therefore, since one of the inputs of the selector 123 can be set to “0”, the selector 123 can be configured by an AND circuit, and the number of circuit elements can be reduced as compared with the clock frequency dividing circuit 100 according to the first embodiment. Can do.

Other Embodiments The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit of the present invention. For example, the frequency division ratio is not limited to 7/2, and can take other values represented by rational numbers, such as 11/6 with A = 11 and B = 6.

  Further, the clock frequency dividing circuit is not limited to the above configuration. For example, as long as similar arithmetic processing can be performed, an arithmetic unit having another configuration may be used instead of the arithmetic unit 11. The same applies to the calculator 12a and the calculator 12b.

11 arithmetic unit 12a, 12b arithmetic unit 100 clock divider circuit 101 register 103 selector 104 subtractor 106 adder 107 selector 108 comparator 109 input clock signal 110 reset signal 111 denominator set value 112 numerator set value 113 register output value 114 denominator set A value that is twice the value 115 A selector output value 116 A calculator output value 117 A value that is twice the numerator set value 118 An adder output value 120 A calculator output value 121 An output clock signal 122 A “0” value 123 A selector 124 A selector output value 125 Adder 200 Clock divider circuit 300 Clock divider circuit 301 Input signal 302 Input clock signal 303 Output clock signal 304 Input signal 305 Selector output 306 Subtractor output signal 307 Selector 308 Adder 309 Register 310 Register output signal 311 Most significant bit output signal 312 Latch output signal 313 Latch 314 AND circuit 315 Adder output signal 316 Subtractor
317 Input signal 318 Reset signal 320 Input signal

Claims (11)

The value of the input signal is recorded in synchronization with the input clock signal, and the first value generated based on the input signal, the first set value, and the second set value is output according to the input clock signal. A first computing unit;
A second computing unit that outputs a second value generated based on the first value, the third set value, and the fourth set value;
A comparator that compares the second value with a fifth set value and outputs a high signal or a low signal as an output clock signal;
The second value is fed back to the first computing unit to become the value of the input signal,
A clock frequency dividing circuit that outputs the output clock signal obtained by dividing the input clock signal by a frequency dividing ratio that is a value obtained by dividing the fifth set value by the first set value. The comparator outputs a high signal as an output clock signal when the second value is greater than or equal to the fifth set value, and when the second value is smaller than the fifth set value. A low signal is output as the output clock signal,
The clock divider circuit according to claim 1. The first computing unit is:
When the input clock signal is a high signal, a value obtained by subtracting the first set value from the value of the input signal is output as the first value. When the input clock signal is a low signal, A value obtained by subtracting the second set value from the value of the input signal is output as the first value.
The clock divider circuit according to claim 1 or 2. The first computing unit is:
A register that records the value of the input signal in synchronization with the input clock signal and outputs the value of the input signal as a third value;
When the input clock signal is a low signal, the first set value is output as a fourth value, and when the input clock signal is a high signal, the second set value is output as the fourth value. A first selector that outputs as a value;
A subtracter that outputs a value obtained by subtracting the fourth value from the third value as the first value;
The clock divider circuit according to claim 3. The register is initialized by a reset signal and outputs a value “0” as the first value.
The clock divider circuit according to claim 4. The second computing unit is:
When the first value is less than the fourth set value, a value obtained by adding the third set value to the first value is output as the second value, and the first value is When the value is equal to or greater than the fourth set value, the first value is output as the second value.
The clock divider circuit according to claim 1. The second computing unit is:
A first adder that outputs a value obtained by adding the third set value to the first value as a fifth value;
When the first value is less than the fourth set value, the fifth value is output as the second value, and when the first value is greater than or equal to the fourth set value. Comprises a second selector that outputs the first value as the second value,
The clock divider circuit according to claim 6. The second computing unit is:
When the first value is less than the fourth set value, the third set value is output as a sixth value, and when the first value is greater than or equal to the fourth set value. A third selector for outputting the value “0” as the sixth value;
A second adder that outputs a value obtained by adding the sixth value to the first value as the second value;
The clock divider circuit according to claim 6. The second set value is twice the first set value,
The clock divider circuit according to claim 1. The third set value is twice the fifth set value,
The clock frequency dividing circuit according to claim 1. The fourth setting value is 0,
The clock frequency dividing circuit according to claim 1.

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