JPH11340818A - Pulse arithmetic processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide inexpensively a pulse arithmetic processing unit of a very high speed, where an 'integer of the unity or over within a range which is not larger than the denominator of a frequency division ratio' can be set, even to a numerator of the frequency division ratio freely and frequency division is controlled. SOLUTION: This pulse arithmetic processing unit is provided with a pulse input means 1, a pulse output means 2, a digital comparator 3, a logic circuit 4, a data selector 5, a digital adder/subtractor 6, a sum/difference data latch register 7 and an initial value setting means 3, frequency division ratio denominator data are set to 1st data D1, and frequency division ratio numerator data are set to 3rd data D3, and the processing unit can be made to output pulse signals having directivity in an input UP pulse signal S1 and an input DOWN pulse signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse arithmetic processing device for freely dividing the frequency and the number of pulses of a directional pulse signal in a digital signal processing device such as an NC machine tool.

[0002]

2. Description of the Related Art Recently, in digital signal processing apparatuses which have become more sophisticated and complicated, a pulse having directivity (for example, an UP pulse input to an up / down counter and a DO
In many cases, frequency division control of a WN pulse or the like is required.

[0003] Above all, in the case of frequency division control of a position sensor output signal in servo control of an NC machine tool or the like, it is required that the pulse signal frequency is as high as about 10 MHz at the maximum and that the time delay due to the frequency division is very small. You.

In the case of a rotary encoder generally used as a position sensor in servo control of an NC machine tool or the like, each time the axis of a servo motor rotates by an angle corresponding to the resolution of the position sensor, an UP is determined according to the rotation direction.
A pulse or a DOWN pulse is output.

[0005] By controlling the frequency division of this pulse by the pulse arithmetic processing unit, the same UP pulse and DOWN pulse as those obtained by changing the resolution of the position sensor can be obtained. The above is an example of the use of the pulse arithmetic processing device.

Hereinafter, a conventional pulse arithmetic processing device will be described. In FIG. 7, reference numeral 9 denotes an input UP pulse signal S1 at each rising edge of the clock signal S13 having a constant period.
It is determined whether or not the input DOWN pulse signal S2 has been input. If the input UP pulse signal S1 has been input, a count UP pulse signal S14 is output. If the input DOWN pulse signal S2 has been input, the countdown has occurred. This is an input pulse synchronization circuit that outputs a pulse signal S15.

Reference numeral 10 denotes a presettable up / down counter that performs an up / down counting operation with the count UP pulse signal S14 and the count DOWN pulse signal S15 and outputs count result data D16. Numeral 11 denotes a digital comparator which compares the count result data D16 with a preset frequency division ratio denominator data D1 and outputs a comparison result signal S16 indicating whether or not they match.

[0008] 12 is that the count result data D16 is'-
This is a negative detection digital comparator that outputs a comparison result signal S17 indicating whether or not the value is 1 'or less. Reference numeral 13 denotes the comparison result signal S16 and the comparison result signal S17
Is a timing pulse generating circuit that checks at each falling edge of the counter and generates a clear signal S18 and a preset signal S19 of the presettable up / down counter. The preset data D15 of the presettable up / down counter is set to a value obtained by subtracting 1 from the frequency division ratio denominator data D1.

The operation of the pulse arithmetic processing device configured as described above will be described below.

In FIG. 8, an input UP pulse signal S1 is inputted to an input pulse synchronizing circuit, and a frequency division ratio denominator data D1
FIG. 11 is a diagram showing an operation when “3” and preset data D15 are “2”. The input UP pulse signal S1 is synchronized with the rising edge of the clock signal S13 to count U
The signal is input to the presettable up / down counter 10 as a P signal S14.

As a result, the presettable counter 10 performs a count-up operation, and eventually the count result data D16 and the frequency division ratio denominator data D1 become equal, and the comparison result signal S16 is output.

Considering the timing at which the comparison result signal S16 changes, a count-up pulse signal S14 is generated as a result of the rise of the clock signal S13.
As a result, the presettable up / down counter 10 performs a count-up operation, and as a result, the digital comparator 11 generates a comparison result signal S16.

Therefore, the time delay from the rising edge of the clock signal S13 until the comparison result signal S16 finds a match corresponds to the delay time of those elements, and the delay time is from the rising edge to the falling edge of the clock signal S13. Designed smaller than time.

The comparison result signal S16 is checked by the timing pulse generation circuit 13 at each falling edge of the clock signal S13, and when the comparison result signal S16 indicates a coincident state, a clear signal S18 is generated.

Considering the operation before and after the generation of the clear signal S18, when the clear signal S18 is generated in synchronization with the falling edge of the clock signal S13, the count result data D16 becomes "0" as a result, and as a result, Indicates that the comparison result signal S16 does not match.

Here, the pulse width of the clear signal S18 is not less than the pulse width necessary for the clear operation of the presettable up / down counter 10, and the clock signal S13
Is designed to have a width sufficiently smaller than the time from the falling edge to the rising edge. Therefore, when the next count-up pulse signal S14 is input, the presettable up-down counter 10 starts the count-up operation, and the same operation is continued thereafter.

Here, it can be seen that the relationship of Equation 1 is established between the input UP pulse signal S1 and the clear signal S18. Therefore, the clear signal S18 is configured to be output as the output UP pulse signal S7.

(Formula 1) fou = fiu / D1 where fou = frequency of output UP pulse signal S7 fiu = frequency of input UP pulse signal S1 D1 = frequency-dividing ratio denominator data It can be seen that the frequency division control of the UP pulse signal can be performed.

Next, the operation when the input DOWN pulse S2 is input will be described. FIG. 9 shows an input DOWN input to the input pulse synchronization circuit in the conventional pulse processing device.
FIG. 11 is a diagram illustrating an operation when a pulse signal S2 is input, the frequency division ratio denominator data D1 is “3”, and the preset data D15 is “2”.

Since this operation can be easily understood from the description of FIG. 8, the detailed description is omitted. However, when the comparison result signal S17 of the negative detection digital comparator 12 indicates a coincidence state, the preset signal S19 becomes The difference is that the preset data D15 is generated and is preset in the presettable up / down counter 10.

Here, it can be seen that the relationship of Equation 2 is established between the input DOWN pulse signal S2 and the preset signal S19.

(Formula 2) fod = fid / D1 where fod = frequency of output DOWN pulse signal S8 fid = frequency of input DOWN pulse signal S2 D1 = frequency division ratio denominator data This preset signal S19 is output as DOWN pulse signal S8 It is configured to output as.

The above is the description of the operation of the conventional pulse arithmetic unit. The relation between the input and the output is expressed by the following equation (3) by summarizing the above.

(Formula 3) fout = fin / D1 where fout = output pulse frequency of the pulse arithmetic processing device fin = input pulse frequency of the pulse arithmetic processing device D1 = divider ratio denominator data

[0025]

However, in the above-mentioned conventional configuration, the denominator of the frequency division ratio can be freely changed within an integer range of 1 or more, but only one numerator of the frequency division ratio can be selected.

Therefore, the frequency division ratio essentially has a great restriction that only "one integer" can be set.

The present invention solves the above-mentioned conventional problems. The numerator of the frequency division ratio can be freely set to "an integer of 1 or more within a range not larger than the denominator of the frequency division ratio", and is very inexpensive and very cheap. An object of the present invention is to provide a pulse arithmetic processing device capable of high-speed frequency division control.

[0028]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides an input pulse signal and an input pulse signal which are synchronized with a clock signal having a fixed period by inputting an input UP pulse signal and an input DOWN pulse signal. A pulse input means for receiving an output pulse presence / absence signal and an output pulse direction signal, and outputting an output UP pulse signal, an output DOWN pulse signal, and a register holding timing signal in synchronization with the clock signal; A digital comparator that receives first preset data and second data, respectively, and outputs a comparison result signal with the register holding data; and outputs the comparison result signal, the input pulse presence / absence signal, and the input pulse direction signal. Input data selection signal, addition / subtraction selection command signal, output pulse presence / absence signal, and output pulse A logic circuit for uniquely outputting a first direction signal, a first data, a third data, a fourth data, a fifth data and a sixth data which always have a value of '0', respectively set in advance. And a data selector for selecting any one of the data selection signals and outputting selection result data according to the data selection signal, and adding or subtracting the selection result data and the register holding data in accordance with the addition / subtraction selection command signal to obtain addition / subtraction result data. A digital adder / subtractor to be output, initial value setting means for selecting predetermined tenth data and eleventh data by the input UP pulse signal and the input DOWN pulse signal and outputting arithmetic initial value data, The initial value data is used as a register initial value, and the addition / subtraction result data is held by the register holding timing signal. A data holding register that outputs data held by the data holding register.

By the above means, the input UP pulse signal S
1 and the input DOWN signal S2, the output UP pulse signal S7 and the output DOWN
An N pulse signal S8 can be obtained.

(Formula 4) fout = fin × D3 / D1, where fout = output pulse frequency of pulse arithmetic processing device fin = input pulse frequency of pulse arithmetic processing device D1 = division ratio denominator data D3 = division ratio numerator data D1 ≧ D3 In other words, in the conventional pulse arithmetic processing device, the frequency division ratio could only be set to “1/1”, whereas in the pulse arithmetic processing device according to the present invention, both the numerator and the denominator of the frequency division ratio were set. It can be varied and the division ratio can be set very finely.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to solve the above-mentioned problems, the present invention provides an input UP pulse signal and an input DOWN pulse signal, and outputs an input pulse presence / absence signal and an input pulse direction signal synchronized with a clock signal of a fixed period. Pulse input means for outputting, and pulse output means for receiving an output pulse presence / absence signal and an output pulse direction signal and outputting an output UP pulse signal, an output DOWN pulse signal, and a register holding timing signal in synchronization with the clock signal; A digital comparator for inputting preset first data and second data and outputting a comparison result signal with the register holding data; inputting the comparison result signal, the input pulse presence / absence signal, and the input pulse direction signal; Data selection signal, addition / subtraction selection command signal, output pulse presence / absence signal, and output pulse direction signal. And a logic circuit for uniquely outputting the first data, the third data, the fourth data, the fifth data, and the sixth data always having a value of '0', which are preset. A data selector for selecting one of the data according to the data selection signal and outputting selected result data, and adding or subtracting the selected result data and the register holding data according to the addition / subtraction selection command signal to output addition / subtraction result data. A digital adder / subtractor, which respectively sets the preset tenth data and eleventh data by the input UP pulse signal and the input DOWN
Initial value setting means for selecting and outputting operation initial value data by a pulse signal, data for setting the operation initial value data as a register initial value, holding the addition / subtraction result data by the register holding timing signal, and outputting the register holding data This is a pulse arithmetic processing device provided with a holding register.

[0032] In addition, the first set in advance respectively.
This is a pulse arithmetic processing apparatus in which one of data 0 and the eleventh data is set to '0', and the other data is a value obtained by subtracting third data from first data.

As described above, both the numerator and the denominator of the pulse division ratio can be varied, and the division ratio can be set very finely.

Further, it is possible to match the output pattern of the pulse output between the case where the pulse division is started with the input UP pulse signal and the case where the pulse division is started with the input DOWN pulse signal.

[0035]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) In FIG. 1, 1 is an input UP
A pulse input means for receiving a pulse signal S1 and an input DOWN pulse signal S2 and outputting an input pulse presence / absence signal S3 and an input pulse direction signal S4 synchronized with a clock signal S13 having a fixed period; A pulse output means for receiving a direction signal S10 and outputting an output UP pulse signal S7, an output DOWN pulse signal S8 and a register holding timing signal S12 in synchronization with the clock signal S13, respectively, is a first data set in advance. A digital comparator which receives the frequency division ratio denominator data D1 and the second data D2 and outputs a comparison result signal S5 with the register holding data D8, and 4 outputs a comparison result signal S5, an input pulse presence / absence signal S3, and an input pulse direction. The signal S4 is input, and the data selection signal S6 and the addition / subtraction selection command signal S11 are output. A logic circuit having the logic shown in Table 1 for uniquely outputting the pulse presence / absence signal S9 and the output pulse direction signal S10, and a division ratio denominator data D1 set in advance and a division ratio numerator as the third data, respectively. The data D3, the fourth data D4, the fifth data D5 and the sixth data D6 always having a value of "0" are inputted, and one of them is selected by the data selection signal S6, and the selection result data D
7 is a data selector that outputs 7 and 6 is selection result data D7.
And the register holding data D8 by the addition / subtraction selection command signal S11.
Is a digital adder / subtracter that outputs addition / subtraction result data D9 by adding or subtracting according to the following equation.
2 as a register initial value and a register holding timing signal S
12 is an addition / subtraction data holding register for holding the addition / subtraction result data D9 and outputting the register holding data D8. It is an initial value setting means which selects and outputs operation initial value data D12 in S2.

[0037]

[Table 1]

FIG. 2 is a diagram showing an example in which an UP pulse or a DOWN pulse is inputted from the input of an UP pulse or a DOWN pulse having the configuration shown in FIG.
This shows the concept of arithmetic processing up to the output of a pulse.

The operation of the pulse arithmetic processing device configured as described above will be described with reference to FIG.

FIG. 3 shows that the input UP pulse signal S1 is input to the pulse input means 1 and the frequency division ratio denominator data D1 is "4".
It is a figure which shows operation | movement in case frequency division ratio numerator data D3 is "3". It is assumed that the second data D2, the fourth data D4, and the fifth data D5 are set to the data shown in Expression 5.

(Equation 5) D1 = frequency-dividing ratio denominator data D2 = 0 D3 = frequency-dividing ratio numerator data D4 = D3 + D1 D5 = D3-D1 D6 = always '0' However, D1 ≧ D3 First, the initial state of the register holding data D8 Consider the state as '0'. The pulse input means 1 receives the input UP pulse signal S1 and the input DO signal every rising edge of the clock signal S13.
It is determined whether the WN pulse signal S2 has been input or not, and the input pulse presence signal S3 and the input pulse direction signal S4 are updated according to the result.

Here, considering the state before the input UP pulse signal S1 is input, the input pulse presence / absence signal S3 is considered.
And the input pulse direction signal S4 indicates the state “B” of “no input pulse”, and the comparison result signal S5 indicates “D2 ≦ D8 <D
1 "state" F ". Therefore, based on the states of S3, S4, and S5, the logic circuit 4 indicates that the data selection signal S6 is "select D6" state 'N', the output pulse presence / absence signal S9, and the output pulse direction signal S10 are "output" according to Table 1. The state "Q" of "N" and the addition / subtraction selection command signal S11 become the state "I" of "Add or subtract", and as a result, "0" is output to D7.

Since D8 is "0" from the initial state, D8
7 and D8 are added / subtracted result data D9 whether added or subtracted.
Is '0'.

The register holding timing signal S12 is input to the addition / subtraction data holding register 7 at each rising edge of the clock signal S13, and the addition / subtraction result data is taken in to update the data. However, in this state, '0' is always held, and '0' is output to D8.

Next, the input UP pulse signal S1 is input and the rising edge of the clock signal S13 (point i in FIG. 3).
When the input pulse presence / absence signal S3 and the input pulse direction signal S4 change to the state "A" of "the presence of an input pulse in the UP direction" in synchronization with the state "F" of the comparison result signal S5 of "D2≤D8 <D1" , The logic circuit 4 uses S3, S4, and S5 to change the data selection signal S6 to "D3
Select ", the output pulse presence / absence signal S9 and the output pulse direction signal S10 are maintained in the" do not output "state 'Q', and the addition / subtraction selection command signal S11
Changes to the state "G" of "add". As a result, D
7 = D3 = '3', and as a result,
D7 is added to D8, and D9 = '3'. The above is the signal processing paths (a) and (f) of FIG.

Next, in this state, the clock signal S1
When the register holding timing signal S12 is generated in synchronization with the next rising edge (point j in FIG. 3), the addition / subtraction data holding register 7 takes in and holds D9, and D8 changes from '0' to '3'. . D8 is compared with D1 and D2 by the digital comparator 3, and as a result, the comparison result signal S5 maintains the state “F” of “D2 ≦ D8 <D1”.

At the same time, the input pulse existence signal S3 and the input pulse direction signal S4 are also updated in synchronization with the rising edge of the clock signal S13, and the input pulse existence signal S3 and the input pulse direction signal S4 become "no input pulse".
State 'B'.

Based on the states of S3 and S4 and the state of S5, the logic circuit 4 changes the data selection signal S6 to the "select D6" state "N" according to Table 1, and outputs the output pulse presence / absence signal S9 and the output signal. The pulse direction signal S10 maintains the state “Q” of “do not output”, and the addition / subtraction selection instruction signal S
11 changes to the state "I" of "add or subtract". As a result, D7 = '0', and as a result, D7 is added to D8, and D9 = '3'. The above are the signal processing paths (c) and (f) in FIG.

Here, the output pulse presence / absence signal S9 and the output pulse direction signal S10 are read by the pulse output means 2 in synchronization with the rising edge of the clock signal S13.
The output UP pulse signal S7 and the output DOWN pulse signal S8 are output according to the state of S10. The current state is S
9. Since S10 is in the "do not output" state 'Q', no pulse is output.

Thereafter, until the next input UP pulse signal S1 is input, D8 is '3' and S5 is "D2≤D8 <D
The state “F” of “1”, S9 and S10 maintain the state “Q” of “do not output”.

When the next input UP pulse S1 is inputted, at the rising edge of the clock signal S13 (point k in FIG. 3), the input pulse presence signal S3 and the input pulse direction signal S4
Becomes the state “A” of “there is an input pulse in the UP direction”. Based on the states of S3 and S4 and the state of S5, the logic circuit 4 sets the data selection signal S6 to the "select D3" state 'K' according to (Table 1), and the output pulse presence / absence signal S9
The output pulse direction signal S10 maintains the state "Q" of "do not output", and the addition / subtraction selection command signal S11 changes to the state "G" of "add". As a result, D7 =
The state becomes '3', and as a result, D9 = D8
+ D7 = '3' + '3' = '6' The above is the signal processing paths (a) and (f) of FIG.

Next, when D8 = '6' in synchronization with the next rising edge of the clock signal S13 (point l in FIG. 3), as a result, S5 is in the state of "D2≤D8" and "D1≤D8". D '. At the same time, in synchronization with the rising edge of the clock signal S13, the input pulse presence / absence signal S3 and the input pulse direction signal S4 change to the state “B” of “no input pulse”, and the logic circuit 4 is turned on from the states of S3, S4 and S5. 1, the data selection signal S6 becomes the state "J" of "select D1", the output pulse presence / absence signal S9 and the output pulse direction signal S10 become the state "O" of "output an UP pulse", and the addition / subtraction selection command is issued. The signal S11 changes to the state "H" of "subtract". As a result, D7
= '4' and D9 = D8-D7 = '6'-'4' =
It becomes '2'. The above is the signal processing path (c) of FIG.
(D).

Next, when the output pulse presence / absence signal S9 and the output pulse direction signal S10 are read into the pulse output means 2 in synchronization with the next rising edge (point m in FIG. 3) of the clock signal S13, the output UP pulse signal S7 is output.

Thereafter, by continuing the operation similarly,
When 4 pulses of input UP pulse signal S1 are input, output UP
An operation is performed in which three pulse signals S7 are output, and the relationship of Expression 6 is established between the input UP pulse signal S1 and the output UP pulse signal S7.

(Formula 6) fou = fiu × D3 / D1 where fou = frequency of output UP pulse signal S7 fiu = frequency of input UP pulse signal S1 D1 = division ratio denominator data D3 = division ratio numerator data D1 ≧ D3 Similarly, when the case where the input DOWN pulse signal S2 is input is considered, it can be seen that the relationship of Expression 7 holds between the input DOWN pulse signal S2 and the output DOWN pulse signal S8.

(Formula 7) fod = fid × D3 / D1 where fod = frequency of output DOWN pulse signal S8 fid = frequency of input DOWN pulse signal S2 D1 = division ratio denominator data D3 = division ratio numerator data D1 ≧ D3 FIG. 4 is a diagram showing an operation when the input UP pulse signal S1 and the input DOWN pulse signal S2 are input at high speed. In the above description, it goes without saying that the rising edge of the clock signal S13 may be the falling edge of the clock signal S13.

The above is the description of the operation of the pulse arithmetic processing apparatus according to the first embodiment of the present invention.

(Embodiment 2) FIGS. 5 and 6 show the operation of the embodiment using the initial value setting means 8 in FIG.

FIG. 5 shows that the frequency division ratio denominator data D1 described in the first embodiment is "4" and the frequency division ratio numerator data D3 is "4" for the output signal of the rotary encoder treated as an input signal to the pulse arithmetic processing device. This is an example of pulse calculation processing in the case of '3'.

The output signal from the rotary encoder is 1
It is composed of two-phase pulse trains A and B that output a predetermined number of pulses at a rotation of 360 °, and a Z-phase that outputs one pulse. When the encoder shaft rotates CW (clockwise rotation), FIG.
At the time of CCW rotation (counterclockwise rotation), the signal of FIG.

When the input UP pulse signal S1 or the input DOWN pulse signal S2 is generated according to the signal edges of the A-phase and the B-phase and the rotation direction, the output UP is calculated by the above-described pulse calculation processing.
The pulse signal S7 or the output DOWN pulse signal S8 is obtained as shown in FIG.

It should be noted that the output pattern of the output UP pulse signal S7 when the pulse calculation is started with the UP pulse signal S1 starting from the point X in FIG. 5 and the DOWN pulse signal S2 starting from the X point , The consistency with the output pattern of the output DOWN pulse signal S8, that is, pulse numbers 0, 1, 2,... N in FIG.
It is important that a pulse is output at the position of the same pulse number for the UP pulse S1 or the DOWN pulse S2 up to -1. If this consistency is not ensured, a shift in the pulse output position occurs depending on the rotation direction.

FIG. 6 shows an initial value setting means 8 according to the present invention.
FIG. 9 is a diagram showing an operation of the embodiment for realizing the consistency of the pulse output by using the second data D2 and the fourth data D;
It is assumed that the data shown in Formula 8 is set in the fourth data D5, the tenth data D10, and the eleventh data D11.

(Equation 8) D1 = frequency-dividing ratio denominator data D2 = 0 D3 = frequency-dividing ratio numerator data D4 = D3 + D1 D5 = D3-D1 D6 = always '0' D10 = 0 (pulse operation starts when an UP pulse is input. D11 = D1−D3 (Initial value when pulse calculation start is DOWN pulse input) D1 ≧ D3 However, FIG. 3A shows an operation example during (a) CW rotation in FIG.
The operation at the time of (b) CCW rotation will be described with reference to FIG.

First, considering the state until the input DOWN pulse signal S2 is inputted, the input pulse presence / absence signal S
3 and the input pulse direction signal S4 indicate the state “B” of “no input pulse”, and the comparison result signal S5 indicates “D2 ≦ D8 <D
1 "state" F ". Therefore, from S3, S4 and S5, the logic circuit 4 sets the data selection signal S6 to the state "N" of "select D6" according to Table 1, and the output pulse presence / absence signal S
9 and the output pulse direction signal S10 are in the state "Q" of "do not output", and the addition / subtraction selection command signal S11 is in the state of "I" of "addition or subtraction". As a result, D7 is "0", D
Since 8 is “0” from the initial state, the addition / subtraction result data D9 is “0” regardless of whether D7 and D8 are added or subtracted.

Next, when the input DOWN pulse signal S2 is input, the initial value setting means 8 detects that S2 has been input and outputs the eleventh data D11, that is, D1-D3 = '4'-.
'3' = '1' is selected, and '1' is output as the computation initial value data D12.

Next, in this state, the clock signal S1
When the register holding timing signal S12 is generated in synchronization with the rising edge of point 3 (point i in FIG. 6), the addition / subtraction data holding register 7 takes in and holds the operation initial value data D12, that is, "1" as the register initial value, and D8 holds "1". It changes from “0” to “1”. The digital comparator 3 compares D8 with D1 and D2, and as a result, the comparison result signal S5 maintains the state “F” of “D2 ≦ D8 <D1”.

At the same time, the input pulse presence / absence signal S3 and the input pulse direction signal S4 are updated in synchronization with the rising edge of the clock signal S13 and change to the state "C" of "input pulse in the DOWN direction". The logic circuit 4 follows (Table 1) and the data selection signal S6 is "D
3 "state" K ", the output pulse presence / absence signal S9 and the output pulse direction signal S10 are" do not output "state" Q ", and the addition / subtraction selection command signal S11 is" subtract "state. H '. As a result, D7 = D3
= '3', D7 is subtracted from D8, and D9 = D8-
D7 = '1'-'3' = '-2'. The above is the signal processing paths (b) and (f) of FIG.

Next, in this state, the clock signal S1
When the register holding timing signal S12 is generated in synchronization with the next rising edge (point j in FIG. 6), the addition / subtraction data holding register 7 takes in and holds D9, and D8 changes from "1" to "-2". . D8 and D1, D2
Are compared by the digital comparator 3, and as a result, the comparison result signal S5 becomes "D8 <D2", "D8 <D
1 "state" E ".

At the same time, when the input pulse presence / absence signal S3 and the input pulse direction signal S4 change to the state “B” with no input pulse in synchronization with the rising edge of the clock signal S13, the logic circuit 4 starts from S3, S4 and S5. According to (Table 1), the data selection signal S6 changes to the state “J” of “select D1”, and the output pulse presence / absence signal S9 and the output pulse direction signal S10 change to the state “P” of “output a DOWN pulse”. The addition / subtraction selection command signal S11 is "add"
To state 'G'. As a result, D7 = D1 =
It becomes '4' and D9 = D8 + D7 = '-2' + '4' =
It becomes '2'. The above is the signal processing path (c) of FIG.
(E).

Next, in synchronization with the next rising edge of the clock signal S13 (point k in FIG. 6), the output pulse presence / absence signal S9 and the output pulse direction signal S10 are read by the pulse output means 2 and the output UP pulse signal S7 Is output.

Thereafter, by continuing the operation in the same manner,
The operation shown in FIG. As described above, since both the denominator and the numerator of the frequency division ratio can be varied, the frequency division ratio can be set very precisely, and the consistency of the output pattern of the pulse calculation processing pattern during CW rotation and CCW rotation can be ensured. A high-speed and inexpensive pulse processing device can be realized.

[0073]

As is clear from the above embodiment, the present invention can set both the denominator and the numerator of the frequency division ratio very finely, so that the frequency division ratio can be set very finely. The present invention can provide an inexpensive pulse arithmetic processing device that can satisfy the requirements and operates at a very high speed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a pulse arithmetic processing device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating the operation of the pulse arithmetic processing device according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating the operation of the pulse arithmetic processing device according to the first embodiment of the present invention.

FIG. 4 is a diagram illustrating the operation of the pulse arithmetic processing device according to the first embodiment of the present invention.

FIG. 5 is a diagram illustrating the operation of the pulse arithmetic processing device according to the second embodiment of the present invention.

FIG. 6 is an explanatory operation diagram of a pulse calculation processing device according to a second embodiment of the present invention.

FIG. 7 is a diagram illustrating the operation of a conventional pulse arithmetic processing device.

FIG. 8 is a diagram illustrating the operation of a conventional pulse arithmetic processing device.

FIG. 9 is a diagram illustrating the operation of a conventional pulse arithmetic processing device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 pulse input means 2 pulse output means 3 digital comparator 4 logic circuit 5 data selector 6 digital adder 7 addition / subtraction data holding register 8 initial value setting means 9 input pulse synchronization circuit D1 first data (division ratio denominator data) D2 Data D2 Third data (frequency division ratio numerator data) D4 Fourth data D5 Fifth data D6 Sixth data D7 Selection result data D8 Register holding data D9 Addition / subtraction result data D10 Tenth data D11 Eleventh D12 Calculation initial value data S1 Input UP pulse signal S2 Input DOWN pulse signal S3 Input pulse presence / absence signal S4 Input pulse direction signal S5 Comparison result signal S6 Data selection signal S7 Output UP pulse signal S8 Output DOWN pulse signal S9 Output pulse presence / absence signal

Claims (2)

[Claims] 1. A pulse input means for receiving an input UP pulse signal and an input DOWN pulse signal and outputting an input pulse presence / absence signal and an input pulse direction signal synchronized with a clock signal having a fixed period, an output pulse presence / absence signal and an output pulse Pulse output means for receiving a direction signal and outputting an output UP pulse signal, an output DOWN pulse signal, and a register holding timing signal in synchronization with the clock signal; first and second preset data; And a digital comparator for receiving a comparison result signal, the input pulse presence / absence signal, and the input pulse direction signal to input a data selection signal, an addition / subtraction selection command signal, and the output pulse. A logic circuit for uniquely outputting the presence / absence signal and the output pulse direction signal, The first data, the third data, the fourth data, the fifth data, and the sixth data, which always have a value of '0', are inputted and any one of them is set by the data selection signal. And a digital adder / subtractor for adding or subtracting the selection result data and the register holding data according to the addition / subtraction selection command signal to output addition / subtraction result data, respectively, Initial value setting means for selecting the tenth data and the eleventh data by the input UP pulse signal and the input DOWN pulse signal and outputting operation initial value data; the operation initial value data as a register initial value; A data holding register that holds the addition / subtraction result data by a timing signal and outputs the register holding data. Pulse processing unit. 2. One of the pre-set tenth data and eleventh data is set to "0".
The pulse arithmetic processing device according to claim 1, wherein the other data is a value obtained by subtracting the third data from the first data.