JPH05188066A - Servo motor speed detecting device - Google Patents

Abstract

PURPOSE:To provide a speed detecting device capable of detecting the rotating speed of a servo motor from a low speed region to a high speed region with accuracy. CONSTITUTION:Output pulses from a pulse encoder is divided by a divider 12. A preset register 19 given the divider 12 dividing ratio information predetermined according to the output pulse number from the purse encoder in the preceding sampling cycle at the starting time of each sampling cycle. The clock pulse number in each encoder dividing pulse cycle from the divider is counted by a clock pulse counter 15, and a CPU 23 computes the rotating speed of a servo motor on the basis of the dividing ratio information of the divider 12 and the count value of the clock pulse counter 15 on the latest encoder dividing pulse cycle in the sampling cycle.

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a speed detecting device for a servo motor, which detects the rotational speed of the servo motor based on the output pulse of a pulse encoder attached to the servo motor.

[0002]

2. Description of the Related Art An example of a conventional speed detecting device of this type is
It is disclosed in JP-A-59-160766. This conventional speed detection device includes a counter that counts the period of each output pulse from a pulse encoder attached to a servomotor using a clock pulse that is generated at a constant period, and a register that stores the counted output pulse period. And a memory that stores the reciprocal of the output pulse cycle in advance as a data table.The latest encoder output pulse cycle in a fixed sampling cycle is read from the register, and the encoder output pulse cycle is stored in the address of the memory. The conversion is performed and the reciprocal of the output pulse period is read from this memory to detect the rotation speed of the servo motor.

[0003]

However, in the above-described conventional speed detecting device, the period of the output pulse of the pulse encoder is measured by using the number of clock pulses of a constant period, so that the servo motor is operated at a low speed. The speed detection accuracy is good when rotating in the area, but in the high speed area, the number of clock pulses becomes small, so that the speed detection accuracy is deteriorated.

The present invention has been made to solve the above-mentioned drawbacks, and provides a speed detecting device for a servo motor capable of accurately detecting the rotation speed of the servo motor from a low speed region to a high speed region. To aim.

[0005]

In order to achieve the above object, a speed detecting device for a servo motor according to the invention of claim 1 rotates a servo motor based on an output pulse of a pulse encoder attached to the servo motor. In a speed detection device for detecting a speed, at the start of each sampling cycle, frequency division ratio information that determines the frequency division ratio in the sampling cycle is provided by the frequency division ratio information setting means, and the frequency division ratio of the output pulse from the pulse encoder is divided. A frequency divider, and a clock pulse counter for counting the number of clock pulses in the period of the encoder frequency division pulse from the frequency divider,
Arithmetic processing means for calculating the rotation speed of the servomotor based on the frequency division ratio information of the frequency divider and the clock pulse count value of the clock pulse counter for the latest encoder frequency division pulse period in the sampling period, The frequency division ratio information setting means is preset according to an output pulse counter for counting the number of output pulses from the pulse encoder in the sampling cycle and an encoder output pulse count value in the previous sampling cycle counted by the output pulse counter. Means for setting the obtained frequency division ratio information in the frequency divider.

According to a second aspect of the present invention, there is provided a servo motor speed detecting device which detects a rotation speed of a servo motor based on an output pulse of a pulse encoder attached to the servo motor. At the time of starting, frequency division ratio information that determines the frequency division ratio in the sampling cycle is given by the frequency division ratio information setting means, and a frequency divider for dividing the output pulse from the pulse encoder and an encoder frequency division from the frequency divider. Based on a clock pulse counter that counts the number of clock pulses in a pulse cycle, frequency division ratio information of the frequency divider, and a clock pulse count value of the clock pulse counter for the latest encoder frequency division pulse cycle in the sampling cycle And a processing unit for calculating the rotation speed of the servo motor, The frequency division ratio information setting means stores a plurality of frequency division ratio information, a frequency division pulse counter for counting the number of encoder frequency division pulses from the frequency divider in the sampling cycle, and a predetermined frequency division pulse counter. Comparison means for comparing the set value with the encoder divided pulse count value in the previous sampling cycle counted by the divided pulse counter, and this comparing means determines that the previous encoder divided pulse count value is larger than the set value. If it is determined that the frequency division ratio information is a frequency division ratio smaller than the previous frequency division ratio from the storage means, if the previous encoder frequency division pulse count value is determined to be less than the set value,
Frequency division ratio information selection means for selecting frequency division ratio information having a frequency division ratio larger than the previous frequency division ratio, and frequency division ratio information selected by the frequency division ratio information selection means to the frequency divider. And means for setting.

[0007]

In the speed detecting device for the servo motor according to the first and second aspects of the invention, the output pulse from the pulse encoder is divided by the divider. At the start of each sampling cycle, the frequency division ratio information setting means provides the frequency divider with frequency division ratio information that determines the frequency division ratio in the sampling cycle. In this case, in the speed detecting device according to the invention of claim 1, the frequency division ratio information set in advance is set according to the number of output pulses from the pulse encoder in the previous sampling cycle. Further, in the speed detecting device according to the second aspect of the invention, the frequency division ratio information is set based on the number of encoder frequency division pulses in the previous sampling cycle. The clock pulse counter counts the number of clock pulses in the cycle of each encoder frequency division pulse from the frequency divider. Then, the arithmetic processing means calculates the rotation speed of the servo motor based on the frequency division ratio information of the frequency divider and the clock pulse count value of the clock pulse counter for the latest encoder frequency division pulse cycle in the sampling cycle. .. Therefore, the output pulse from the pulse encoder is divided by the frequency divider, and the rotation speed of the servo motor is calculated based on the frequency division ratio information of the frequency divider and the number of clock pulses for the latest encoder frequency division pulse period in the sampling period. Therefore, the rotation speed of the servo motor can be accurately detected from the low speed region to the high speed region.

[0008]

EXAMPLES The present invention will be described below based on examples. 1 is a block diagram showing the configuration of a speed detecting device for a servo motor according to an embodiment of the invention of claim 1, and FIG.
6 is a diagram for explaining the operation of the speed detection device shown in FIG.

In FIG. 1, 11 is a waveform shaping circuit,
A pulse signal from a pulse encoder PG connected to a shaft of a servo motor (not shown) is shaped by a waveform shaping circuit 11 and is input to a frequency divider (programmable frequency divider) 12 as an encoder output pulse signal E _P to be divided. While being divided, it is also configured to be input to an output pulse counter 13 which constitutes a division ratio information setting means described later. Encoder division pulse signal EB _P from the frequency divider 12 is input to the first flip-flop 14 (in (a) refer to FIG. 2). A clock pulse signal C _P from a clock pulse generator (not shown) is also input to the first flip-flop 14 (see FIG. 2B).

[0010] The first flip-flop 14, the clock pulse signal C in the encoder division pulse signal EB _P at input
_In synchronization with the rising edge of _P , a set encoder pulse signal (hereinafter referred to as a SETEP signal) and a reset encoder pulse signal (hereinafter referred to as an RSTEP signal) to be given to the clock pulse counter 15 are generated ( 2 (c) and (d)).

The clock pulse counter 15 to which the clock pulse signal C _P is input is reset in synchronization with the rising edge of the RSTEP signal described above, and in the period corresponding to the cycle of the encoder frequency division pulse signal EB _P , that is, for each encoder. This is for counting the number of clock pulse signals C _P in the cycle of the circular pulse signal EB _P (see (e) of FIG. 2). The count value of the clock pulse counter 15 is
The data is latched in the first register 16 in synchronization with the rising edge of the SETEP signal (see (f) in FIG. 2).

On the other hand, a sampling pulse signal S _P is generated from a sampling pulse generator (not shown) (see (g) of FIG. 2), and the sampling pulse signal S _P and the clock pulse signal C _P are It is configured to be input to the second flip-flop 17. Second
The flip-flop 17 synchronizes with the rising edge of the clock pulse signal C _P when the sampling pulse signal S _{P is} input, and a set sampling signal (hereinafter, SETSP signal) and a reset sampling signal (hereinafter, RS).
It is called a TSP signal. ) And (see (h) and (i) of FIG. 2).

The output pulse counter 13 to which the output pulse signal E _P from the pulse encoder PG is input is reset in synchronization with the rising edge of the RSTSP signal from the second flip-flop 17, and the sampling cycle In order to count the number of encoder output pulse signals E _P. The count value of the output pulse counter 13 is latched in the second register 18 in synchronization with the rising edge of the SETSP signal from the second flip-flop 17.

Reference numeral 19 is a preset register. The preset register 19 reads the count data of bit 1 or more of the encoder output pulse count value in the previous sampling cycle, which is counted by the output pulse counter 13 and latched in the second register 18, and reads the pulse encoder in the previous sampling cycle. The frequency division ratio information, which is determined in advance according to the number of output pulses of the PG, is set in the frequency divider 12 at the start of the current sampling cycle. In addition, the frequency division ratio by the frequency divider 12 is 1 /
If it is represented by m, the frequency division ratio information is represented by the frequency division value m in this embodiment.

Reference numeral 20 is a comparator, and the comparator 20 is the second
Compare the contents of register 18 with a predetermined constant K,
When the number of output pulses of the pulse encoder PG in the previous sampling cycle is smaller than the constant K, the ON signal LT is set to AN.
It is given to the D gate (and gate) 21. A
The ND gate 21 receives the ON signals LT and SE from the comparator 20.
Preset clear signal when TSP signal and is input
CL is given to the preset register 19.

The output pulse counter 13, the second register 18,
Preset register 19, comparator 20 and AND gate 21
Constitutes a frequency division ratio information setting means for setting and supplying to the frequency divider 12 a frequency division value that determines the frequency division ratio in each sampling cycle at the start of each sampling cycle. twenty two
Is a third register, and this third register 22 is
It is configured to be reset by the SP signal, and the frequency division ratio information (frequency division value) in the current (current) sampling cycle necessary for calculating the rotation speed of the servo motor described later.
Is read from the preset register 19.

A central processing unit (hereinafter referred to as CPU) 23 as an arithmetic processing means executes arithmetic processing necessary for calculating the rotation speed of the servo motor according to a predetermined control program, and shows a rotation speed signal of the servo motor. Not output to the servo motor speed control unit. CPU23
Reads the clock pulse count value for the latest cycle of the encoder divided pulse EB _{P in} the current sampling cycle, which is latched in the first register 16 at that time by inputting the SETSP signal as the interrupt signal. At the same time, the frequency division ratio information (frequency division value) in the current sampling period, which is latched in the third register 22, is read.

Next, the operation of the speed detecting device having the above structure will be described below with reference to FIGS. 1 and 2. Here, in order to facilitate understanding, the operation of setting the frequency division value in the frequency divider 12 performed at the start of each sampling period will be described first. The preset register 19 reads the count data of bit 1 or more of the encoder output pulse count value N _{EP in} the previous sampling cycle, which is counted by the output pulse counter 13 and latched in the second register 18. In this case, when the output pulse number N _EP of the pulse encoder PG in the previous sampling cycle is an odd number, it is read as an even value obtained by adding 1 to the value.

Therefore, when the encoder output pulse count value N _EP is 2m-1, 2m, the count data of bit 1 or more is read, that is, the value of 1/2 of the encoder output pulse count value N _EP is read. In the preset register 19, m is set as the frequency division value. For example, when the number of output pulses of the encoder PG in the previous sampling cycle is 4, the frequency division value m = 2, and the frequency divider 12 performs the frequency division operation with the frequency division ratio of 1/2.

Here, the comparator 20 compares the constant K with the contents of the second register 18 indicating the number N _EP of output pulses of the pulse encoder PG in the previous sampling cycle.
If the constant K is set to K = 3, the number of output pulses N _EP
Is smaller than 3, the ON signal LT from the comparator 20 is A
It is supplied to the ND gate 21. When the ON signal LT is input, the preset clear signal CL is output from the AND gate 21 in synchronization with the input of the SETSP signal.
Given to 19. As a result, when the number of output pulses N _EP of the pulse encoder PG in the previous sampling cycle is smaller than 3, the frequency dividing operation by the frequency divider 12 is not performed.

As the constant K, two or more encoder frequency division pulse signals EB _{P in the} sampling cycle are used.
The optimum value obtained empirically may be set so that is output. In addition, the maximum acceleration / deceleration of the servo motor is set to α (re
v / min ² ), the sampling period is TS (seconds), and the number of pulses per rotation of the pulse encoder PG is P, K =
[(1/2) x α x P x TS ² ] / 3 of the value calculated by 3600
You may make it employ | adopt the above odd value.

Now, the output pulse signal E _P from the pulse encoder PG is divided by the frequency divider 12 in which the frequency division value m in the sampling cycle is set at the start of each sampling cycle as described above. It will be divided by m. And the clock pulse counter 15
Thus, the number of clock pulse signals C _P in the cycle of each encoder divided pulse signal EB _P is counted, and the counted value is synchronized with the rising edge of the SETEP signal and the first register
Latched to 16.

When the CPU 23 receives an interrupt request by the SETSP signal in the current sampling cycle, it is latched in the first register 16 at that time.
Encoder divided pulse in this sampling period
Clock pulse count value N _CP for the latest period of EB _P
And the frequency division value m in the current sampling period, which is latched in the third register 22, is read.

The clock pulse count value N _CP and the frequency division value m
Based on and, V = [m / (N _CP × TC)] × (60 / P)
Calculate the rotation speed V (rpm) of the servo motor by
A signal indicating the rotation speed V is output to a servo motor speed control unit (not shown). Where TC is the clock pulse C _P
, P is the number of pulses per rotation of the pulse encoder PG.

The above-described operation is repeated every sampling period. In this way, the frequency division ratio information set in advance according to the number of output pulses from the pulse encoder in the previous sampling cycle is set in the frequency divider. The output pulse from the pulse encoder is divided by this divider, and the rotation speed of the servo motor is calculated based on the dividing ratio information of the divider and the number of clock pulses for the latest encoder dividing pulse period in the sampling period. Since the calculation is performed, the rotation speed of the servo motor can be accurately detected from the low speed region to the high speed region.

FIG. 3 is a block diagram showing the structure of a speed detecting device for a servo motor according to an embodiment of the invention. This embodiment is substantially the same as the configuration shown in FIG. 1 except that the configuration of the dividing ratio information setting means is different from the configuration shown in FIG. Are denoted by the same reference numerals and description thereof will be omitted, and only different points will be described.

[0027] In FIG 3, 31 denotes a frequency dividing pulse counter, the divider pulse counter 31 Encoder division pulse signal EB _P from the frequency divider 12 is input, RSTSP signal from the second flip-flop 17 is reset in synchronization with the rising, it is for counting the number of encoder division pulse signal EB _P in the sampling period.
The count value of the divided pulse counter 31 is latched in the second register 32 in synchronization with the rising edge of the SETSP signal from the second flip-flop 17.

Reference numeral 33 is a first comparator, 34 is a second comparator, and 35 is a third comparator. When the SETSP signal is given, the first comparator 33 counts by the frequency division pulse counter 31 and is latched in the second register 32, the encoder frequency division pulse count value in the previous sampling cycle (previous encoder frequency division pulse). (Count value) is compared with a preset constant zero, and a reset command signal RST for resetting the count value is output to the adder / subtractor 36 or the second comparator 34 via the AND gate 37 according to the comparison result. It outputs a signal for operating this.

When the operation signal from the first comparator 33 is given, the second comparator 34 compares the previous encoder divided pulse count value with a preset constant K _1, and based on the comparison result, The addition command signal ADD is output to the adder / subtractor 36, or a signal for operating this is output to the third comparator 35 via the AND gate 38. Third comparator
When the actuating signal from the second comparator 34 is given, 35 is
The previous encoder divided pulse count value is compared with a preset constant K ₂ (K ₂ <K ₁ ) and the subtraction command signal SUB is output to the adder / subtractor 36 according to the comparison result.
The comparators 33, 34, 35 form a comparison means.

Reference numeral 39 is a memory as a storage means for storing a frequency division value as a plurality of frequency division ratio information. As will be described later, the adder / subtractor 36 as the frequency division ratio information selecting means performs addition and subtraction using the constant 1 in accordance with the command signals ADD and SUB, so that the adder / subtractor 36 responds to the previous encoder frequency division pulse count value from the memory 39. This is for designating a memory reference address in order to select an optimum frequency division value. The preset register 40 reads the frequency division value selected by the adder / subtractor 36 from the memory 39 at the start of the sampling period and sets it in the frequency divider 12. Divided pulse counter 31, second register 32, comparator
33, 34, 35, adder / subtractor 36, AND gates 37, 38 and memory
The 39 and the preset register 40 constitute frequency division ratio information setting means for setting and supplying to the frequency divider 12 a frequency division value that determines the frequency division ratio in each sampling cycle at the start of each sampling cycle.

Next, the operation of the speed detecting device having the above structure will be described below with reference to FIG. Here, in order to facilitate understanding, the operation of setting the frequency division value in the frequency divider 12 will be described first. The memory 39, in this embodiment, the dividing value in the address zero 1, thereafter as address 1 frequency division value m _1, address 2 frequency division value m ₁ ^2, the frequency division value in the address n m Remember ₁ ⁿ . Note that when the servo motor is stopped rotating, since the encoder division pulse signal EB _P to divide the pulse counter 31 is not input, the first comparator 33, the previous encoder division pulse count becomes zero constant A reset command signal RST indicating that it coincides with zero is given to the adder / subtractor 36. As a result, the memory reference address becomes zero, and the frequency division value 1 (frequency division ratio 1/1) is set in the frequency divider 12 by the preset register 40. Therefore, in the first sampling period when the servo motor is started, the frequency divider 12 divides the frequency by 1 /
The frequency division operation is performed by 1.

First, the first comparator 33 causes the SETSP signal to be transmitted.
When the number is given, the divided pulse counter 31 counts
And the previous sampler that is latched in the second register 32
Encoder divided pulse count value N in the cycle_EB(Previous time
Encoder divided pulse count value) and constant zero are compared.
It As a result of comparison, the previous encoder divided pulse count value N _EB
Is naturally larger than the constant zero, the first comparator 33
Activates the second comparator 34 via the AND gate 37
To output the signal.

When the operation signal from the first comparator 33 is given, the second comparator 34 compares the previous encoder divided pulse count value N _EB with the constant K ₁ . This constant K ₁ corresponds to a “threshold value” that determines whether or not frequency division is possible in each sampling cycle, and is set as a value of 3 or more. As a result of the comparison, when the encoder frequency division pulse number N _EB in the previous sampling cycle is larger than the constant K ₁ , the second comparator 34 outputs the addition instruction signal ADD to the adder / subtractor 36.

As a result, the memory reference address is incremented by 1, and the preset register 40 has a value m ₁ times larger than the frequency division value in the previous sampling cycle from the memory 39 at the start of the current sampling cycle. The frequency division value is read and set in the frequency divider 12. Therefore, if the encoder frequency division pulse number N _EB in the previous sampling cycle is larger than the constant K ₁ , the frequency divider 12
In the current sampling cycle, the frequency division operation is performed with a frequency division ratio smaller than the frequency division ratio of the previous sampling cycle. In this embodiment, the frequency division operation is performed with a frequency division ratio that is 1 / m ₁ times the frequency division ratio of the previous sampling period.

On the other hand, the second comparator 34 outputs a signal for operating the third comparator 35 via the AND gate 38 when the previous encoder divided pulse count value N _EB is smaller than the constant K _1. Output. Receiving this signal, the third comparator 35
Is the previous encoder divided pulse count value N _EB and constant K ₂
When the encoder frequency division pulse number N _EB in the previous sampling cycle is smaller than the constant K ₂ , the subtraction command signal SUB is output to the adder / subtractor 36.

As a result, the memory reference address is decremented by 1, and the preset register 40 sets a value 1 / m ₁ times the frequency division value in the previous sampling cycle from the memory 39 at the start of the current sampling cycle. The frequency division value which it has is read and this is set to the frequency divider 12. Therefore, if the encoder frequency division pulse number N _EB in the previous sampling cycle is smaller than the constant K ₂ , the frequency divider 12
In this sampling period, the frequency division operation is performed with a frequency division ratio larger than the frequency division ratio of the previous sampling period. In this embodiment, the frequency dividing operation is performed with a frequency dividing ratio obtained by multiplying the frequency dividing ratio of the previous sampling period by m ₁ . If the previous encoder divided pulse count value N _EB is not smaller than the constant K ₂ , the memory reference address is not operated and the frequency divider 12 divides the frequency of the previous sampling period in the current sampling period. The frequency division operation is performed with the same frequency division ratio as the ratio.

The output pulse signal E _P from the pulse encoder PG is frequency-divided by the frequency divider 12 in which the frequency division value in the sampling cycle is set at the start of each sampling cycle as described above. Become. Then, by the clock pulse counter 15, a clock pulse signal C in the period of each encoder division pulse signal EB _P
The number of _Ps is counted, and the counted value is latched in the first register 16 in synchronization with the rising edge of the SETEP signal.

When the CPU 23 receives an interrupt request by the SETSP signal in the current sampling cycle, it is latched in the first register 16 at that time.
Encoder divided pulse in this sampling period
Clock pulse count value N _CP for the latest period of EB _P
And the frequency division value in the current sampling cycle, which is latched in the preset register 40, is read. The frequency division value in this sampling cycle is represented by m.

This frequency division value m and clock pulse count value N _CP
Based on and, V = [m / (N _CP × TC)] × (60 / P)
Calculate the rotation speed V (rpm) of the servo motor by
A signal indicating the rotation speed V is output to a servo motor speed control unit (not shown). Where TC is the clock pulse C _P
, P is the number of pulses per rotation of the pulse encoder PG.

The above operation is repeated every sampling period. As a result of the above, claim 1 described above
Similarly to the speed detecting device according to the invention, the rotation speed of the servo motor can be accurately detected from the low speed region to the high speed region. Further, since the frequency divider is provided with a feedback means for setting the frequency division ratio information (frequency division value) based on the number of encoder frequency division pulses in the previous sampling cycle at the start of each sampling cycle, the frequency division is performed. Since the frequency dividing operation is performed by the device with an optimum frequency division ratio according to the rotation speed of the servo motor, the rotation speed of the servo motor can be detected accurately over a wider speed range.

[0041]

According to the speed detecting device for a servomotor of the first aspect of the present invention, the frequency divider is preset in accordance with the number of output pulses from the pulse encoder in the previous sampling period at the start of each sampling period. Set the division ratio information, divide the output pulse from the pulse encoder by this divider, and measure the division ratio information of the divider and the latest encoder division pulse period in the sampling period. Since the rotation speed of the servo motor is calculated based on the clock pulse count value for this, the rotation speed of the servo motor can be accurately detected from the low speed region to the high speed region. According to the speed detecting device of the servo motor of the invention of claim 2, in addition to the above-mentioned effect, the frequency divider has a frequency division ratio based on the number of encoder frequency division pulses in the previous sampling period at the start of each sampling period. Since the information is set, the frequency divider performs the frequency division operation with the optimum frequency division ratio according to the rotation speed of the servo motor, so the rotation speed of the servo motor can be set in a wider speed range. It is possible to detect with high accuracy.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a speed detection device for a servo motor according to an embodiment of the invention of claim 1.

FIG. 2 is a diagram for explaining the operation of the speed detection device shown in FIG.

FIG. 3 is a block diagram showing a configuration of a speed detection device for a servo motor according to an embodiment of the invention of claim 2;

[Explanation of symbols]

11 ... Waveform shaping circuit 12 ... Divider 13 ... Output pulse counter 14 ... First flip-flop 15 ... Clock pulse counter 16 ... First register 17 ... Second flip-flop
18 ... Second register 19 ... Preset register 20 ... Comparator 21 ... AND gate 22 ... Third register 23 ... CP
U 31 ... Divided pulse counter 32 ... Second register 33 ...
First comparator 34 ... Second comparator 35 ... Third comparator 36 ... Adder / subtractor 37, 38 ... AND gate 39 ... Memory 40 ... Preset register PG ... Pulse encoder

Claims (2)

[Claims] 1. A speed detection device for detecting a rotation speed of a servo motor based on an output pulse of a pulse encoder attached to a servo motor, wherein a frequency division ratio that determines a frequency division ratio in the sampling cycle at the start of each sampling cycle. Information is given by the division ratio information setting means, a frequency divider for dividing the output pulse from the pulse encoder, and a clock pulse counter for counting the number of clock pulses in the cycle of the encoder divided pulse from the frequency divider, Arithmetic processing means for calculating the rotation speed of the servomotor based on the frequency division ratio information of the frequency divider and the clock pulse count value of the clock pulse counter for the latest encoder frequency division pulse cycle in the sampling cycle. , The frequency division ratio information setting means is An output pulse counter that counts the number of output pulses from the encoder and frequency division ratio information preset according to the encoder output pulse count value in the previous sampling cycle counted by the output pulse counter is set in the frequency divider. And a speed detecting device for a servo motor. 2. A speed detection device for detecting a rotation speed of a servo motor based on an output pulse of a pulse encoder attached to a servo motor, wherein a frequency division ratio that determines a frequency division ratio in the sampling cycle at the start of each sampling cycle. Information is given by the division ratio information setting means, a frequency divider for dividing the output pulse from the pulse encoder, and a clock pulse counter for counting the number of clock pulses in the cycle of the encoder divided pulse from the frequency divider, Arithmetic processing means for calculating the rotation speed of the servo motor based on the frequency division ratio information of the frequency divider and the clock pulse count value of the clock pulse counter for the latest encoder frequency division pulse cycle in the sampling cycle. The frequency division ratio information setting means stores a plurality of frequency division ratio information. Storage means, a frequency division pulse counter for counting the number of encoder frequency division pulses from the frequency divider in the sampling cycle, a preset value and an encoder for the previous sampling cycle counted by the frequency division pulse counter A comparing means for comparing the divided pulse count value with the dividing means, and if the comparing means determines that the previous encoder divided pulse count value is larger than a set value, the dividing means stores the divided frequency smaller than the previous division ratio from the storage means. If the frequency division ratio information that is a ratio is selected and it is determined that the previous encoder frequency division pulse count value is smaller than the set value, the frequency division ratio that is a frequency division ratio larger than the previous frequency division ratio from the storage means. It has a frequency division ratio information selection means for selecting information and means for setting the frequency division ratio information selected by the frequency division ratio information selection means in the frequency divider. Servo motor speed detector.