JPS58120167A - Detection of speed - Google Patents

Abstract

PURPOSE:To improve the detection of speed in a wide range by processing outputs of a pulse generator for generating pulses each time a moving object moves by a specific distance with first and second counters, an oscillator and a register. CONSTITUTION:Output pulses PLG from a pulse generator for generating pulses each time a moving object moves by a specific distance are counted with a first counter 17. The output value of a second counter 18 is memorized into a register 23 by counting a clock pulse of a generator 19 with a second counter 18. The number of output pulses PLG is obtained with the first counter 17 to a fixed time after it synchronizes the pulse and the discrete value of the second counter 18 and the value of a register 23 are done at the time after a fixed time passes. The speed of the moving object is detected by dividing the discrete value of the second counter 18 by the value of the register 23 and adding the result to the first counter 17.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for detecting the speed of a moving body or a rotating body, and particularly to a speed detecting method suitable for use in detecting the speed of a digital speed control device.

A pulse generator (usually called an incremental encoder) that generates pulses at the same rotational position that divides one revolution into two is often used in digital speed control devices for electric motors. This pulse generator generates a pulse every time the position changes by l/P rotation, and requires some kind of signal processing circuit to obtain the detected speed value Nt as a digital quantity. The following two methods are used for signal processing.

The first method is to count the output pulses of the pulse generator generated during the elapse of one foot and obtain the speed detection value Nt from the count 11NM1 using the following equation (pulse number counting method).

K, is a constant In the second method, the output pulse interval Tp (1/
This is a method (2) of the pulse interval counting method 1 in which the detected speed value N- is obtained by the following equation using the counted value M2 by counting the time of P rotational movement) using a clock pulse of -Ube wave number.

K2: Constant However, both methods have the following drawbacks.

In the former pulse counting method, when the speed becomes low, the count value M1 becomes small and the resolution deteriorates. To increase the count value M1 at low speeds, either lengthen the fixed time Td or increase the number of pulses P generated per revolution of the pulse generator.However, if the time Td is lengthened, the detected speed value N+ It takes time to obtain P, making it impossible to improve the response.Furthermore, it is difficult to increase the number of pulses P due to the structure of the pulse detector.

On the other hand, in the latter pulse interval counting method, as is clear from equation (2), the resolution deteriorates significantly when the count value M2 becomes small, that is, at high speeds when the pulse interval Tp becomes narrow. In order to solve these disadvantages of both methods, it is known to use both methods together to reduce detection delay and improve resolution.

This method uses the pulse count value M of the pulse generator generated during a constant time Td and the count value M2, which is the output pulse interval of the pulse generator multiplied by 1 with a clock pulse of a constant frequency, using the following formula. The speed detection value N is obtained by

M.

According to this method, two quantities, the count values M+ and M2, are counted, so there are many combinations, and the resolution of the speed detection value Nt is improved, and the detection time Td is constant.
Detection delay can be reduced.

However, this method also has the following drawbacks.

That is, the count value M is the number of pulses within a certain time Td, and is proportional to the rotation angle, but is essentially 1.
Contains pulse error. Specifically, it is not known whether the count value M is close to (M, +1) or (M, +O). In particular, at low speeds, the count value M also becomes small, so the error reaches several tens of lights. For this reason, it is not possible to perform speed detection with an n degree of accuracy when the speed is extremely low.

Further, the count value M means a pulse interval, but it is a pulse interval at one point in the detection time T4, and does not indicate an accurate value when the speed is changing such as acceleration or deceleration.

As described above, there is no conventional speed detection method that can reduce detection delay over a wide speed range from low to high speeds and improve both resolution and accuracy, which is hindering the practical application of digital speed control devices. That is the reality.

An object of the present invention is to provide a speed detection method that has less delay in speed detection over a wide speed range and has improved resolution and accuracy.

The present invention skillfully combines the pulse counting method and the pulse interval counting method to detect speed with high precision without detection delay.
I will explain its basic philosophy.

The present invention includes a first counter that starts counting the output pulses of a pulse generator in synchronization with the pulses and continues counting until after a certain time Td, and a first counter that counts output pulse intervals during the counting time of the first counter and counts the output pulses for a certain period of time. a second counter that stops after Td;
A register is provided to store the counted value of the pulse interval, and the detected speed value Ng is determined by the following equation.

However, K is a constant, M3 is the count value of the first counter,
M4 is the register value 2M, and is the count value of the second counter.

In this way, Me/M4 will be corrected for the number of M1 pulses that arrive within the time Td,
Accuracy has improved.

The speed detection time is Td, and even at the lowest rotation speed that guarantees control performance, there is no particular detection delay because there is a correction of Ms/M4.

FIG. 1 shows an embodiment of an electric motor digital speed control device employing the speed detection method according to the present invention. 1 is a speed command circuit, 2 is a microcomputer, 3 is a drive circuit, 4
5 is an electric motor, 5 is a pulse generator, and 6 is a speed detection circuit.

The microcomputer 2 takes in the speed command value N from the speed command circuit 1, and also uses the speed detection value N1 calculated by the process described later based on the information obtained from the speed detection circuit 6 to read the speed command value N1 from the drive circuit 3. The converter is composed of a power converter made of power semiconductors such as thyristors and transistors, and its control circuit, and the motor 4 is rotated by its operation. As a result, the pulse generator 5 generates a pulse train with a frequency proportional to the motor rotation speed. This pulse train becomes an input to the speed detection circuit 6, and the detected speed value N is converted into information calculated by the microcomputer 2.

A detailed circuit diagram of the speed detection circuit 6 for performing such speed control operation is shown in FIG. Further, the operation waveforms are shown in FIG. 3, and the processing performed by the microcomputer 2 for speed detection is shown in the flowchart of FIG.

The speed detection circuit 6 is a flip-flop circuit 9°10, OR
Circuit 12. AND circuit 13, 14° 15, counter 16
, 17.18, a pulse oscillator 19. which generates clock pulses with a frequency of -. Monostable circuits 20, 21, delay circuit 2
2. Consists of register 23.

RES is a pulse generated by the microcomputer 2 before starting the speed detection circuit operation, and is used as a reset signal (connected to the clear terminal CR) for the flip-flop circuits 9 and 1° via the OR circuit 12. As a result,
In the initial state, the outputs F1 and F2 of the output terminals Q of the flip-flop circuits 9 and 10 are both at the "0" level. From this state, the microcomputer 2 sets the signal DBT for starting the operation of the speed detection circuit 6 to the "1" level. Then, when the pulse PT to start speed detection is generated, the output F1 of the flip-flop circuit 9 becomes the third pulse.
As shown in the figure, the level becomes "l".

On the other hand, assuming that the output pulse PLO of the pulse generator 5 changes as shown in FIG. As a result, a clock pulse from the pulse oscillator 19 is applied to the counter 16 via the AND circuit 13. By the way, since the clock pulse generated from the pulse oscillator 19 has a constant frequency, the overflow pulse Ol''P is generated after a constant time Td determined by the number of bits of the counter 16.
occurs. When this pulse is generated, the flip-flop circuits 9 and 1o are reset, and the respective outputs Fl,
F2 becomes the 10'' level.

On the other hand, the output signal F2 of the flip-flop circuit 1o is “1”.
'', that is, during the time Td, the counter 17 counts the number of pulses of the output pulse PLG, and the counter 18 counts the number of output pulses of the pulse generator 19.
O is input as a clear signal to the counter 18 via the monostable circuit 21 and the delay circuit 22. Therefore, the counter 18 repeats counting every PLG period. The counted value is then transferred to the register 23 before being cleared. That is, while the signal F2 is at the "1" level, the outputs (9) Ma, M5 . M4 changes as shown in Figure 3.

On the other hand, the OF P (g) of the counter 16 is output to the microcomputer 2 as an interrupt pulse signal INT.

When the microcomputer 2 receives the interrupt pulse INT, it executes the process shown in FIG. First, in step 30, the outputs MA, MB and MC of the counters 17 and 18 are input.

Each count value is Ma.

Let them be M5 and M4. Next, in step 31, the count value M
The calculation of equation (4) is performed using s and Ma 1M4. Since the microcomputer 2 performs integer arithmetic in order to shorten processing time, processing is actually performed in the order of one song shown in FIG. As a result, the obtained speed detection value Nt is stored in a predetermined storage device. This stored value is used when the microcomputer 2 performs speed control. Finally, a pulse PT is generated to start the next speed detection.

As a result, the counter 17 is reset, and the output F1 of the flip-flop circuit 9 is brought to the .degree.1" level and the above-described operations are repeated.

(10) According to the embodiment described above, since the number of output pulses of the pulse generator 5 within one hour T is accurately measured by the counters 17 and 18 and the register 23, the speed detection is calculated using these values. Value resolution can be improved. Furthermore, the speed detection processing of the microcomputer is as shown in FIG. 4, and is sufficient to be performed every time Td, so that the burden on the microcomputer 2 is small. Further, since the microcomputer 2 is interrupted when the data of the counters 17 and 18 are established, the detected speed value can be calculated immediately.

According to the present invention, it is possible to perform digital speed detection with no detection delay, high resolution, and high precision.

Therefore, it has an effect that can be applied to high-speed, high-response speed control.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a digital speed control device for an electric motor employing the present invention, Fig. 2 is a circuit diagram showing an embodiment of the present invention, and Figs. 3 and 4 are the same as those shown in Fig. 2. The time chart and flowchart for explaining the operation. Figure 5 is the actual processing flowchart of Figure 4 (11) (12) Figure 2

Claims (1)

[Claims] 1. A pulse generator that generates a pulse every time a moving object moves a predetermined distance, and an oscillator that generates a clock pulse at a frequency that is one foot higher than the output pulse of the pulse generator;
a first counter means for counting the output pulses of the pulse generator; and a second counter means for counting the clock pulses of the oscillator.
and a register for storing one output pulse of the second counter, the number of pulses and the one-leg time from the time when the first counter means is synchronized with the output pulse of the pulse generator to the one-leg time. A second counter count value and a register value are obtained at the time when the second counter count value and a register value are obtained, and the speed of the moving object is detected by the value obtained by adding the value obtained by dividing the second counter count value by the register value to the first counter count value. The speed detection method that takes the value.