JP3589527B2 - Displacement measuring device - Google Patents

Description

【００１４】
表１において、×は“０”，“１”を問わないことを意味する。表１の論理による動作を説明すれば、源計数パルスＰＵＥＮ＝０でかつ、出力イネーブル信号ＯＵＴＥＮ＝０の場合、バッファカウンタ３を動かす必要がないから、ＳＴＯＰとする。源計数パルスＰＵＥＮのダウンカウント指示（ＰＵＥＮ＝１，Ｕ／Ｄ＝０）と、計数値が負の状態での計数パルス出力によるアップカウント指示（ＯＵＴＥＮ＝１，ＭＩＮＵＳ＝０）とが重なった場合、バッファカウンタに入力されるパルスと出力するパルスが同数であることを意味するから、バッファカウンタ３はＳＴＯＰとする。同様に、源計数パルスＰＵＥＮのアップカウント指示（ＰＵＥＮ＝１，Ｕ／Ｄ＝１）と、計数値が正の状態での計数パルス出力によるダウンカウントの指示（ＯＵＴＥＮ＝１，ＭＩＮＵＳ＝１）が重なった場合も、ＳＴＯＰとする。
【００１５】
また、源計数パルスの入力がなく（ＰＵＥＮ＝０）、計数パルス出力がある場合（ＯＵＴＥＮ＝１）には、計数パルス出力によりバッファしておく値が増減することを意味するため、計数値の正，負に応じて、−１，＋１カウントする。逆に、ＰＵＥＮ＝１，ＯＵＴＥＮ＝０の場合は、アップ／ダウンの指示に応じて、＋１，−１カウントする。更に、源計数パルスによるアップカウント指示（ＰＵＥＮ＝１，Ｕ／Ｄ＝１）と、計数値が負の状態での計数パルス出力によるアップカウント指示（ＯＵＴＥＮ＝１，ＭＩＮＵＳ＝０）が重なった場合には、計数パルス出力と源計数パルスの方向が逆であり、バッファカウンタ増減値を倍にする必要があるため、＋２カウントする。逆に、源計数パルスによるダウンカウント指示（ＰＵＥＮ＝１，Ｕ／Ｄ＝０）と、計数値が正の状態での計数パルス出力によるダウンカウントの指示（ＯＵＴＥＮ＝１，ＭＩＮＵＳ＝１）が重なった場合は、−２カウントする。
【００１６】
以上のようなバッファカウンタ３でのカウント制御により、第１のクロックＣＫ０で動作するバッファカウンタ３の計数値をリアルタイムで増減しながら、第２のクロックＣＫ１で動作するパルス出力回路８から計数パルス出力を出力することができる。なおパルス出力回路８では、通常行われているフォーマット加工が行われて、例えば計数パルス信号とＵ／Ｄ信号、または２相方形波信号である出力パルスφＡ，φＢが得られることになる。
【００１７】
バッファカウンタ３およびその周囲の具体的な回路構成を図２に示す。図２においては、バッファカウンタ３を３個の１６ビット（符号ビットとしての１ビットを含む）のアップダウンカウンタ３１ａ〜３１ｂの縦続接続により構成した例を示している。２段目および３段目はそれぞれ前段のオーバーフロー出力である出力イネーブルＥＮＯＵＴが入力イネーブルＥＮＩＮとして入って、全体として、±２０４７カウント可能なアップダウンカウンタとなっている。カウンタ３１ａ，３１ｂ，３１ｃ間の桁上げを確実にするため、第１のクロックＣＫ０は、バッファ遅延回路３２，３３を介して少しずつ遅延させて各段クロック端子ＣＫＢに入力している。
【００１８】
３段目のカウンタ３１ｃの最上位桁Ｑ３が符号ビットＭＩＮＵＳとして用いられている。
オールゼロ検出回路４は、各段カウンタ３１ａ〜３１ｃの各桁出力がオールゼロであることを検出するＮＯＲゲートＧ４１，Ｇ４２，Ｇ４３と、これらの出力の一致を検出するＮＡＮＤゲートＧ４４とから構成されている。これにより、オールゼロ検出回路４は、バッファカウンタ３での計数値がゼロの場合に、ＡＺ＝０を出力し、それ以外はＡＺ＝１を出力する。
【００１９】
クロックゲート６は、第２のクロックＣＫ１とオールゼロ検出回路４の出力ＡＺの一致を検出するＮＡＮＤゲートＧ６１とインバータゲートＧ６２とからなる。これにより、ＡＺ＝０の場合に、クロックゲート６はオフになり、バッファカウンタ３に計数値がある間（ＡＺ＝１）、第２のクロックＣＫ１がクロックゲート６を通って、出力イネーブル信号ＯＵＴＥＮとして取り出される。
【００２０】
初段カウンタ３１ａには、３つのモード制御端子、即ち、１カウントするか、２カウントするかを選択する選択信号ＳＥＬ１，ＳＥＬ２の端子と、アップ／ダウン選択信号ＵＰの端子が設けられている。これらの３つの制御端子の入力の組み合わせと、カウントモードをまとめると、下表２のようになる。
【００２１】
【表２】

【００２２】
カウンタ制御ゲート７は、源計数パルスＰＵＥＮ，アップ／ダウンパルスＵ／Ｄ，出力イネーブル信号ＯＵＴＥＮおよび符号ビットＭＩＮＵＳの組み合わせにより、表２の制御信号を発生するように、図２のように構成される。ＥＸ・ＮＯＲゲートＧ７１は、ＰＵＥＮとＵ／Ｄの一致を検出して選択信号ＳＥＬ１を発生する。ＥＸ・ＮＯＲゲートＧ７１２とＮＡＮＤゲートＧ７３は、ＭＩＮＵＳとＵ／Ｄの一致検出を行い、その検出結果とＰＵＥＮ，ＯＵＴＥＮとの一致検出を行って、選択信号ＳＥＬ２を発生する。また、ＡＮＤゲートＧ７４，Ｇ７５，ＮＯＲゲートＧ７６，インバータＧ７７，Ｇ７８の部分は、ＭＩＮＵＳ，ＰＵＥＮ，Ｕ／Ｄの組み合わせにより、アップ／ダウン信号ＵＰを発生させる。
【００２３】
以上のようにこの実施例によると、高速の第１のクロックＣＫ０により動作するバッファカウンタ３により源計数パルスをカウントしながら、同時に、低速の第２のクロックＣＫ１で計数パルスが出力され、計数パルス出力によりリアルタイムでバッファカウンタ３の計数値が増減制御され、変位量に相当するバッファカウンタ３での計数値分の計数パルスが得られることになる。従って、外部カウンタが低周波であっても、これに制限されることなく変位検出器の高速の移動速度を確保することができる。また、出力計数パルスの周波数を決定する第２のクロックＣＫ１を生成する出力周期カウンタ５を外部から分周比可変とすることにより、例えば外部カウンタが高速計数できる場合には第２のクロックＣＫ１の周波数を第１のクロックＣＫ０と同じとして、外部カウンタに接続することができる。
【００２４】
この実施例において、バッファカウンタ３の桁数は、変位検出器１の移動範囲と出力計数パルスの周波数との兼ね合いで決定される。例えば、桁数を移動範囲より多くすれば、出力周波数を如何に低くしても差し支えなく、しかも内部的な計数は高速クロックで動作するバッファカウンタ３で行われるから、出力周波数を低くしたことにより検出器移動速度が低い範囲に制限されることはない。また、桁数を変位検出器移動範囲より少なくしても、バッファカウンタ３の計数値はリアルタイムで計数パルス出力毎に加減算されるから、外部カウンタの計数可能な周波数の範囲で出力周波数を高く設定すれば、問題はない。これにより、回路規模を小さくすることができる。
【００２５】
計数パルス出力回路８の構成例を図４に示し、その動作タイミング図を図５に示す。詳細な説明は省くが、二つのＤタイプフリップフロップＦＦ１，ＦＦ２と、これらの出力とＯＵＴＥＮ信号及びＭＩＮＵＳ信号によりフリップフロップＦＦ１，ＦＦ２への入力を決定するためのゲートＧ８１，Ｇ８２を用いて、２相方形波出力φＡ，φＢを出力するようになっている。
【００２６】
【発明の効果】
以上述べたようにこの発明によれば、第１のクロックで動作するバッファカウンタを用いて、源計数パルスをカウントしながら同時に、その計数値相当分の計数パルスを第２のクロックで出力するようにして、低周波の外部カウンタによる計数を可能とした変位測定装置を提供することができる。
【図面の簡単な説明】
【図１】この発明の一実施例による変位測定装置のブロック構成を示す。
【図２】同実施例の主要部の具体構成例を示す。
【図３】同実施例の第１，第２クロックの関係を示す。
【図４】同実施例のパルス出力回路の具体構成例を示す。
【図５】同パルス出力回路の動作タイミングを示す。
【符号の説明】
１…変位検出器、２…源計数パルス発生回路、３…バッファカウンタ、４…オールゼロ検出回路、５…出力周期カウンタ、６…クロックゲート、７…カウンタ制御ゲート、８…計数パルス出力回路。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a displacement measuring device of a type in which a counting pulse corresponding to a displacement amount is counted by an external counter.
[0002]
[Prior art]
In displacement measuring devices such as a linear gauge and a linear scale, the movement amount of a head or a spindle is output as a count pulse, and this is often counted and displayed by an external counter. In this method, normal operation cannot be guaranteed unless the relationship of fOUT ≦ fCNT is established between the output frequency fOUT of the count pulse and the count frequency fCNT of the external counter. Therefore, when the speed of the displacement measuring device is increased and the counting pulse is increased, there is a problem that an external counter having a low fCNT of a conventional type cannot be used.
[0003]
When the output counting pulse frequency changes in accordance with the moving speed of the displacement detector, the moving speed of the displacement detector is limited by the external counter when a low-speed external counter is used, so that high-speed counting cannot be performed.
Furthermore, some servo circuits using a capacitance type displacement detector or the like output a burst-like high-speed counting pulse irrespective of the moving speed of the detector. If a low-speed external counter is connected to such a measuring device, errors such as erroneous counting and overspeed may occur even when the moving speed of the detector is low.
[0004]
[Problems to be solved by the invention]
The present invention has been made in consideration of the above circumstances, and provides a displacement measuring device that outputs a counting pulse that can internally perform high-speed counting and can also perform counting by a low-speed external counter. It is an object.
[0005]
[Means for Solving the Problems]
The present invention is a displacement measuring device which outputs a number of count pulses corresponding to a displacement amount to be counted by an external counter based on an output of a displacement detector, wherein the displacement measuring device operates in synchronization with a first clock, and A source count pulse generating circuit for outputting a source count pulse having a width corresponding to the amount of displacement detected by the detector and an up / down pulse for instructing up / down in accordance with the displacement direction; A buffer counter that counts up / down with one clock, and a pulse that operates with a second clock having a frequency equal to or lower than that of the first clock and generates the same number of count pulses as the count value of the buffer counter And an output circuit.
[0006]
According to the present invention, in addition to the above configuration, an output period counter for generating the second clock for dividing the first clock to determine a frequency of a count pulse to be output, and a count value of the buffer counter Is not zero, the clock gate which takes out the second clock as an output enable signal and supplies it to the pulse output circuit and the combination of the source count pulse, up / down pulse and output enable signal, A counter control gate for performing control to increase or decrease the count value of the buffer counter in real time according to the count pulse output.
Preferably, in the present invention, the output cycle counter is configured such that the frequency of the second clock can be set to be equal to or lower than the frequency of the first clock by switching a frequency division ratio under control from an external terminal. Is done.
More preferably, in the present invention, the overflow terminal of the buffer counter is led out as an overspeed terminal.
[0007]
According to the present invention, the buffer counter that operates with the high-speed clock counts the source count pulse and simultaneously outputs the count pulse corresponding to the count value with the low-speed clock. Therefore, counting by a low-speed external counter is possible. If the number of digits of the buffer counter can cover the moving range of the displacement detector, no matter how low the frequency of the output counting pulse, the moving speed of the displacement detector is not limited. Also, by controlling the count value of the buffer counter to increase or decrease in real time simultaneously with the output of the count pulse, the number of digits of the buffer counter can be made smaller than the moving range of the displacement detector, thereby reducing the circuit scale. In addition, the moving speed of the displacement detector can be secured without being limited by the counting frequency of the external counter.
Further, if the output cycle counter for generating the second clock for determining the frequency of the output count pulse is made externally variable in frequency division ratio, the count pulse frequency can be switched according to the external counter. For example, when the external counter can perform high-speed counting, the division ratio 1, that is, the second clock frequency can be made the same as the first clock frequency, and therefore, the system adaptability can be made high.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows the configuration of a displacement measuring device according to an embodiment of the present invention. The displacement detector 1 may be of any type, such as a capacitance type, a photoelectric type, and the like. The source count pulse generation circuit 2 operates in synchronization with the first clock CK0, and performs source count pulse PUEN having a width corresponding to the amount of displacement detected by the displacement detector 1 and up / down in accordance with the direction of displacement. The instructing up / down pulse U / D is output. The source count pulse PEUN differs depending on the method of the displacement detector 2, but may be a burst pulse including the clock CK0 inside, or a pulse obtained by envelope-detecting the burst pulse. The source count pulse PUEN is directly transferred together with the up / down pulse U / D to the count pulse output circuit which operates on the same clock, and has a predetermined format (for example, a count pulse and a U / D signal or a two-phase square wave signal). Etc.) was produced.
[0009]
In this embodiment, a source count pulse PUEN and an up / down pulse U / D obtained from a source count pulse generation circuit 2 are sent to a buffer counter 3, where the width of the source count pulse PEUN is set to a first clock. Counted by CK0. The count value of the buffer counter 3 corresponds to the displacement amount to be obtained. It is the count pulse output circuit 8 that outputs a count pulse output equal in number to the count value of the buffer counter 3. In this embodiment, as described later, the count value of the buffer counter 3 is increased or decreased in real time. The count pulse output circuit 8 outputs a count output pulse. An overflow terminal OF of the buffer counter 3 is led out as an overspeed terminal OS.
[0010]
An output cycle counter 5 is provided to determine the frequency of the count pulse output by the count pulse output circuit 8. The output cycle counter 5 outputs a second clock CK1 obtained by dividing the first clock CK0 by a predetermined division ratio. In this embodiment, an external terminal for switching the division ratio is provided. Thus, as exemplified in FIG. 3, the frequency of the second clock CK1 can be variably set in the same range as or lower than that of the first clock CK0. Then, the second clock CK1 obtained from the output cycle counter 5 is used as a synchronous clock of the count pulse output circuit 8.
[0011]
At the same time as counting the source count pulse PUEN, the buffer counter 3 detects an all-zero state of all digit outputs of the buffer counter 3 in order to perform real-time increase / decrease control of the count value according to the output from the count pulse output circuit 8. An all-zero detection circuit 4 and a clock gate 6 controlled by the output AZ of the detection circuit 4 to take out the second clock CK1 from the output cycle counter 5 as an output enable signal OUTEN are provided, and the counting operation of the buffer counter 3 is performed. A counter control gate 7 for controlling is provided. The counter control gate 7 sends a control signal to the buffer counter 3 by a combinational logic of the source count pulse PUEN, the up / down pulse U / D, the output enable signal OUTEN, and the sign bit output MINUS of the buffer counter 3, and In this case, control of ± 1 count, ± 2 count or count stop is performed.
[0012]
Before describing the detailed circuit of each part, the count operation of the buffer counter 3 is summarized in a truth table as shown in Table 1 below. The sign MINUS of the buffer counter 3 indicates which of the up / down directions the source count pulse has been output, and thereby determines the direction of the count pulse output.
[0013]
[Table 1]

[0014]
In Table 1, x means that "0" or "1" is not considered. The operation based on the logic of Table 1 will be described. If the source count pulse PUEN = 0 and the output enable signal OUTEN = 0, the buffer counter 3 does not need to be moved, so that the operation is STOP. When the down count instruction of the source count pulse PUEN (PUEN = 1, U / D = 0) and the up count instruction by the count pulse output when the count value is negative (OUTEN = 1, MINUS = 0) overlap Since the number of pulses input to the buffer counter and the number of output pulses are the same, the buffer counter 3 is set to STOP. Similarly, an up-count instruction of the source count pulse PUEN (PUEN = 1, U / D = 1) and a down-count instruction (OUTEN = 1, MINUS = 1) by a count pulse output when the count value is positive are given. If they overlap, it will be a STOP.
[0015]
If there is no input of the source count pulse (PUEN = 0) and there is a count pulse output (OUTEN = 1), it means that the value to be buffered by the count pulse output increases or decreases. −1 and +1 are counted according to positive and negative. Conversely, when PUEN = 1 and OUTEN = 0, the count is incremented by +1, -1 in accordance with the up / down instruction. Further, when the up-count instruction by the source count pulse (PUEN = 1, U / D = 1) and the up-count instruction by the count pulse output when the count value is negative (OUTEN = 1, MINUS = 0) overlap. In this case, the count pulse output and the source count pulse are in opposite directions, and it is necessary to double the increase / decrease value of the buffer counter. Conversely, the down-count instruction by the source count pulse (PUEN = 1, U / D = 0) and the down-count instruction by the count pulse output when the count value is positive (OUTEN = 1, MINUS = 1) overlap. If so, count -2.
[0016]
By the count control of the buffer counter 3 as described above, the count pulse output from the pulse output circuit 8 operated by the second clock CK1 while increasing or decreasing the count value of the buffer counter 3 operated by the first clock CK0 in real time. Can be output. In the pulse output circuit 8, the usual format processing is performed to obtain output pulses φA and φB which are, for example, a count pulse signal and a U / D signal or a two-phase square wave signal.
[0017]
FIG. 2 shows a specific circuit configuration of the buffer counter 3 and its surroundings. FIG. 2 shows an example in which the buffer counter 3 is configured by cascade connection of three 16-bit (including 1 bit as a sign bit) up / down counters 31a to 31b. The second and third stages each have an output enable ENOUT, which is an overflow output of the previous stage, as an input enable ENIN, and are an up / down counter capable of counting ± 2047 as a whole. To ensure the carry between the counters 31a, 31b, and 31c, the first clock CK0 is input to the clock terminal CKB of each stage with a slight delay through the buffer delay circuits 32 and 33.
[0018]
The most significant digit Q3 of the third stage counter 31c is used as the sign bit MINUS.
The all-zero detection circuit 4 includes NOR gates G41, G42, G43 for detecting that all digit outputs of the counters 31a to 31c are all zero, and a NAND gate G44 for detecting coincidence of these outputs. . Thus, the all-zero detection circuit 4 outputs AZ = 0 when the count value of the buffer counter 3 is zero, and outputs AZ = 1 otherwise.
[0019]
The clock gate 6 includes a NAND gate G61 for detecting a match between the second clock CK1 and the output AZ of the all-zero detection circuit 4, and an inverter gate G62. As a result, when AZ = 0, the clock gate 6 is turned off, and while the buffer counter 3 has a count value (AZ = 1), the second clock CK1 passes through the clock gate 6 and outputs the output enable signal OUTEN. Is taken out as
[0020]
The first stage counter 31a is provided with three mode control terminals, that is, terminals for selection signals SEL1 and SEL2 for selecting whether to count 1 or 2 and a terminal for an up / down selection signal UP. Table 2 below summarizes the combinations of the inputs of these three control terminals and the count mode.
[0021]
[Table 2]

[0022]
The counter control gate 7 is configured as shown in FIG. 2 so as to generate the control signals of Table 2 by a combination of the source count pulse PUEN, the up / down pulse U / D, the output enable signal OUTEN, and the sign bit MINUS. . EX / NOR gate G71 detects a match between PUEN and U / D and generates a selection signal SEL1. The EX / NOR gate G712 and the NAND gate G73 detect a match between MINUS and U / D, and detect a match between the detection result and PUEN and OUTEN to generate a selection signal SEL2. Further, the AND gates G74 and G75, the NOR gate G76, and the inverters G77 and G78 generate an up / down signal UP by a combination of MINUS, PUEN, and U / D.
[0023]
As described above, according to this embodiment, while counting the source count pulse by the buffer counter 3 operated by the high-speed first clock CK0, the count pulse is simultaneously output by the low-speed second clock CK1, and the count pulse is output. The count value of the buffer counter 3 is controlled to increase or decrease in real time by the output, and count pulses corresponding to the count value of the buffer counter 3 corresponding to the displacement amount are obtained. Therefore, even if the external counter has a low frequency, a high-speed moving speed of the displacement detector can be secured without being limited to this. Further, the output cycle counter 5 for generating the second clock CK1 for determining the frequency of the output counting pulse is made variable in frequency division ratio from the outside. For example, when the external counter can perform high-speed counting, the second clock CK1 is generated. Assuming that the frequency is the same as the first clock CK0, it can be connected to an external counter.
[0024]
In this embodiment, the number of digits of the buffer counter 3 is determined based on a balance between the moving range of the displacement detector 1 and the frequency of the output counting pulse. For example, if the number of digits is larger than the moving range, the output frequency can be lowered no matter how much, and since the internal counting is performed by the buffer counter 3 operated by a high-speed clock, the output frequency is lowered. The detector movement speed is not limited to a low range. Even if the number of digits is smaller than the displacement detector moving range, the count value of the buffer counter 3 is added or subtracted for each count pulse output in real time, so the output frequency is set high within the range of the countable frequency of the external counter. Then there is no problem. Thereby, the circuit scale can be reduced.
[0025]
FIG. 4 shows a configuration example of the counting pulse output circuit 8, and FIG. 5 shows an operation timing chart thereof. Although a detailed description is omitted, two D-type flip-flops FF1 and FF2 and gates G81 and G82 for determining inputs to the flip-flops FF1 and FF2 based on their outputs, the OUTEN signal and the MINUS signal are used. It outputs phase square wave outputs φA and φB.
[0026]
【The invention's effect】
As described above, according to the present invention, the source counter pulse is counted and the count pulse corresponding to the count value is simultaneously output by the second clock while using the buffer counter operated by the first clock. Thus, it is possible to provide a displacement measuring device capable of counting by a low-frequency external counter.
[Brief description of the drawings]
FIG. 1 shows a block configuration of a displacement measuring device according to an embodiment of the present invention.
FIG. 2 shows a specific configuration example of a main part of the embodiment.
FIG. 3 shows a relationship between first and second clocks of the embodiment.
FIG. 4 shows a specific configuration example of a pulse output circuit of the embodiment.
FIG. 5 shows an operation timing of the pulse output circuit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Displacement detector, 2 ... Source count pulse generation circuit, 3 ... Buffer counter, 4 ... All zero detection circuit, 5 ... Output cycle counter, 6 ... Clock gate, 7 ... Counter control gate, 8 ... Count pulse output circuit.

Claims (4)

A displacement measuring device that outputs a number of count pulses corresponding to a displacement amount to be counted by an external counter based on an output of a displacement detector,
A source which operates in synchronization with the first clock and outputs a source count pulse having a width corresponding to the amount of displacement detected by the displacement detector and an up / down pulse for instructing up / down in accordance with the direction of displacement. A counting pulse generating circuit;
A buffer counter that counts up / down the source count pulse with the first clock;
A pulse output circuit that operates with a second clock having a frequency equal to or lower than the first clock and generates the same number of count pulses as the count value of the buffer counter. apparatus. An output cycle counter that generates the second clock that determines the frequency of a count pulse to be output by dividing the first clock;
A clock gate which takes out the second clock as an output enable signal when the count value of the buffer counter is not zero and gives it to the pulse output circuit;
A counter control gate for performing control to increase or decrease the count value of the buffer counter in real time in accordance with the count pulse output from the pulse output circuit by a combination of the source count pulse, the up / down pulse, and the output enable signal. The displacement measuring device according to claim 1, wherein: The output cycle counter is configured so that the frequency of the second clock can be set to be equal to or lower than the frequency of the first clock by switching the frequency division ratio under the control of an external terminal. The displacement measuring device according to claim 2, wherein 4. The displacement measuring device according to claim 1, wherein an overflow terminal of the buffer counter is led out as an overspeed terminal.

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