JP2006318002A - Clock frequency-dividing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock frequency-dividing circuit which is capable of high-speed and stable switching and reducible in circuit scale. <P>SOLUTION: In synchronism with timing of variation of a frequency-division clock signal to a low level, the clock frequency dividing circuit sets (n)-bit frequency division ratio data corresponding to a frequency division ratio for a basic clock signal of the frequency-division clock signal and also sets (n)-bit 1/2 frequency-division ratio setting data obtained by halving the frequency-division clock ratio setting data. When count data from a counter match the 1/2 frequency-division ratio setting data, a frequency-division clock set signal for varying the frequency-division clock signal to a high level is generated. When the count data from the counter match the frequency-division ratio setting data, a frequency-division clock reset signal for varying the frequency-division clock signal to the low level is generated. The frequency-division clock signal is varied to the high level in accordance with the frequency clock set signal and varied to the low level in accordance with the frequency-division reset signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a clock divider circuit that outputs a divided clock obtained by dividing a basic clock, and more particularly to a clock divider circuit that can switch and output divided clocks having different frequencies.

  As a clock generation circuit capable of switching and outputting clocks having different frequencies, for example, a circuit using a clock frequency dividing circuit described in Patent Document 1 or Patent Document 2 is known. Each of the clock divider circuits described in these patent documents selects a plurality of dividers having different division ratios and a plurality of divided clocks output from each divider. And a circuit (switching circuit), which is capable of outputting divided clocks having different frequencies while preventing a so-called hazard occurring at the time of switching.

JP 2001-296937 A Japanese Patent Laid-Open No. 5-19892

  However, the clock frequency dividing circuits described in Patent Document 1 and Patent Document 2 are configured to include a number of frequency dividers corresponding to the number of frequency-divided clocks having different frequencies that can be output. In order to configure a clock frequency dividing circuit with an increased number of types of frequency of the peripheral clock, there is a problem that the number of frequency dividers increases by the increased type of frequency and the circuit scale increases.

  Further, in the clock frequency divider circuit described in Patent Document 1, the frequency-divided clocks are switched in such a way that all the frequency-divided clocks input from a plurality of frequency dividers to the switch circuit are low (L) level and the basic clock is high ( H) Since it is performed at the time of rising to the level, the time required for switching takes 1/2 to 1 cycle of the frequency-divided clock having the largest frequency-dividing ratio regardless of the type of frequency-divided clock to be output. In other words, there is a problem that the time required for switching is long.

  As described above, the conventional clock divider circuit has a problem in terms of circuit scale. In addition, there are cases where it is insufficient in terms of stable and high-speed switching of the divided clock.

  The present invention has been made in order to solve the above-described conventional problems, and provides a technique capable of stably switching at high speed and reducing the circuit scale in a clock divider circuit. Objective.

In order to achieve at least a part of the above object, a first clock divider circuit of the present invention includes:
A clock divider circuit that outputs a divided clock signal obtained by dividing a basic clock signal,
An n-bit counter (n is an integer of 2 or more) that outputs count data obtained by counting the number of clocks of the basic clock signal;
In synchronization with the timing of the change of the divided clock signal to the low level, n-bit division ratio setting data corresponding to the division ratio of the divided clock signal to the basic clock signal is set, and the divided frequency signal is set. A frequency division ratio setting unit for setting n-bit 1/2 frequency division ratio setting data obtained by halving the value of the ratio setting data;
A first compare circuit for generating a frequency-divided clock set signal for changing the frequency-divided clock signal to a high level when the count data from the counter matches the 1/2 frequency-dividing ratio setting data;
A second compare circuit for generating a frequency-divided clock reset signal for changing the frequency-divided clock signal to a low level when the count data from the counter matches the frequency-division ratio setting data;
A flip-flop circuit that changes the divided clock signal to a high level according to the divided clock set signal, and changes the divided clock signal to a low level according to the divided clock reset signal;
It is characterized by providing.

The second clock divider circuit of the present invention is
A clock divider circuit that outputs a divided clock signal obtained by dividing a basic clock signal,
An n-bit counter (n is an integer of 2 or more) that outputs count data obtained by counting the number of clocks of the basic clock signal;
In synchronization with the timing of the change of the divided clock signal to the low level, n-bit division ratio setting data corresponding to the division ratio of the divided clock signal to the basic clock signal is set, and the divided frequency signal is set. A frequency division ratio setting unit for setting n-bit 1/2 frequency division ratio setting data obtained by halving the value of the ratio setting data;
A first compare circuit that generates a frequency-divided clock set signal for changing the frequency-divided clock signal to a high level when the count data from the counter matches the frequency-division ratio setting data;
A second compare circuit for generating a frequency-divided clock reset signal for changing the frequency-divided clock signal to a low level when the count data from the counter matches the 1/2 frequency-dividing ratio setting data;
A flip-flop circuit that changes the divided clock signal to a high level according to the divided clock set signal, and changes the divided clock signal to a low level according to the divided clock reset signal;
It is characterized by providing.

  According to the first and second clock frequency dividing circuits, high-speed and stable switching can be performed, and the circuit scale can be reduced.

The frequency division ratio setting unit is m-bit frequency division for selecting one of the frequency division ratios corresponding to 2 ^m (m is an integer equal to or less than n-1) frequency division ratios. The ratio selection signal is taken in synchronization with the timing of the change of the divided clock signal to the low level, and the divided ratio selection signal taken in from the division ratio setting data corresponding to the 2 ^m division ratios. The division ratio setting data corresponding to may be selected.

In the first and second clock divider circuits,
The division ratio setting unit sets the division ratio setting data and the ½ division ratio setting data so as to generate a clock that is 16 times the transfer rate in asynchronous serial communication. Also good.

  In this way, the clock divider circuit of the present invention can be easily used for asynchronous serial communication.

  Note that the present invention is not limited to the above-described aspects of the invention, and can be realized in various aspects of an information processing apparatus such as a serial communication apparatus including a clock frequency dividing circuit.

Next, embodiments of the present invention will be described in the following order based on examples.
A. First embodiment:
A1. Configuration of clock divider circuit:
A2. basic action:
A3. Switching operation:
A4. Effects of the embodiment:
B. Second embodiment:
B1. Configuration and basic operation of clock divider:
B2. Switching operation:
B3. Effects of the embodiment:
C. Variations:

A. First embodiment:
A1. Configuration of clock divider circuit:
FIG. 1 is a block diagram showing a configuration of a clock frequency dividing circuit 100 as a first embodiment of the present invention. The clock frequency dividing circuit 100 includes a counter 10, two compare circuits 20, 30, a JK flip-flop 40, a latch 50, a frequency division ratio setting circuit 60, a 1/2 frequency division ratio setting circuit 70, And an inverter 80. Hereinafter, for convenience of explanation, the JK flip-flop may be simply referred to as a flip-flop.

The counter 10 is an n-bit counter (n is an integer of 2 or more) that counts the number of clocks at the rising edge timing of the clock signal input to the clock terminal (CK terminal). The basic clock signal RCK is input to the CK terminal of the counter 10, and the divided clock reset signal BRST output from the second compare circuit 30 is input to the clear terminal (CLR terminal). The n-bit preset terminal (P terminal: P0 to Pn) is fixed at the L level, and the preset count value is set to “0”. Therefore, the counter 10 changes the divided clock reset signal BRST input to the CLR terminal to the H level, and the value of the n-bit count signal CSIG output from the output terminal (QD terminal: QD0 to QDn) is “ The number from 0 to (2 ⁿ −1) is sequentially counted at the rising edge timing of the basic clock signal RCK input to the CK terminal until it is set to “0”.

  The two compare circuits 20 and 30 detect the coincidence between the n-bit signal input to the first input terminal (A terminal) and the n-bit signal input to the second input terminal (B terminal). The signal output from the output terminal (EQ terminal) changes to the H level when the two input signals match, and remains at the L level when they do not match.

  The count signal CSIG output from the counter 10 is input to the A terminal of the first compare circuit 20, and the 1/2 frequency division ratio setting output from the 1/2 frequency division ratio setting circuit 70 is input to the B terminal. The signal HBSIG is input. Therefore, the first compare circuit 20 outputs a signal that changes to the H level when the count signal CSIG and the 1/2 frequency division ratio setting signal HBSIG match. The output signal from the first compare circuit 20 is input to the J terminal of the flip-flop 40 as the divided clock set signal BSET. Note that the frequency division ratio is the frequency division number of the basic clock signal RCK and means the count value counted by the counter 10.

  The count signal CSIG output from the counter 10 is also input to the A terminal of the second compare circuit 30, and the frequency division ratio setting signal BSIG output from the frequency division ratio setting circuit 60 is input to the B terminal. Yes. Therefore, the second compare circuit 30 outputs a signal that changes to the H level when the count signal CSIG and the division ratio setting signal BSIG match. The output signal from the second compare circuit 30 is input to the K terminal of the flip-flop 40 and the CLR terminal of the counter 10 as the divided clock reset signal BRST.

The flip-flop 40 has an output terminal (Q terminal) at the rising edge timing of the basic clock signal RCK input to the clock input terminal (CK terminal) when the divided clock set signal BSET input to the J terminal is at the H level. ) Is changed to H level. The flip-flop 40 sets the divided clock signal BCK to L level at the rising edge timing of the basic clock signal RCK input to the CK terminal when the divided clock reset signal BRST input to the K terminal is at H level. Change.

  The latch 50 receives an m-bit (m is an integer less than or equal to 2 and less than n) clock selection signal SELD input to the data terminal (D terminal) and a rising edge of the clock signal input to the clock input terminal (LT terminal). Latching is performed at the timing, and the clock selection signal LSELD is output from the m-bit output terminal (Q terminal: Q0 to Qm). The clock selection signal LSELD is input to the frequency division ratio setting circuit 60.

  The frequency division ratio setting circuit 60 outputs an n-bit frequency division ratio setting signal BSIG corresponding to the input clock selection signal LSELD. The output frequency division ratio setting signal BSIG is input to the second input terminal (B terminal) of the second compare circuit 30 and the 1/2 frequency division ratio setting circuit 70.

FIG. 2 is a block diagram illustrating a configuration example of the frequency division ratio setting circuit 60. The frequency division ratio setting circuit 60 includes 2 ^m frequency division ratio setting registers 62 (0) to 62 (k) (k = 2 ^m −1) and a selector 64.

  In each of the frequency division ratio setting registers 62 (0) to 62 (k), the frequency division ratio corresponding to the frequency division clock to be set is set as n-bit data. The n-bit division ratio setting data BD (0) to BD (k) set for each is input to the input terminals A (0) to A (k) of the selector 64, respectively. Note that the set values of the frequency division ratio setting registers 62 (0) to 62 (k) can be set in advance to values desired by the user via a control circuit (not shown).

The selector 64 selects any one of the division ratio setting data BD (0) to BD (k) input to the [k + 1] (= 2 ^m ) input terminals A (0) to A (k). This is selected according to the m-bit clock selection signal LSELD input to the (SL terminal), and is output from the output terminal (SO) as the n-bit division ratio setting signal BSIG. For example, when m = 3, the clock selection data (binary number) represented by the 3-bit clock selection signal LSELD changes in the order of [000], [001], [010],..., [110], [111]. Then, the frequency division ratio setting data BD (0), BD (1), BD (2),..., BD (6), BD (7) are selected in accordance with this.

  The ½ division ratio setting circuit 70 in FIG. 1 is an n-bit ½ division ratio obtained by halving the value of the n-bit division ratio setting signal BSIG output from the division ratio setting circuit 60. A setting signal HBSIG is output. The output 1/2 division ratio setting signal HBSIG is input to the second input terminal (B terminal) of the first compare circuit 20. Note that the 1/2 frequency division ratio setting circuit is easily configured by using a bit shift operation circuit.

  FIG. 3 shows a specific example of setting the transfer rate, transfer clock, and division ratio when the clock divider circuit of this embodiment is used to generate a transfer clock corresponding to the transfer rate of asynchronous serial communication. It is explanatory drawing shown about.

  Asynchronous serial communication transfer rates correspond to six types of 4800 bps, 9600 bps, 19200 bps, 38400 bps, 57600 bps, and 115200 bps. In this case, assuming that the frequency of the transfer clock for each transfer rate is 16 times the frequency of each transfer rate, 76.8 kHz, 153.6 kHz, 307.2 kHz, 614.4 kHz, 921 in order from the lowest transfer rate. .6 kHz and 1843.2 kHz.

  When the frequency of the basic clock signal RCk is 14.7456 MHz, the frequency division ratios for generating each transfer clock are 192, 96, 48, 24, 16, and 8 in order from the lowest frequency.

  Then, the clock selection data [000], [001], [010], [011], [100], and [101] represented by the 3-bit clock selection signal SELD (LSELD) are assigned to each transfer rate. Assuming that the lower transfer rates are assigned in order, 8-bit data [10111111] (binary number) representing the division ratio 192 is used as the division ratio setting data BD (0) in the division ratio setting register 62 (0). Then, 8-bit data [0101111] representing the division ratio 962 is set as the division ratio setting data BD (1) in the division ratio setting register 62 (1), and the division ratio setting register 62 (2) is set. 8-bit data [00101111] representing the division ratio 48 is set as the division ratio setting data BD (2), and the division ratio 24 is displayed in the division ratio setting register 62 (3). 8-bit data [00010111] is set as the division ratio setting data BD (3), and 8-bit data [00001111] representing the division ratio 16 is set in the division ratio setting register 62 (4). This is set as BD (4), and 8-bit data [00000111] representing the division ratio 8 is set as the division ratio setting data BD (5) in the division ratio setting register 62 (5).

  By setting as described above, the clock frequency dividing circuit 100 according to the embodiment has 76.8 kHz, corresponding to six types of 4800 bps, 9600 bps, 1920 bps, 38400 bps, 57600 bps, and 115200 bps as transfer rates of asynchronous serial communication. Six types of transfer clocks of 153.6 kHz, 307.2 kHz, 614.4 kHz, 921.6 kHz, and 1843.2 kHz can be generated.

  In the case of six types of transfer rates, there is no transfer rate corresponding to the clock selection data [110] and [111] represented by the clock selection signal SELD. In such a case, for example, the same transfer rate as in [101] may be assigned. Of course, it may be in an unassigned state or may be assigned to another transfer rate.

  Next, in the following description, the clock frequency dividing circuit 100 according to the present embodiment is configured so that the number of bits of the clock selection signal SELD is m = 3, the number of bits of the counter is n = 8, and the conditions described in FIG. The basic operation and switching operation will be described as operating.

A2. basic action:
FIG. 4 is a timing chart showing the basic operation of the clock frequency dividing circuit 100. In this timing chart, the clock selection data represented by the 3-bit clock selection signal SELD (FIG. 4A) is represented by [101] (binary number) in order to facilitate the explanation of the divided clock generation operation in the clock divider circuit 100. ) And the division ratio is set to [8] (decimal number), and is latched at the falling edge timing of the divided clock signal BCK (FIG. 4 (i)) to latch 50 (FIG. 1). The clock selection data represented by the clock selection signal LSELD (FIG. 4B) output from is also shown as [101].

  In the case of the above premise, the frequency division ratio setting signal BSIG (FIG. 4C) output from the frequency division ratio setting circuit 60 (FIG. 1) is the counter 10 (FIG. 1) whose frequency division ratio corresponds to [8]. Is set to 8-bit frequency division ratio setting data [00000111] (binary number) representing the count value [7] (decimal number). Further, the ½ division ratio setting signal HBSIG (FIG. 4D) output from the ½ division ratio setting circuit 70 is an 8-bit ½ fraction representing the count value [3] of the counter 10. It is set in the circumferential ratio setting data [00000011].

  The 8-bit count signal CSIG (FIG. 4 (f)) output from the counter 10 is sequentially counted up from [0] to [7] at the rising edge timing of the basic clock signal RCK (FIG. 4 (e)). This is a count signal. In the example shown in the figure, the count value represented by the count signal CSIG is set to [0] at the rising edge timing of the basic clock RCK at time t0, and the count from [0] to [7] is repeated.

  When the count value of the count signal CSIG is counted up to [3] at the rising edge timing t3 of the basic clock signal RCK, this value matches the value of the 1/2 division ratio setting signal HBSIG. The set signal BSET (FIG. 4 (g)) changes to the H level. Then, at the next rising edge timing t4 of the basic clock signal RCK, the divided clock signal BCK (FIG. 4 (i)) is set to the H level.

  Next, when the count value of the count signal CSIG is counted up to [7] at the rising edge timing t7 of the basic clock signal RCK, this value matches the value of the frequency division ratio setting signal BSIG. The reset signal BRST (FIG. 4 (h)) changes to the H level. Then, at the next rising edge timing t10 of the basic clock signal RCK, the divided clock signal BCK is reset to the H level.

  Further, when the count value of the count signal CSIG is counted up to [3] at the rising edge timing t13 of the basic clock signal RCK, this value matches the value of the 1/2 frequency division ratio setting signal HBSIG. The peripheral clock set signal BSET changes to the H level. Then, at the next rising edge timing t14 of the basic clock signal RCK, the divided clock signal BCK is set to the H level.

  As a result, the frequency-divided clock signal BCK is a clock signal obtained by dividing the basic clock signal RCK by 8, that is, a clock signal in which eight cycles of the basic clock signal RCK are one cycle.

  In the above timing chart, the case where the clock selection data represented by the 3-bit clock selection signal SELD is [101] (binary number) and the division ratio is [8] (decimal number) is described as an example. Even when the clock selection data represented by the clock selection signal SELD is other than that, the frequency-divided clock signal BCK is a clock signal having a frequency-divided period corresponding to each frequency-dividing ratio.

A3. Switching operation:
FIG. 5 is a timing chart showing the switching operation of the divided clock output from the clock frequency dividing circuit 100. This timing chart shows the rising edge timing t10 of the basic clock signal RCK after the divided clock signal BCK (FIG. 5 (i)) falls at the rising edge timing t0 of the basic clock signal RCK (FIG. 5 (e)). The clock selection data represented by the clock selection signal SELD (FIG. 5 (a)) changes from [101] (binary number) to [100] at any time until it falls again at the time, and the division ratio is The case where the state is changed from [8] (decimal number) to [16] is shown as an example.

  In the case of the above assumption, until the divided clock signal BCK falls at the rising edge timing t10 of the basic clock signal RCK, the clock selection data represented by the clock selection signal LSELD after latching (FIG. 5B) is [ 101].

  When the divided clock signal BCK falls at the rising edge timing t10 of the basic clock signal RCK, the clock selection data [100] represented by the clock selection signal SELD is latched, and the clock selection data represented by the clock selection signal LSELD is [101]. ] To [100]. At this time, the frequency division ratio setting signal BSIG (FIG. 5C) is an 8-bit frequency division ratio setting data [00001111] (binary number) representing the count value [15] corresponding to the frequency division ratio [16]. The 1/2 dividing ratio setting signal HBSIG (FIG. 5D) is set to 8-bit 1/2 dividing ratio setting data [00000111] representing the count value [7].

  As a result, the 8-bit count signal CSIG (FIG. 5 (f)) output from the counter 10 is sequentially counted up from [0] to [15] at the rising edge timing of the basic clock signal RCK.

  When the count value of the count signal CSIG is counted up to [7] at the rising edge timing t17 of the basic clock signal RCK, this value is ½ division ratio setting data represented by the ½ division ratio setting signal HBSIG. Since it matches the value of [00000111], the divided clock set signal BSET (FIG. 5 (g)) changes to the H level. Then, at the next rising edge timing t18 of the basic clock signal RCK, the divided clock signal BCK is set to the H level.

  Next, when the count value of the count signal CSIG is counted up to [15] at the rising edge timing t1F of the basic clock signal RCK, this value is the frequency division ratio setting data [000011111] represented by the frequency division ratio setting signal BSIG. Therefore, the divided clock reset signal BRST (FIG. 5 (h)) changes to the H level. Then, at the next rising edge timing t20 of the basic clock signal RCK, the divided clock signal BCK is reset to the L level.

  Thereafter, the setting of the divided clock signal BCK to the H level and the resetting to the L level are repeated at the same timing. As a result, the divided clock signal BCK is a clock signal obtained by dividing the basic clock signal RCK by 16, that is, a clock signal obtained by dividing the basic clock signal RCK by 8, that is, a clock signal having one cycle of eight cycles of the basic clock signal RCK. The signal, that is, the clock signal having the 16 cycles of the basic clock signal RCK as one cycle is switched.

  Here, the divided clock signal BCK after the divided clock signal BCK rises at the rising edge timing t18 of the basic clock signal RCK operates as a clock signal obtained by dividing the basic clock signal RCK by 16. Therefore, the time required to switch from the clock signal obtained by dividing the basic clock signal RCK by 8 to the clock signal obtained by dividing the basic clock signal RCK by 16 is the rising edge timing t10 of the basic clock signal RCK. It can be defined as the time from when the clock selection data [100] represented by SELD is latched to the rising edge timing t18 of the basic clock signal RCK until the divided clock signal BCK rises. This time is [8 · Tr] when the cycle of the basic clock signal RCK is Tr, and corresponds to a half cycle of the cycle [16 · Tr] of the divided clock signal BCK after switching.

  In the timing chart, the clock selection data represented by the clock selection signal SELD is switched from [101] to [100], and the basic clock signal RCK is divided into 16 minutes from the state of the clock signal obtained by dividing the basic clock signal RCK by 8. The case of switching to the state of the clock signal that has been rotated has been described as an example, but the same applies to other switching cases.

A4. Effects of the embodiment:
The clock frequency dividing circuit 100 of the present embodiment can switch the frequency of the frequency-divided clock to be output using one counter 10 without using a plurality of frequency dividers having different frequency dividing ratios. The circuit scale can be reduced as compared with the circuit.

  Further, the clock frequency dividing circuit 100 according to the present embodiment latches the clock selection signal SELD to be applied at the falling edge timing of the frequency-divided clock signal BCK, so that the frequency-dividing ratio of the frequency-divided clock signal BCK and ½ A second compare circuit 30 that sets a division ratio and outputs a reset signal for a divided clock detects a count value corresponding to the set division ratio and outputs a set signal for the divided clock. Since the count value corresponding to the set 1/2 frequency dividing ratio is detected by the compare circuit 20, the occurrence of a so-called hazard at the time of switching can be prevented and stable switching can be realized.

  Furthermore, the clock frequency dividing circuit 100 according to the present embodiment can set the time required for switching to a time corresponding to a half cycle of the frequency-divided clock signal BCK after switching, so that high-speed switching is possible. .

  As described above, the clock frequency dividing circuit 100 of this embodiment can be switched at high speed and stably, and the circuit scale can be reduced.

B. Second embodiment:
B1. Configuration and basic operation of clock divider:
FIG. 6 is a block diagram showing a configuration of a clock frequency dividing circuit 100A as a second embodiment of the present invention. The frequency dividing circuit 100A inputs a frequency dividing ratio setting signal BSIG, which is an output of the frequency dividing ratio setting circuit 60, to the B terminal of the first compare circuit 20, and outputs 1/2 of the 1/2 frequency dividing ratio setting circuit 70. Except that the division ratio setting signal HBSIG is input to the second compare circuit 30, and the divided clock set signal BSET output from the EQ terminal of the first compare circuit 20 is input to the CLR terminal of the counter 10. Thus, it has the same configuration as the clock divider circuit of the first embodiment.

  The clock frequency dividing circuit 100A according to the present embodiment has a timing at which the frequency-divided clock set signal BSET output from the first compare circuit 20 changes to the H level and the second compare circuit 30 due to the difference in configuration. The timing at which the frequency-divided clock reset signal BRST output from H changes to the H level is opposite to that in the first embodiment, and the rise of the frequency-divided clock BCK output from the flip-flop 40 is the timing. Although the falling timing is opposite to that in the first embodiment, a divided clock signal corresponding to the set division ratio can be output as in the first embodiment. .

B2. Switching operation:
The clock frequency dividing circuit 100A of the present embodiment differs from the first embodiment as described below due to the above differences in the time required for clock switching. In the following, as in the case of the description of the switching operation in the first embodiment, the clock frequency dividing circuit 100A of this embodiment is configured such that the number of bits of the clock selection signal SELD is m = 3 and the number of bits of the counter is n. = 8 and the operation is performed under the conditions described in FIG.

  FIG. 7 is a timing chart showing the switching operation of the divided clock output from the clock divider circuit 100A. This timing chart shows the divided clock signal BCK (FIG. 7 (i)) at the rising edge timing t4 of the basic clock signal RCK (FIG. 7 (e)), similarly to the switching operation in the first embodiment (see FIG. 5). ) Has fallen, and at any time until it falls again at the rising edge timing t14 of the basic clock signal RCK, the clock selection data represented by the clock selection signal SELD (FIG. 7A) is [101]. In the example, the value is changed from (binary number) to [100], and the frequency division ratio is changed from [8] (decimal number) to [16].

  In the case of the above assumption, until the divided clock signal BCK falls at the rising edge timing t14 of the basic clock signal RCK, the clock selection data indicated by the clock selection signal LSELD after latching (FIG. 7B) is [ 101].

  When the divided clock signal BCK falls at the rising edge timing t14 of the basic clock signal RCK, the clock selection data [100] represented by the clock selection signal SELD is latched, and the clock selection data represented by the clock selection signal LSELD is [101]. ] To [100]. At this time, the frequency division ratio setting signal BSIG (FIG. 7C) is an 8-bit frequency division ratio setting data [00001111] (binary number) representing the count value [15] corresponding to the frequency division ratio [16]. The 1/2 dividing ratio setting signal HBSIG (FIG. 5D) is set to 8-bit 1/2 dividing ratio setting data [00000111] representing the count value [7].

  As a result, the 8-bit count signal CSIG (FIG. 7 (f)) output from the counter 10 is sequentially counted up from [0] to [15] at the rising edge timing of the basic clock signal RCK.

  When the count value of the count signal CSIG is counted up to [7] at the rising edge timing t17 of the basic clock signal RCK, this value is ½ division ratio setting data represented by the ½ division ratio setting signal HBSIG. Since it matches the value of [00000111], the divided clock reset signal BRST (FIG. 7 (h)) changes to the H level. Then, at the next rising edge timing t18 of the basic clock signal RCK, the divided clock signal BCK is reset to the L level. However, since the divided clock signal BCK has already been reset at the rising edge timing t14 of the basic clock signal RCK, nothing changes at the rising edge timing t18 of the basic clock signal RCK.

  Next, when the count value of the count signal CSIG is counted up to [15] at the rising edge timing t1F of the basic clock signal RCK, this value is the frequency division ratio setting data [000011111] represented by the frequency division ratio setting signal BSIG. Therefore, the divided clock set signal BSET (FIG. 7 (g)) changes to the H level. Then, at the next rising edge timing t20 of the basic clock signal RCK, the divided clock signal BCK is set to the H level.

  Thereafter, resetting the divided clock signal BCK to the L level and setting to the H level are repeated at the same timing. As a result, the divided clock signal BCK is switched from the clock signal obtained by dividing the basic clock signal RCK by 8 to the clock signal obtained by dividing the basic clock signal RCK by 16.

  Here, the time required to switch from the clock signal obtained by dividing the basic clock signal RCK by 8 to the clock signal obtained by dividing the basic clock signal RCK by 16 is selected at the rising edge timing t14 of the basic clock signal RCK. It can be defined as the time from when the clock selection data [100] represented by the signal SELD is latched to when the divided clock signal BCK rises at the rising edge timing t20 of the basic clock signal RCK. This time is [12 · Tr], where Tr is the period of the basic clock signal RCK, and corresponds to 3/4 period of the period [16 · Tr] of the divided clock signal BCK after switching.

  In the timing chart, the clock selection data represented by the clock selection signal SELD is switched from [101] to [100], and the basic clock signal RCK is divided into 16 minutes from the state of the clock signal obtained by dividing the basic clock signal RCK by 8. The case of switching to the state of the clock signal that has been rotated has been described as an example, but the same applies to other switching cases. However, the time required for switching is a value obtained by subtracting the 1/2 frequency division ratio of the clock before switching from the frequency division ratio of the clock after switching. For example, when the division ratio before switching is [8] and the division ratio after switching is [192], the time required for switching is [188 · Tr]. That is, as the difference between the divide ratio after switching and the ½ divider ratio before switching increases, the time required for switching becomes closer to one cycle of the divided clock signal after switching, and the difference becomes smaller. Indeed, it becomes closer to a half cycle of the divided clock signal after switching. However, switching is possible at least within the cycle of the divided clock signal BCK after switching.

B3. Effects of the embodiment:
In the clock frequency dividing circuit 100A according to the present embodiment, similarly to the first embodiment, a single counter 10 is used to output a divided clock to be output without using a plurality of frequency dividers having different frequency division ratios. Since the frequency can be switched, the circuit scale can be reduced as compared with the conventional circuit.

  Also in the clock frequency dividing circuit 100A of the present embodiment, the clock selection signal SELD is latched at the falling edge timing of the frequency divided clock signal BCK, so that the frequency dividing ratio of the frequency divided clock signal BCK and the 1 / The second compare circuit 30 that sets the divide-by-2 ratio and outputs the reset signal of the divided clock detects the count value of the counter corresponding to the set divide-by-2 ratio, and sets the divided clock Since the count value of the counter corresponding to the set frequency division ratio is detected by the first compare circuit 20 that outputs a signal, it is possible to prevent the occurrence of a so-called hazard at the time of switching and to realize stable switching. it can.

  Furthermore, the clock frequency dividing circuit 100A according to the present embodiment can set the time required for switching to a time within one cycle of the frequency-divided clock signal BCK after switching, so that high-speed switching is possible.

  As described above, the clock frequency dividing circuit 100A according to the present embodiment can be switched at high speed and stably, and the circuit scale can be reduced.

C. Variations:
Note that the present invention is not limited to the above-described embodiment, and can be implemented in various modes without departing from the scope of the invention.

C1. Modification 1:
In the above-described embodiment, based on the 3-bit clock selection signal SELD, an 8-bit counter is prepared in advance among the division ratios corresponding to 256 types of divided clock signals that can be output as the divided clock signal BCK. A specific example is described of a configuration in which one frequency division ratio is set from the eight frequency division ratios and a frequency division clock signal corresponding to the set frequency division ratio is generated. However, the present invention is not limited to this, and a configuration in which one type is selected from a plurality of types of division ratios prepared in advance and a divided clock corresponding to the set division ratio may be generated. . However, in this case, the latch 50 is configured to be able to latch a clock selection signal having the number of bits required to select and set one type from a plurality of types, and a plurality of selectors 64 constituting the division ratio setting circuit 60 are provided. It is necessary to adopt a configuration in which one type is selected from the types of frequency division ratio setting data.

  Further, the counter sets one division ratio from the division ratios corresponding to all kinds of divided clock signals that can be output as a divided clock signal by the counter, and the divided clock signal corresponding to the set division ratio. The structure which produces | generates may be sufficient. In this case, the frequency division ratio setting circuit 60 can be omitted.

C2. Modification 2:
In the above embodiment, it has been described that each division ratio setting register 62 of the division ratio setting circuit 60 can be set to a value desired by the user in advance via a control circuit (not shown). Data is stored and may not be rewritten. Further, when the data is fixed in advance, a storage circuit such as the frequency division ratio setting register 62 can be omitted.

C3. Modification 3:
Note that the clock divider circuit of the above embodiment generates a clock 16 times the serial communication transfer rate and performs asynchronous serial communication, or an information processing apparatus including such a serial communication device. It can be used as a clock generation circuit provided in various information processing apparatuses such as.

1 is a block diagram showing a configuration of a clock frequency dividing circuit 100 as a first embodiment of the present invention. FIG. 3 is a block diagram illustrating a configuration example of a frequency division ratio setting circuit 60. FIG. FIG. 4 is an explanatory diagram showing a specific example of setting a transfer rate, a transfer clock, and a frequency division ratio when the clock frequency dividing circuit according to the present embodiment is used to generate a transfer clock corresponding to the transfer rate of asynchronous serial communication. is there. 3 is a timing chart showing the basic operation of the clock divider circuit 100. 4 is a timing chart showing a switching operation of a divided clock output from the clock divider circuit 100. It is a block diagram which shows the structure of 100 A of clock frequency dividing circuits as 2nd Example of this invention. It is a timing chart showing the switching operation of the divided clock output from the clock divider circuit 100A.

Explanation of symbols

100 ... Clock divider circuit 100A ... Divider circuit 10 ... Counter 20 ... First compare circuit 30 ... Second compare circuit 30 ... Second compare circuit 40 .. .JK flip-flop 50 ... Latch 60 ... Division ratio setting circuit 62 ... Division ratio setting register 64 ... Selector 80 ... Inverter

Claims (6)

A clock divider circuit that outputs a divided clock signal obtained by dividing a basic clock signal,
An n-bit counter (n is an integer of 2 or more) that outputs count data obtained by counting the number of clocks of the basic clock signal;
In synchronization with the timing of the change of the divided clock signal to the low level, n-bit division ratio setting data corresponding to the division ratio of the divided clock signal to the basic clock signal is set, and the divided frequency signal is set. A frequency division ratio setting unit for setting n-bit 1/2 frequency division ratio setting data obtained by halving the value of the ratio setting data;
A first compare circuit for generating a frequency-divided clock set signal for changing the frequency-divided clock signal to a high level when the count data from the counter matches the 1/2 frequency-dividing ratio setting data;
A second compare circuit for generating a frequency-divided clock reset signal for changing the frequency-divided clock signal to a low level when the count data from the counter matches the frequency-division ratio setting data;
A flip-flop circuit that changes the divided clock signal to a high level according to the divided clock set signal, and changes the divided clock signal to a low level according to the divided clock reset signal;
A clock frequency dividing circuit comprising: A clock divider circuit that outputs a divided clock signal obtained by dividing a basic clock signal,
An n-bit counter (n is an integer of 2 or more) that outputs count data obtained by counting the number of clocks of the basic clock signal;
In synchronization with the timing of the change of the divided clock signal to the low level, n-bit division ratio setting data corresponding to the division ratio of the divided clock signal to the basic clock signal is set, and the divided frequency signal is set. A frequency division ratio setting unit for setting n-bit 1/2 frequency division ratio setting data obtained by halving the value of the ratio setting data;
A first compare circuit that generates a frequency-divided clock set signal for changing the frequency-divided clock signal to a high level when the count data from the counter matches the frequency-division ratio setting data;
A second compare circuit for generating a frequency-divided clock reset signal for changing the frequency-divided clock signal to a low level when the count data from the counter matches the 1/2 frequency-dividing ratio setting data;
A flip-flop circuit that changes the divided clock signal to a high level according to the divided clock set signal, and changes the divided clock signal to a low level according to the divided clock reset signal;
A clock frequency dividing circuit comprising: A clock divider circuit according to claim 1 or claim 2,
The division ratio setting unit selects an m-bit division ratio for selecting one division ratio among the division ratios corresponding to 2 ^m (m is an integer equal to or less than n−1) division ratios. The signal is acquired in synchronization with the timing of the change of the frequency-divided clock signal to the low level, and the frequency-division ratio selection signal corresponding to the acquired frequency-division ratio setting data corresponding to 2 ^m frequency-dividing ratios is supported. A clock divider circuit that selects the division ratio setting data to be selected. A clock divider circuit according to any one of claims 1 to 3,
The division ratio setting unit sets the division ratio setting data and the ½ division ratio setting data so as to generate a clock that is 16 times the transfer rate in asynchronous serial communication. A clock divider circuit.   A serial communication device comprising the clock frequency dividing circuit according to claim 4 and performing asynchronous serial communication.   An information processing apparatus comprising the serial communication apparatus according to claim 5.

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