JP2001127618A - Clock signal generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a clock signal generating circuit that can generate a clock signal with an optional frequency division ration. SOLUTION: The clock signal generating circuit that applies frequency- division to a system clock, is provided with an adder that sums external input data and a preceding sum result and a storage means that stores the result of sum of this adder synchronously with the system clock and supplies the output to the adder as the preceding sum result, and extracts the most significant bit of the output of the storage means as a clock signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal generating circuit for generating a reference clock signal or the like by dividing a system clock, and more particularly to a clock signal capable of generating a clock signal having an arbitrary dividing ratio. It relates to a generating circuit.

[0002]

2. Description of the Related Art In a conventional clock signal generating circuit, a system clock is appropriately divided by a frequency divider to generate a clock signal having a desired frequency. FIG. 6 is a configuration block diagram showing an example of such a conventional clock signal generation circuit. In FIG. 6, 1 is a frequency divider, 100 is a system clock, and 101 is a generated clock signal.

[0003] A system clock 100 is input to a frequency divider 1, and a clock signal 101 is output from the frequency divider 1.
For example, when the frequency division ratio of the frequency divider is “4”, the clock signal 101 having a frequency １ ／ of the system clock 100 is used.
Is output.

[0004]

However, in the conventional example shown in FIG. 6, if the frequency of the system clock 100 is not an integral multiple of the frequency of the clock signal to be generated, the clock signal generated cannot be properly divided. And a desired frequency will occur.

[0005] When such a clock signal is used as a communication reference clock for asynchronous communication, there has been a problem that a communication error may occur due to an error in the frequency of the generated clock signal.

For example, FIG. 7 is a timing chart for explaining a situation in which such a communication error occurs. In FIG. 7, (a) is a communication reference clock on the transmission side, (b) is transmission data from the transmission side, (c) is a communication reference clock on the reception side,
(D) is data received on the receiving side.

In FIG. 7, since the frequency of the communication reference clock (c) on the receiving side is lower than the frequency of the communication reference clock (a) on the transmitting side, the reception data (d) is synchronized with the communication reference clock of this small frequency. ), A communication error occurs in the data preceding the portion indicated by "ER01" in FIG. Therefore, an object of the present invention is to realize a clock signal generation circuit capable of generating a clock signal having an arbitrary frequency division ratio.

[0008]

To achieve the above object, according to the present invention, there is provided a clock signal generating circuit for dividing a system clock to generate a clock signal. An adder for adding the input data and the previous addition result; and storage means for storing the addition result of the adder in synchronization with the system clock and supplying an output to the adder as the previous addition result. By extracting the most significant bit of the output of the storage means as the clock signal, it is possible to generate a clock signal having an arbitrary frequency division ratio.

According to a second aspect of the present invention, in the clock signal generating circuit according to the first aspect, the value of the external input data is "n", and the number of bits of the adder and the storage means is "m". And the frequency division ratio is “2 ^m /
By setting n ”, it becomes possible to generate a clock signal having an arbitrary frequency division ratio.

According to a third aspect of the present invention, in a clock signal generating circuit for generating a clock signal by dividing a system clock, an adder for adding external input data and a previous addition result, and an adder for the adder Storage means for storing a result in synchronization with the system clock and supplying an output to the adder as the previous addition result; and switching between first and second values based on the magnitude of the output of the storage means. A data selector circuit for supplying the external input data to the adder, and by taking out the most significant bit of the output of the storage means as the clock signal, it is possible to generate a clock signal having an arbitrary frequency division ratio. Become.

According to a fourth aspect of the present invention, in the clock signal generating circuit according to the third aspect of the present invention, the number of bits of the adder and the storage means is "r", and the first value is "n". When the second value is "n + 2 ^r -k", the data selector circuit determines that the output of the storage means is smaller than "2 ^r-1 -n + k / 2". By selecting a value and selecting the second value in the case of “2 ^r−1 −n + k / 2” or more, it becomes possible to generate a clock signal having an arbitrary frequency division ratio.

According to a fifth aspect of the present invention, in the clock signal generating circuit according to the fourth aspect, the number of bits of the adder and the storage means is "r", and the first value is "n". When the second value is “n + 2 ^r −k”, the frequency division ratio becomes “k / n”, so that a clock signal having an arbitrary frequency division ratio can be generated.

According to a sixth aspect of the present invention, in the clock signal generating circuit according to the third aspect of the present invention, one of a plurality of values having different values is selected by a selection signal and the data selector is used as the first value. With the provision of the second data selector circuit for supplying the circuit, a clock signal generation circuit having a plurality of frequency division ratios can be configured.

According to a seventh aspect of the present invention, in the clock signal generating circuit according to the sixth aspect of the present invention, when the value selected by the second data selector circuit is "ni", the frequency division ratio is increased. By setting “k / ni”, a clock signal generation circuit having a plurality of frequency division ratios can be configured.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 is a configuration diagram showing one embodiment of a clock signal generation circuit according to the present invention. In FIG. 1, reference numeral 2 denotes an m-bit adder, 3 denotes an m-bit D-type flip-flop circuit serving as data storage means one clock before, 100a denotes a system clock, 102 denotes external input data having a value of n, 1
03 is an m-bit output signal of the D-type flip-flop circuit 3, and 104 is a clock signal which is the most significant bit of the m-bit output signal of the output signal 103.

The system clock 100a is input to the clock input terminal of the D-type flip-flop circuit 3, and the external input data 102 is input to one input terminal of the adder 2.

The output of the adder 2 is connected to the input terminal of the D-type flip-flop circuit 3, and the output signal 103 of the D-type flip-flop circuit 3 is connected to the other input terminal of the adder 2. The most significant bit of the output signal 103 is output as the clock signal 104.

The operation of the embodiment shown in FIG. 1 will be described with reference to FIG. FIG. 2 is a timing chart for explaining the operation of FIG. In FIG. 2, (a) shows the system clock 1
00a and (b) show the output signal 103 of the D-type flip-flop circuit 3, and (c) shows the clock signal 104 which is the most significant bit of the output signal 103.

At the timing shown in FIG. 2, the external input data 102 is 3 (n = 3), and the adder 2 and the D-type flip-flop circuit 3 are 3 bits (m = 3 bits). Notations such as "001" and "111" indicate 3-bit data expressed in binary.

It is assumed that the output signal 103 is "000" at the timing indicated by "T001" in FIG. At this time, since the most significant bit of the output signal 103 is “0”, the level of the clock signal 104 becomes “0”.
Is the result of addition of the output signal 103 and the external input data 102, so that "000 + 011 = 011" is obtained.

Then, at the timing indicated by "T002" in FIG. 2, "011" which is the addition result is taken into the D-type flip-flop circuit 3 in synchronization with the system clock 100a, and the output signal 103 changes to "011". I do.

At this time, since the most significant bit of the output signal 103 is "0", the level of the clock signal 104 becomes "0".
0 ". On the other hand, the output of the adder 2 is the result of addition of the output signal 103 and the external input data 102.
+ 011 = 110 ".

Then, at the timing indicated by "T003" in FIG. 2, the addition result "110" is taken into the D-type flip-flop circuit 3 in synchronization with the system clock 100a, and the output signal 103 changes to "110". I do.

At this time, since the most significant bit of the output signal 103 is "1", the level of the clock signal 104 is "1".
1 ". On the other hand, since the output of the adder 2 is a result of addition of the output signal 103 and the external input data 102," 110 "
+ 011 = 001 ". Similarly, the clock signal 104 is generated.

In FIG. 2, for example, the output signal 103
Changes from “110” to “011” as described above,
This is sequentially and repeatedly generated with the cycle indicated by “PD01” in FIG. 2 as one cycle.

That is, the frequency of the clock signal 104 is "C" in FIG.
Since the clocks for three periods shown in P01, CP02, and CP03 are generated, the frequency is "3 /
8 ", in other words, the frequency division ratio is" 8/3 ".

Here, the value of the external input data 102 is
n ", the adder 2 and the D-type flip-flop circuit 3 have the frequency division ratio" DR1 "if the number of bits is" m bits ".
Is DR1 = 2 ^m / n (1). However, “2 ^m > n”.

As a result, the addition result of the external input data 102 and the output of the D-type flip-flop circuit 3 is sequentially stored in the D-type flip-flop circuit 3, and the most significant bit of the output signal of the D-type flip-flop circuit 3 is extracted. This makes it possible to generate a clock signal having an arbitrary frequency division ratio.

FIG. 3 is a block diagram showing another embodiment of the clock signal generating circuit according to the present invention. 3, 4 is a data selector circuit, 5 is an r-bit adder, 6 is an r-bit D-type flip-flop circuit, 100b is a system clock, and 103a is a D-type flip-flop circuit 3.
, 104a is a clock signal that is the most significant bit of the r-bit output signal of the output signal 103a, 105 is external input data having a value of “n”, and 106 is a value of “n + 2 ^r −k”. "Is the external input data.

The system clock 100b is input to the clock input terminal of the D-type flip-flop circuit 6, and external input data 105 and 106
Input to each of the two input terminals.

The output of the data selector circuit 4 is connected to one input terminal of an adder 5, and the output of the adder 5 is connected to the input terminal of a D-type flip-flop circuit 6.

The output signal 103a of the D-type flip-flop circuit 6 is connected to the control terminal of the data selector circuit 4 and the other input terminal of the adder 5, respectively. Further, the most significant bit of the output signal 103a is the clock signal 1
04a is output.

The operation of the embodiment shown in FIG. 3 will now be described with reference to FIG. FIG. 4 is a timing chart for explaining the operation of FIG. In FIG. 4, (a) shows the system clock 1
00b and (b) show the output signal 103a of the D-type flip-flop circuit 6, and (c) shows the clock signal 104a which is the most significant bit of the output signal 103a.

The data selector circuit 4 selects the external input data 106 if the input value of the control terminal, in other words, the output of the D-type flip-flop circuit 6 is "2 ^r-1 -n + k / 2" or more. If the output of the D-type flip-flop circuit 6 is smaller than "2 ^r-1 -n + k / 2", the external input data 105 is selected and output.

Further, at the timing shown in FIG. 4, the external input data 105 is 3 (n = 3), the adder 5 and the D flip-flop circuit 6 are 4 bits (r = 4 bits), and the external input data 106 is 9 (r = 4 bits). k = 10, n + 2 ^r −k = 3 +
2 ⁴ −10 = 3 + 16−10 = 9). Also, “0”
Notations such as "001" and "1111" indicate 4-bit data expressed in binary.

At the timing indicated by "T101" in FIG. 4, the output signal 103a is assumed to be "0000". At this time, since the most significant bit of the output signal 103a is "0", the level of the clock signal 104a becomes "0".

On the other hand, the output signal 103a is "2 ^r-1 -n +
Since k / 2 = 2 ³ −3 + 10/2 = 10 ”, the data selector circuit 4 outputs the external input data 1 having the value“ 3 ”.
05 is selectively output.

For this reason, the output of the adder 5 is the output signal 10
3a and the result of adding the external input data 105.
0000 + 0011 = 0011 ".

Then, at the timing shown by "T102" in FIG. 4, "0011" which is the addition result is taken into the D-type flip-flop circuit 6 in synchronization with the system clock 100b, and the output signal 103a changes to "0011". I do.

At this time, since the most significant bit of the output signal 103a is "0", the level of the clock signal 104a is "0".
0 ".

On the other hand, the output signal 103a is "2 ^r-1 -n +
Since k / 2 = 2 ³ −3 + 10/2 = 10 ”, the data selector circuit 4 outputs the external input data 1 having the value“ 3 ”.
05 is selectively output.

Therefore, the output of the adder 5 is the output signal 10
3a and the result of adding the external input data 105.
0011 + 0011 = 0110 ″.

Then, at the timing indicated by "T103" in FIG. 4, "0110" which is the addition result is taken into the D-type flip-flop circuit 6 in synchronization with the system clock 100b, and the output signal 103a changes to "0110". I do.

At this time, since the most significant bit of the output signal 103a is "0", the level of the clock signal 104a becomes "0".
0 ".

On the other hand, the output signal 103a is "2 ^r-1 -n +
Since k / 2 = 2 ³ −3 + 10/2 = 10 ”, the data selector circuit 4 outputs the external input data 1 having the value“ 3 ”.
05 is selectively output.

Therefore, the output of the adder 5 is the output signal 10
3a and the result of adding the external input data 105.
0110 + 0011 = 1001 ".

Then, at the timing indicated by "T104" in FIG. 4, "1001" as the addition result is taken into the D-type flip-flop circuit 6 in synchronization with the system clock 100b, and the output signal 103a changes to "1001". I do.

At this time, since the most significant bit of the output signal 103a is "1", the level of the clock signal 104a is "1".
1 ".

On the other hand, the output signal 103a is "2 ^r-1 -n +
Since k / 2 = 2 ³ −3 + 10/2 = 10 ”, the data selector circuit 4 outputs the external input data 10 having the value“ 3 ”.
5 is selectively output.

Therefore, the output of the adder 5 is the output signal 10
3a and the result of adding the external input data 105.
1001 + 0011 = 1100 ".

Then, at the timing indicated by "T105" in FIG. 4, "1100" which is the addition result is taken into the D-type flip-flop circuit 6 in synchronization with the system clock 100b, and the output signal 103a changes to "1100". I do.

At this time, since the most significant bit of the output signal 103a is "1", the level of the clock signal 104a is "1".
1 ".

On the other hand, the output signal 103a is "2 ^r-1 -n +
Since k / 2 = 2 ³ −3 + 10/2 = 10 ”or more, the value of the data selector circuit 4 is“ 9 (= n + 2 ^r −k = 3 +).
2 ⁴ −10 = 3 + 16−10) ”external input data 10
6 is selectively output.

Therefore, the output of the adder 5 is the output signal 10
3a and the result of adding the external input data 106.
1100 + 1001 = 0101 ". Similarly, the clock signal 104a is generated.

In FIG. 4, for example, the output signal 103
“a” changes from “0110” to “0011” as described above, and this is sequentially and repeatedly generated with the cycle indicated by “PD11” in FIG. 4 as one cycle.

That is, the frequency of the clock signal 104a is as shown in FIG.
Since the clocks for three cycles shown in the middle “CP11”, “CP12” and “CP13” are generated, the frequency is “3”.
/ 10 ", in other words, the frequency division ratio is" 10/3 ".

Here, the value of the external input data 105 is set to “
n ”, the adder 5 and the D-type flip-flop circuit 6 set the number of bits to“ r bits ”and set the value of the external input data 106 to“ n ”.
+2 ^r -k ", the frequency division ratio" DR2 "becomes DR2 = k / n (2), where"r> n, k is an even number ".

As a result, the external input data 1 selected based on the magnitude of the output signal of the D-type flip-flop circuit 6
05 or 106 and the output of the D-type flip-flop circuit 6 are sequentially stored in the D-type flip-flop circuit 6, and the most significant bit of the output signal of the D-type flip-flop circuit 6 is taken out to obtain an arbitrary frequency division. It is possible to generate a clock signal having a ratio.

FIG. 5 is a block diagram showing another embodiment of the clock signal generating circuit according to the present invention. In FIG. 5, reference numeral 7 denotes a data selector circuit which is a frequency division ratio selection means, 8 denotes a clock signal generation circuit described in FIG. 3, 100c denotes a system clock, 104b denotes a clock signal, 107a and 10
7b and 107c are external input data, 108 is a selection signal, and 109 is an output signal of the data selector circuit 7.

The system clock 100c is input to the clock input terminal of the D-type flip-flop circuit 6 constituting the clock signal generating circuit 8, and receives the external input data 107a to 107c.
Reference numeral 107c is input to each of the plurality of input terminals of the data selector circuit 7.

The output signal 109 of the data selector circuit 7 is connected to the input terminal of the data selector circuit 4 constituting the clock signal generating circuit 8, and the selection signal 108 is connected to the control terminal of the data selector circuit 7. The clock signal generation circuit 8 outputs a clock signal 104b.

Here, the operation of the embodiment shown in FIG. 5 will be described. However, the description of the part relating to the clock signal generation circuit 8 described above is omitted, and the value is merely an arbitrary value.
It is assumed that inputting "n" operates at the frequency division ratio "k / n".

The external input data 107a to 107c have different values "na", "nb" and "nc", respectively, and all the values are smaller than "k" described in FIG. Then, the data selector circuit 7 outputs the external input data 107a to 107
c is selected and supplied to the clock signal generation circuit 8.

For this reason, the clock signal generating circuit 8 has a frequency division ratio of “k / n” according to the selected external input data.
a "," k / nb "and" k / nc ".

As a result, by providing division ratio selection means for selecting and supplying a value of “n” to be input to the clock signal generation circuit 8 having a division ratio of “k / n” from a plurality of values, A clock signal generation circuit having a plurality of frequency division ratios can be configured.

Although the external input data 105 and 106 are merely described in the embodiment shown in FIG. 3, data satisfying the respective values of the external input data 105 and 106 may be individually input from the outside. And the value "n" and the value "
k "may be individually input to calculate internally the external input data 105 and 106 and apply the same to the data selector circuit 4. Further, only the external input data 105 is input and the value" k "is fixed. The external input data 106
May be calculated and applied to the data selector circuit 4.

In the description of the operation of the embodiment shown in FIG. 3, "k" is set to only an even number. However, if "k" is to be set to an odd number, the values of "k" and "n" are respectively set. By doubling, "k" is treated as an even number, so that setting can be made. For example, if "k = 14" and "n = 6" to set the frequency division ratio of "7/3", the frequency division ratio becomes "14/6 = 7/3".

Also, as the storage means shown in FIGS. 1 and 3 and the like, a D-type flip-flop is exemplified, but the present invention is not limited to this, and data of one clock before, such as a latch circuit and a register circuit, is stored or stored. Anything that can be held is acceptable.

[0069]

As is apparent from the above description,
According to the present invention, the following effects can be obtained. According to the first and second aspects of the present invention, the addition result of the external input data and the output of the storage means is sequentially stored in the storage means, and the most significant bit of the output signal of the storage means is taken out, so that an arbitrary amount of data can be obtained. It is possible to generate a clock signal having a cycle ratio.

According to the present invention, the addition result of the first or second value selected based on the magnitude of the output signal of the storage means and the output of the storage means is stored in the storage means. , And extracting the most significant bit of the output signal of the storage means, it is possible to generate a clock signal having an arbitrary frequency division ratio.

According to the invention of claim 6 and claim 7, the value of "n" to be input to the clock signal generation circuit having the division ratio of "k / n" is selected from a plurality of values and supplied. By providing the frequency division ratio selecting means, a clock signal generation circuit having a plurality of frequency division ratios can be configured.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of a clock signal generation circuit according to the present invention.

FIG. 2 is a timing chart for explaining the operation of FIG. 1;

FIG. 3 is a configuration diagram showing another embodiment of the clock signal generation circuit according to the present invention.

FIG. 4 is a timing chart for explaining the operation of FIG. 3;

FIG. 5 is a configuration diagram showing another embodiment of the clock signal generation circuit according to the present invention.

FIG. 6 is a configuration block diagram illustrating an example of a conventional clock signal generation circuit.

FIG. 7 is a timing chart illustrating a situation in which a communication error has occurred.

[Explanation of symbols]

1 frequency divider 2,5 adder 3,6 D-type flip-flop circuit 4,7 data selector circuit 8 clock signal generation circuit 100,100a, 100b, 100c system clock 101 clock signal 102,105,106,107a, 107b, 107
c External input data 103, 103a, 109 Output signal 104, 104a, 104b Clock signal 108 Selection signal

Claims (7)

[Claims] 1. A clock signal generating circuit for generating a clock signal by dividing a system clock, comprising: an adder for adding external input data to a previous addition result; and adding the addition result of the adder to the system clock. A clock signal generating circuit comprising: a memory unit that stores the output in synchronization with the adder as the result of the previous addition, and extracts the most significant bit of the output of the memory unit as the clock signal. 2. When the value of the external input data is "n" and the number of bits of the adder and the storage means is "m", the frequency division ratio is "2 ^m / n". Claim 1.
A clock signal generation circuit as described in the above. 3. A clock signal generating circuit for generating a clock signal by dividing a system clock, comprising: an adder for adding external input data to a previous addition result; and an addition result of the adder being used as the system clock. A storage means for storing and outputting an output to the adder as the result of the previous addition in synchronism, and switching the first and second values based on the magnitude of the output of the storage means and adding the sum as the external input data And a data selector circuit for supplying the highest-order bit of the output of the storage means as the clock signal. 4. When the number of bits of the adder and the storage means is “r”, the first value is “n”, and the second value is “n + 2 ^r −k”, The data selector circuit selects the first value if the output of the storage means is smaller than “2 ^r−1 −n + k / 2”, and selects “2 ^r−1 −n + k /
4. The clock signal generating circuit according to claim 3, wherein the second value is selected when the value is 2 "or more. 5. The number of bits of the adder and the storage means and "r", and the first value "n", the second value when the "n + 2 ^r -k", min 5. The clock signal generation circuit according to claim 4, wherein the circumference ratio is "k / n". 6. A data selector circuit according to claim 1, further comprising a second data selector circuit for selecting one of a plurality of values having different values by a selection signal and supplying the selected value as said first value to said data selector circuit. 3. The clock signal generating circuit according to 3. 7. The frequency division ratio is “k / ni” when the value selected by the second data selector circuit is “ni”.
A clock signal generation circuit as described in the above.