CN213585746U

CN213585746U - Frequency divider circuit

Info

Publication number: CN213585746U
Application number: CN202022525194.0U
Authority: CN
Inventors: 刘凌霄; 王伙荣
Original assignee: Xi'an Ti Pt Sr Electronic Technology Co ltd
Current assignee: Xi'an Ti Pt Sr Electronic Technology Co ltd
Priority date: 2020-11-04
Filing date: 2020-11-04
Publication date: 2021-06-29
Anticipated expiration: 2030-11-04

Abstract

The embodiment of the utility model discloses frequency divider circuit, for example include: the counter circuit comprises a clock signal input end, a counting initial value loading control end and an inversion control signal output end; the two input ends of the output inversion circuit are respectively and electrically connected with the clock signal input end and the inversion control signal output end, and the output inversion circuit also comprises a pre-frequency division clock signal output end, wherein the pre-frequency division clock signal output end is electrically connected with the counting initial value loading control end; and the two input ends of the duty ratio adjusting circuit are respectively and electrically connected with the clock signal input end and the pre-frequency-division clock signal output end, and the duty ratio adjusting circuit also comprises a frequency-division clock signal output end and an odd-even frequency-division control signal input end. The embodiment of the utility model provides a through counter circuit count arouses the design of output clock signal upset, can make under each frequency dividing ratio under the prerequisite of multi-mode frequency division the duty cycle of frequency divider circuit output is 50%.

Description

Frequency divider circuit

Technical Field

The utility model relates to a signal processing technology field especially relates to a frequency divider circuit.

Background

A large number of clock chips, consumer electronics chips, SerDes (Serializer-Deserializer) chips, and display chips are used in electronic products, household appliances, and communication products that are used daily. Because the chips need to cover a plurality of working frequency points in use, the general method is that a high-frequency clock signal is generated through a voltage-controlled oscillator or a phase-locked loop, and the high-frequency clock signal is divided by a frequency divider with a configurable frequency dividing ratio to generate a low-frequency signal required to be used.

The multi-modulus frequency divider has the advantage of continuously available dividing ratio, and the multi-modulus frequency dividers commonly used in the industry at present comprise pulse swallow frequency dividers and asynchronous frequency dividers based on 2/3 frequency division series connection. The pulse swallowing frequency divider is mainly formed by adding two slave counters to one master 2/3 frequency divider, and achieves the effect of multi-mode frequency division by configuring different numbers of 2/3 frequency division ratios; however, the minimum frequency division ratio of the pulse swallow frequency divider is limited, so that frequency division numbers such as frequency division by 2 and frequency division by 3 cannot be output, and output duty ratios at different frequency division ratios are not controllable. The asynchronous frequency divider based on 2/3 frequency division series connection is used for resolving a required frequency division ratio into 3M + 2N (M is 0 or 1, and N is a positive integer), and then the effect of various frequency division ratios is achieved through configuration; however, the duty ratio of the output is 1/N (N is the frequency division number), so that at a large frequency division ratio, the high pulse width of the output of the frequency divider is extremely small, such pulse width may cause unstable operation of the subsequent circuit, and the output duty ratios at different frequency division ratios are also uncontrollable. In short, the output clock duty ratio of the conventional multi-modulus frequency divider is difficult to be 50% at each frequency dividing ratio.

SUMMERY OF THE UTILITY MODEL

Therefore, an embodiment of the present invention provides a frequency divider circuit, which can realize that the duty ratio of the output clock is 50% on the premise that the frequency divider circuit has multi-mode frequency division.

Specifically, the embodiment of the utility model provides a frequency divider circuit, include: the counter circuit comprises a clock signal input end, a counting initial value loading control end and an inversion control signal output end; the two input ends of the output inversion circuit are respectively and electrically connected with the clock signal input end and the inversion control signal output end, and the output inversion circuit also comprises a pre-frequency division clock signal output end, wherein the pre-frequency division clock signal output end is electrically connected with the counting initial value loading control end; and the two input ends of the duty ratio adjusting circuit are respectively and electrically connected with the clock signal input end and the pre-frequency-division clock signal output end, and the duty ratio adjusting circuit also comprises a frequency-division clock signal output end and an odd-even frequency-division control signal input end.

The embodiment of the utility model provides a frequency divider circuit pass through counter circuit count arouses the design combination that output clock signal overturns duty cycle adjusting circuit can make under each frequency dividing ratio under the prerequisite of multi-mode frequency division the duty cycle of frequency divider circuit output is 50%.

In an embodiment of the present invention, a frequency dividing ratio of the frequency-divided clock signal output by the frequency-divided clock signal output terminal to the clock signal input by the clock signal input terminal is an even number 2N or an odd number (2N +1), and N is a positive integer; the counter circuit includes an N/(N +1) down counter.

In an embodiment of the present invention, a frequency dividing ratio of the frequency-divided clock signal output by the frequency-divided clock signal output terminal to the clock signal input by the clock signal input terminal is an even number 2N or an odd number (2N-1), and N is a positive integer; the counter circuit includes an N/(N-1) down counter.

In one embodiment of the invention, the counter circuit comprises an addition counter, or a gray code counter.

In an embodiment of the present invention, the pre-divided clock signal output terminal outputs N low levels of the clock period and (N +1) high levels of the clock period of the clock signal input from the clock signal input terminal in a single cycle when the frequency dividing ratio is an odd number.

In an embodiment of the present invention, the pre-divided clock signal output terminal outputs N high levels of the clock period and (N +1) low levels of the clock period of the clock signal input from the clock signal input terminal in a single cycle when the frequency dividing ratio is an odd number.

In one embodiment of the present invention, the counter circuit further comprises another input terminal electrically connected to the odd-even frequency division control signal input terminal.

In one embodiment of the present invention, the output inversion circuit includes a first not gate, an exclusive nor gate, and a first D flip-flop; the input end of the first not gate is electrically connected with the reverse control signal output end, the two input ends of the exclusive or gate are respectively and electrically connected with the output end of the first not gate and the normal phase output end of the first D trigger, the output end of the exclusive or gate is electrically connected with the data input end of the first D trigger, the clock end of the first D trigger is electrically connected with the clock signal input end, and the normal phase output end of the first D trigger is electrically connected with the pre-divided frequency clock signal output end.

In an embodiment of the present invention, the duty cycle adjusting circuit includes a second D flip-flop, an or gate, a second not gate, a third D flip-flop, and an and gate; the data input end of the second D trigger is electrically connected with the pre-frequency division clock signal output end, the clock end of the second D trigger is electrically connected with the clock signal input end, the two input ends of the OR gate are respectively and electrically connected with the odd-even frequency division control signal input end and the normal phase output end of the second D trigger, the output end of the OR gate is electrically connected with the data input end of the third D trigger, the input end of the second NOT gate is electrically connected with the clock signal input end, the output end of the second NOT gate is electrically connected with the clock end of the third D trigger, the two input ends of the AND gate are respectively and electrically connected with the normal phase output end of the second D trigger and the normal phase output end of the third D trigger, and the output end of the AND gate is electrically connected with the frequency division clock signal output end.

The above technical solution may have one or more of the following advantages: the multi-mode frequency divider can be realized by representing the odd frequency dividing ratio as 2N +1 (or 2N-1) and the even frequency dividing ratio as 2N and matching the counting of the counter circuit to cause the output clock signal to turn over; all odd frequency dividing ratios can realize duty ratio calibration through the same circuit, so that clock output with 50% duty ratio of each frequency dividing ratio is realized on the basis of realizing multi-mode frequency division; furthermore, the output clock is directly clocked out of the input clock, which minimizes the jitter added by the divider circuit.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a frequency divider circuit according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of an internal structure of the output inversion circuit shown in fig. 1.

Fig. 3 is a schematic diagram of input and output waveforms of the output inversion circuit shown in fig. 2 when frequency division is three.

Fig. 4 is a schematic diagram of an internal structure of the duty ratio adjusting circuit shown in fig. 1.

Fig. 5 is a schematic diagram of input and output waveforms of the duty ratio adjusting circuit shown in fig. 4 when frequency division is performed by three.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

[ first embodiment ] A method for manufacturing a semiconductor device

Referring to fig. 1, an embodiment of the present invention provides a frequency divider circuit 10, including: a counter circuit 11, an output inverting circuit 13, and a duty ratio adjusting circuit 15.

The counter circuit 11 includes a clock signal input terminal 11a, a count initial value loading control terminal 11b, and an inversion control signal output terminal 11c, and preferably further includes an input terminal 11d for receiving an odd-even frequency division control signal even _ en. The clock signal input terminal 11a is configured to receive an input of a clock signal clkin, the count initial value loading control terminal 11b is configured to receive a pre-divided clock signal clkopre, and the inversion control signal output terminal 11c is configured to output an inversion control signal TURN.

The two input terminals 13a and 13b of the output inversion circuit 13 are electrically connected to the clock signal input terminal 11a and the inversion control signal output terminal 11c, respectively, to receive the clock signal clkin and the inversion control signal TURN, respectively. In addition, the output inversion circuit 13 further includes a pre-divided clock signal output terminal 13c to output a pre-divided clock signal clkopre, and the pre-divided clock signal output terminal 13c is electrically connected to the count initial value loading control terminal 11 b.

Two input ends 15a and 15b of the duty ratio adjusting circuit 15 are electrically connected to the clock signal input end 11a and the pre-divided clock signal output end 13c, respectively, to receive the clock signal clkin and the output pre-divided clock signal clkopre, respectively. The duty ratio adjusting circuit 15 further includes a divided clock signal output terminal 15c and an odd-even frequency division control signal input terminal 15d, where the divided clock signal output terminal 15c is used for outputting a divided clock signal clkout, and the even-even frequency division control signal input terminal 15d is used for receiving the even-even frequency division control signal even _ en.

In short, the frequency divider circuit 10 of the present embodiment uses the counter circuit 11 to count the input clock signal clkin, when the count value reaches a predetermined value, the counter circuit 11 outputs the inversion control signal TURN to trigger the pre-divided clock signal clkopre output by the output inversion circuit 13 to make level transition, and the duty ratio adjustment circuit 15 outputs the divided clock signal clkout to make level transition accordingly (for example, to make simultaneous transition with the pre-divided clock signal clkopre, or to make later transition than the clock period of the pre-divided clock signal clkpre by half the clock period of the input clock signal clkin), so that the duty ratio of the output divided clock signal clkout can be 50%. As for the duty ratio adjusting circuit 15, it is controlled by the odd-even frequency division control signal even _ en to distinguish between even frequency division and odd frequency division, if even frequency division is performed, the frequency-divided clock signal clkout outputted by the duty ratio adjusting circuit 15 and the pre-frequency-divided clock signal clkopre jump at the same time, if odd frequency division is performed, the frequency-divided clock signal clkout outputted by the duty ratio adjusting circuit 15 jumps after the clock period of the half input clock signal clkin of the pre-frequency-divided clock signal clkopre.

To facilitate a clearer understanding of the frequency divider circuit 10 of the present embodiment, the following description will be made in detail by taking an example in which the counter circuit 11 includes an N/(N +1) down counter, and the frequency dividing ratio of the frequency divider circuit 10 is divided into an odd number and an even number, the even number frequency dividing ratio is represented by 2N, and the odd number frequency dividing ratio is represented by 2N + 1.

For even-numbered division, the pre-divided clock signal clkopre output from the inverting output circuit 13 has a low level of N clock cycles of the clock signal clkin (hereinafter, simply referred to as clock cycles) and a high level of N clock cycles, and thus the duty ratio of the output divided clock signal clkout is 50%.

The even-number frequency division is realized by the following methods:

(i) the duty ratio adjusting circuit 15 adjusts the duty ratio of the output waveform only under odd frequency division, and the input of the output waveform can be considered to be equal to the output under even frequency division;

(ii) at the beginning, the inversion control signal TURN is at low level, the prescaled clock signal clkoprene is at low level, the frequency-divided clock signal clkout is equal to the prescaled clock signal clkoprene and is also at low level, the initial preset number of the N/(N +1) subtraction counter is N, when the rising edge of each input clock clkin comes next, the N/N +1 subtraction counter is operated to subtract 1, the inversion control signal TURN is at low level, the prescaled clock signal clkoprene is at low level, the frequency-divided clock signal clkout is equal to the prescaled clock signal clkoprene and is also at low level;

(iii) until the value of the N/(N +1) down counter is 1, at this time, the inversion control signal TURN changes from low level to high level, the prescaled clock signal clkoprene changes from low level to high level, the divided clock signal clkout is equal to the prescaled clock signal clkoprene and also changes from high level, after the next rising edge of the input clock signal clkin comes, the number of N/(N +1) down counters is N (i.e., the initial value N of the load count), and at the same time, the inversion control signal TURN changes from high level to low level;

(iv) when each rising edge of the input clock signal clkin comes next, the N/(N +1) subtraction counter performs subtraction 1 operation, the inversion control signal TURN is at low level, the prescaled clock signal clkoprene is at high level, and the frequency-divided clock signal clkout is equal to the prescaled clock signal clkoprene and is also at high level;

(v) until the value of the N/(N +1) down counter becomes 1, at this time, the inversion control signal TURN changes from low level to high level, the prescaled clock signal clkopre changes from high level to low level, the divided clock signal clkout equals the prescaled clock signal clkopre and also changes to low level, after the next rising edge of the input clock signal clkin comes, the N/(N +1) down counter is set to N, and at the same time, the inversion control signal TURN changes from high level to low level. (iii) then returning to the state of step (ii), and repeating the steps; this completes the required even division.

For odd-numbered frequency division, the output of the inverting output circuit 13 is a low level of N clock cycles and a high level of N +1 clock cycles, so that the output duty ratio is N/(2N +1), and at this time, the output low level only needs to be increased by 0.5 clock cycles, and the output high level only needs to be decreased by 0.5 clock cycles, so that an odd-numbered frequency division clock signal with a 50% duty ratio can be obtained.

The odd-number frequency division implementation method is as follows:

(a) under odd frequency division, the duty ratio adjusting circuit 15 has a high level width of a pre-divided clock signal clkopre input to the duty ratio adjusting circuit 15 equal to N +1 clock cycles of a clock signal clkin, and a low level of the pre-divided clock signal clkopre is N clock cycles; the duty ratio adjustment circuit 15 subtracts 0.5 clock cycles of the clock signal clkin from the high level and adds to the low level, so that the duty ratio of the output frequency-divided clock signal clkout is 50%.

(b) At the beginning, the inversion control signal TURN is low, the pre-divided clock signal clkopre is low, the divided clock signal clkout is equal to the pre-divided clock signal clkopre and is also low, the initial preset number (i.e. the initial count value) of the N/(N +1) down counter is N, when each rising edge of the next input clock signal clkin comes, the N/(N +1) down counter performs the operation of subtracting 1, the inversion control signal TURN is low, the pre-divided clock signal clkpre is low, and the divided clock signal clkout is equal to the pre-divided clock signal clkopre and is also low.

(c) Until the value of the N/(N +1) down counter is 1, at this time, the inversion control signal TURN changes from low level to high level, the prescaled clock signal clkopre changes from low level to high level, the divided clock signal clkout jumps to high level after half the clock cycle later than the prescaled clock signal clkopre, after the next rising edge of the input clock signal clkin comes, the N/(N +1) down counter is set to N +1 ((i.e., the initial value of load count N +1)), and at the same time, the inversion control signal TURN changes from high level to low level.

(d) When each rising edge of the next input clock signal clkin comes, the N/(N +1) down counter performs a 1 subtraction operation, the inversion control signal TURN signal is at a low level, the pre-divided clock signal clkopre is at a high level, and the divided clock signal clkout is equal to the pre-divided clock signal clkopre and is also at a high level.

(e) Until the value of the N/(N +1) down counter becomes 1, at this time, the inversion control signal TURN changes from low level to high level, the prescaled clock signal clkopre changes from high level to low level, the divided clock signal clkout equals the prescaled clock signal clkopre and also changes to low level, after the next rising edge of the input clock signal clkin comes, the N/(N +1) down counter is set to N, and at the same time, the inversion control signal TURN changes from high level to low level. Then returning to the state of the step (b), and repeating the steps; this completes the required odd frequency division.

As mentioned above, the N/(N +1) down counter in the counter circuit 11 has more implementation methods, and a specific implementation method is not described herein; the working principle is as follows: when each rising edge of the input clock signal clkin comes (i.e., each input clock cycle), the down counter performs a 1-down operation, when the down counter down count is 1, the output inversion control signal TURN jumps to a high level (logic "1"), and then when the next rising edge of the clock signal clkin comes, the down counter reloads to N or N +1 (in this embodiment, only when the odd frequency division and the prescaled clock signal clkoprene are high, the loaded number is N +1, and in the rest cases, the loaded number is N), and at the same time, the inversion control signal TURN jumps to a low level (logic "0"), and the down counter starts to continue the subtraction operation when each rising edge of the input clock signal clkin comes. It should be noted that the counter circuit 11 can selectively load N +1 or N in odd-numbered frequency division and even-numbered frequency division by performing a logic operation on the odd-even frequency division control signal even _ en and the pre-divided clock signal clkopre, but it may also adopt other manners such as configuring two registers to be read alternately in the counter circuit 11, configuring the values in the two registers in even-numbered frequency division as N, and configuring the values in the two registers in odd-numbered frequency division as N and N +1, respectively.

As for the output inverting circuit 13, fig. 2 is a specific implementation of a circuit structure of the output inverting circuit 13, which specifically includes: not gate 131, exclusive nor gate 133, and D flip-flop 135; the input end of the not gate 131 is electrically connected to the inversion control signal output end 11c to receive the inversion control signal TURN, two input ends of the xor gate 133 are electrically connected to the output end of the not gate 131 (the inverted signal TURN b of the inversion control signal TURN) and the non-inverting output end Q of the D flip-flop 135, respectively, the output end of the xor gate 133 is electrically connected to the data input end D of the D flip-flop 135 to provide the signal D, the clock end clk of the D flip-flop 135 is electrically connected to the clock signal input end 11a to receive the clock signal clkin, and the non-inverting output end Q of the D flip-flop 135 is electrically connected to the prescaled clock signal output end 13c to output the prescaled clock signal clkpre. The output inverting circuit 13 of the present embodiment performs the following actions: when each rising edge of the input clock signal clkin comes, if the inversion control signal TURN is at a high level, the pre-divided clock signal clkopre becomes the original reverse level, and if the inversion control signal TURN is at a low level, the pre-divided clock signal clkopre remains unchanged.

Fig. 3 is a schematic diagram of input and output waveforms of the output inverter circuit 13 during three-frequency division. The key idea of the present invention is that the output prescaled clock signal clkoprene is inverted only when the inversion control signal TURN is equal to logic "1", and the inverted control signal TURN is passed through the exclusive nor gate 133, and is inverted to logic "0" if the inversion control signal TURN is logic "1", and the exclusive nor gate 133 corresponds to an inverter, and when the inversion control signal TURN is logic "0", the exclusive nor gate 133 corresponds to a buffer (buffer), so that the inversion operation of the output is completed.

As for the duty ratio adjusting circuit 15, fig. 4 is a specific implementation of a circuit structure of the duty ratio adjusting circuit 15, which specifically includes: d flip-flop 151, or gate 153, not gate 155, D flip-flop 157, and gate 159; a data input end D of the D flip-flop 151 is electrically connected to the prescaled clock signal output end 13c to receive a prescaled clock signal clkoprene, a clock end clk of the D flip-flop 151 is electrically connected to the clock signal input end 11a to receive a clock signal clkin, two input ends of the or gate 153 are electrically connected to the odd-even frequency division control signal input end 15D and the non-inverting output end Q of the D flip-flop 151 to receive an odd-even frequency division control signal even _ en and a clock signal clk1, respectively, an output end of the or gate 153 is electrically connected to the data input end D of the D flip-flop 157 to provide a clock signal clk1i, an input end of the not gate 155 is electrically connected to the clock signal input end 11a to receive an input clock signal clkin, an output end of the not gate 155 is electrically connected to the clock end of the D flip-flop 157, and two input ends of the and gate 159 are electrically connected to the non-inverting output end Q of the D flip-flop 151 and the To receive the clock signals clk1 and clk1h, respectively, and the output terminal of the and gate 159 is electrically connected to the divided clock signal output terminal 15c to output the divided clock signal clkout.

The core idea of the design of the duty cycle adjusting circuit 15 of this embodiment is that when the frequency divider circuit 10 operates in odd frequency division, the odd-even frequency division control signal even _ en is logic "0", the duty cycle adjusting circuit 15 performs the operation of delaying the input pre-divided clock signal clkoprene by 0.5 clock cycles of the input clock signal clkin, and performing an and operation on the delayed signal and the signal clk1, so as to adjust the duty cycle of the input signal clkoprene, and when the even frequency division is performed, the odd-even frequency division control signal even _ en is logic "1", which is equivalent to an and operation between the input signal and a high level, so that the output waveform is equal to the input waveform.

Fig. 5 is a schematic diagram of input and output waveforms of the duty ratio adjusting circuit 15 during three-frequency division. At this time, the odd-even frequency division control signal even _ en is equal to logic "0", and the core idea is to delay the input clock signal clkopre with the duty ratio of 1/3 by half a clock cycle and convert the high level of 0.5 clock cycle to the low level through the or gate 153, so that the output duty ratio is 1.5/3 ═ 50%, and in the even frequency division mode, the even-even frequency division control signal even _ en is equal to logic "1", and the waveform shape of the frequency division clock signal clkout is completely equal to the prescaled clock signal clkopre.

In summary, in the present embodiment, by using the method of representing the odd-numbered division ratio as 2N +1 and the even-numbered division ratio as 2N, the output clock signal is inverted due to the counting of the counter circuit 11, so that the multi-modulus frequency divider can be implemented; all odd frequency dividing ratios can realize duty ratio calibration through the same circuit, so that clock output with 50% duty ratio of each frequency dividing ratio is realized on the basis of realizing multi-mode frequency division; furthermore, the output clock is directly clocked out of the input clock, which minimizes the clock jitter introduced by the divider circuit.

In other embodiments, the aforementioned N/(N +1) down counter may be replaced with an N/(N-1) down counter, in which case the odd frequency division ratio may be represented as 2N 1 and the even frequency division ratio may still be represented as 2N. Alternatively, the N/(N +1) down counter may be replaced with another counter, such as an up counter or a Gray code (Gray code) counter.

Furthermore, in other embodiments, the aforementioned implementation that a single period of the prescaled clock signal comprises N low levels of clock cycles of the clock signal clkin and N +1 high levels of the clock cycles at an odd number of division ratios may be replaced with an implementation that comprises N high levels of the clock cycles and N +1 low levels of the clock cycles.

In addition, it should be understood that the foregoing embodiments are only exemplary illustrations of the present invention, and the technical solutions of the embodiments can be arbitrarily combined and collocated without conflicting technical features and structures and without violating the purpose of the present invention.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention in its corresponding aspects.

Claims

1. A frequency divider circuit, comprising:

the counter circuit comprises a clock signal input end, a counting initial value loading control end and an inversion control signal output end;

the two input ends of the output inversion circuit are respectively and electrically connected with the clock signal input end and the inversion control signal output end, and the output inversion circuit also comprises a pre-frequency division clock signal output end, wherein the pre-frequency division clock signal output end is electrically connected with the counting initial value loading control end; and

and the two input ends of the duty ratio adjusting circuit are respectively and electrically connected with the clock signal input end and the pre-frequency-division clock signal output end, and the duty ratio adjusting circuit also comprises a frequency-division clock signal output end and an odd-even frequency-division control signal input end.

2. The frequency divider circuit according to claim 1, wherein a frequency dividing ratio of the frequency-divided clock signal output from the frequency-divided clock signal output terminal with respect to the clock signal input from the clock signal input terminal is an even number 2N or an odd number (2N +1), and N is a positive integer; the counter circuit includes an N/(N +1) down counter.

3. The frequency divider circuit according to claim 1, wherein a frequency dividing ratio of the frequency-divided clock signal output from the frequency-divided clock signal output terminal with respect to the clock signal input from the clock signal input terminal is an even number 2N or an odd number (2N-1), and N is a positive integer; the counter circuit includes an N/(N-1) down counter.

4. The frequency divider circuit of claim 1, wherein the counter circuit comprises an addition counter, or a gray code counter.

5. The frequency divider circuit according to claim 1, wherein the pre-divided clock signal output terminal outputs a low level of clock cycles of N clock signals input by the clock signal input terminal and a high level of (N +1) clock cycles in a single cycle when a frequency division ratio is an odd number.

6. The frequency divider circuit according to claim 1, wherein the pre-divided clock signal output terminal outputs a high level of clock cycles of N clock signals input by the clock signal input terminal and a low level of (N +1) clock cycles in a single cycle when a frequency division ratio is an odd number.

7. The frequency divider circuit of claim 1, wherein the counter circuit further comprises another input electrically connected to the odd-even division control signal input.

8. The frequency divider circuit of any one of claims 1 to 7, wherein the output inverting circuit comprises a first not gate, an exclusive nor gate, and a first D flip-flop; the input end of the first not gate is electrically connected with the reverse control signal output end, the two input ends of the exclusive or gate are respectively and electrically connected with the output end of the first not gate and the normal phase output end of the first D trigger, the output end of the exclusive or gate is electrically connected with the data input end of the first D trigger, the clock end of the first D trigger is electrically connected with the clock signal input end, and the normal phase output end of the first D trigger is electrically connected with the pre-divided frequency clock signal output end.

9. The frequency divider circuit of any of claims 1 to 7, wherein the duty cycle adjustment circuit comprises a second D flip-flop, an OR gate, a second NOT gate, a third D flip-flop, and an AND gate; the data input end of the second D trigger is electrically connected with the pre-frequency division clock signal output end, the clock end of the second D trigger is electrically connected with the clock signal input end, the two input ends of the OR gate are respectively and electrically connected with the odd-even frequency division control signal input end and the normal phase output end of the second D trigger, the output end of the OR gate is electrically connected with the data input end of the third D trigger, the input end of the second NOT gate is electrically connected with the clock signal input end, the output end of the second NOT gate is electrically connected with the clock end of the third D trigger, the two input ends of the AND gate are respectively and electrically connected with the normal phase output end of the second D trigger and the normal phase output end of the third D trigger, and the output end of the AND gate is electrically connected with the frequency division clock signal output end.

10. The frequency divider circuit of claim 8, wherein the duty cycle adjustment circuit comprises a second D flip-flop, an OR gate, a second NOT gate, a third D flip-flop, and an AND gate; the data input end of the second D trigger is electrically connected with the pre-frequency division clock signal output end, the clock end of the second D trigger is electrically connected with the clock signal input end, the two input ends of the OR gate are respectively and electrically connected with the odd-even frequency division control signal input end and the normal phase output end of the second D trigger, the output end of the OR gate is electrically connected with the data input end of the third D trigger, the input end of the second NOT gate is electrically connected with the clock signal input end, the output end of the second NOT gate is electrically connected with the clock end of the third D trigger, the two input ends of the AND gate are respectively and electrically connected with the normal phase output end of the second D trigger and the normal phase output end of the third D trigger, and the output end of the AND gate is electrically connected with the frequency division clock signal output end.