JP6812780B2 - Reciprocal count value generation circuit and physical quantity sensor - Google Patents

Description

The present invention relates to a reciprocal count value generation circuit and a physical quantity sensor.

A frequency counter that generates a signal corresponding to the ratio of the frequency of the reference signal (reference clock) to the frequency of the signal to be measured is known (see, for example, Patent Document 1). The apparatus described in Patent Document 1 includes a plurality of frequency delta sigma modulators (hereinafter, referred to as “FDSM (Frequency Delta Sigma Modulator)”) electrically connected in parallel.

When each of the direct counting method and the reciprocal counting method is to be realized in the frequency counter, in the direct counting method, the reference signal among the reference signal and the measured signal is used as the operation clock. Further, in the reciprocal counting method, contrary to the above, the signal to be measured is used as the operation clock. In addition, the frequency of the reference signal is compared with the frequency of the signal to be measured, and if the frequency of the reference signal is lower, the direct counting method is adopted, and if the frequency of the signal to be measured is lower, the reciprocal counting method is adopted. It is considered that the measurement can be performed with higher resolution by adopting. Therefore, it is common to adopt a method in which the signal to be measured and the reference signal, whichever has the lower frequency, is used as the operating clock.

JP-A-2015-220552

Here, assuming that the frequency of the signal to be measured is lower than the frequency of the reference signal, the reciprocal counting method is adopted, and a plurality of FDSMs electrically connected in parallel are adopted as the counters of the frequency counters. To consider.

First, the phase relationships of the signal to be measured and the reference signal are different from each other, and there are various methods for realizing the different phase relationships in a plurality of FDSMs electrically connected in parallel. From the viewpoint of power consumption, when a configuration in which a plurality of measured signals input to a plurality of FDSMs are sequentially delayed by a delay element is adopted, the signal is delayed by the delay element as compared with the case where a configuration in which the reference signal is delayed is adopted. It is preferable because the number of times is reduced.

However, in the reciprocal counting method, since the signal to be measured is used as an operation clock, there is a problem that the clock skew becomes large when the configuration for delaying the signal to be measured is adopted.

An object of the present invention is to provide a reciprocal count value generation circuit and a physical quantity sensor that can reduce power consumption with high accuracy.

The present invention has been made to solve at least a part of the above-mentioned problems, and can be realized as the following forms or application examples.

The reciprocal count value generation circuit of the present invention is a reciprocal count value generation circuit that counts a reference clock at a timing specified by a signal to be measured.
A plurality of firsts, which are electrically connected in parallel and each of a plurality of measured signals having different phases are input, and the reference clock is used to detect an inverted edge representing an inversion of the level of the plurality of measured signals. Counter and
A second counter that counts the reference clock and
The product of the number of detected reciprocals of the measured signal at the timing specified by the reference clock and the count value of the second counter at the timing is integrated in the section specified by the measured signal. It is characterized by including a reciprocal count value generation unit that generates a reciprocal count value.

In the present invention, since the phases of the plurality of measured signals are different from each other, the power consumption can be reduced as compared with the case where the phases of the plurality of reference clocks are different from each other.

Further, by inputting the signals to be measured having different phases to each of the first counters, the quantization noise caused by the idle tone can be suppressed, and thus the accuracy can be improved.

In addition, it can be counted without omission without a dead period, a primary noise shaping effect can be obtained, and noise can be effectively shifted to the high frequency side. As a result, for example, by providing a low-pass filter on the output side, the noise component can be reduced and the accuracy can be improved. Further, for example, when a moving average filter is provided on the output side, the configuration of the moving average filter and the moving average filter processing can be simplified.

In the reciprocal count value generation circuit of the present invention, the first counter detects the inverting edge by using the rising edge and the falling edge of the reference clock.
It is preferable that the second counter counts the reference clock by using the rising edge and the falling edge of the reference clock.

As a result, the frequency is effectively doubled, and the SN ratio can be improved.

The reciprocal count value generation circuit of the present invention includes a detection circuit that detects the rise and fall of the reference clock and generates a pulse signal synchronized with the rise and fall of the reference clock.
The first counter detects the inverted edge by using the pulse signal.
The second counter preferably uses the pulse signal to count the reference clock.

As a result, the frequency is effectively doubled with a simple configuration, and the SN ratio can be improved.

The reciprocal count value generation circuit of the present invention includes a detection circuit that detects the rise and fall of the reference clock and generates a pulse signal synchronized with the rise and fall of the reference clock.
The second counter includes a first counting unit that counts the rising edge of the reference clock and a second counting section that counts the falling edge of the reference clock.
The first counter detects the inverted edge by using the pulse signal.
According to claim 1, the second counter counts the rise of the reference clock by the first counting unit and counts the fall of the reference clock by the second counting unit in counting the reference clock. The reciprocal count value generation circuit described.

As a result, the frequency is effectively doubled with a simple configuration, and the SN ratio can be improved.

In the reciprocal count value generation circuit of the present invention, the number of detected inverted edges of the signal to be measured is preferably the number of rising or falling edges of the signal to be measured.
As a result, the circuit configuration can be simplified.

In the reciprocal count value generation circuit of the present invention, the number of detected inverted edges of the signal to be measured is preferably the total value of the number of rising and falling edges of the signal to be measured.

As a result, the effective input frequency of the signal to be measured is doubled, so that the SN ratio can be improved by the oversampling effect.

The physical quantity sensor of the present invention includes a detection unit that detects a physical quantity related to vibration and
It is characterized by including a reciprocal count value generation circuit of the present invention in which a signal to be measured output from the detection unit is input.

In the present invention, since the phases of the plurality of measured signals are different from each other, the power consumption can be reduced as compared with the case where the phases of the plurality of reference clocks are different from each other.

Further, by inputting the signals to be measured having different phases to each of the first counters, the quantization noise caused by the idle tone can be suppressed, and thus the accuracy can be improved.

In addition, it can be counted without omission without a dead period, a primary noise shaping effect can be obtained, and noise can be effectively shifted to the high frequency side. As a result, for example, by providing a low-pass filter on the output side, the noise component can be reduced and the accuracy can be improved. Further, for example, when a moving average filter is provided on the output side, the configuration of the moving average filter and the moving average filter processing can be simplified.

In the physical quantity sensor of the present invention, the physical quantity is preferably a physical quantity related to vibration.
As a result, the physical quantity related to vibration can be detected with high accuracy.

It is a block diagram which shows 1st Embodiment of the reciprocal count value generation circuit of this invention. It is a block diagram which shows the 2nd Embodiment of the reciprocal count value generation circuit of this invention. It is a timing chart for demonstrating the operation of the reciprocal count value generation circuit shown in FIG. It is a block diagram which shows the 3rd Embodiment of the reciprocal count value generation circuit of this invention. It is a block diagram which shows the 4th Embodiment of the reciprocal count value generation circuit of this invention. It is a block diagram which shows the 5th Embodiment of the reciprocal count value generation circuit of this invention. It is a figure which shows the internal structure of the detection part in embodiment of the acceleration sensor which is an example of the physical quantity sensor of this invention. It is sectional drawing which is taken along the line AA in FIG.

Hereinafter, the reciprocal count value generation circuit and the physical quantity sensor of the present invention will be described in detail based on the embodiments shown in the accompanying drawings.

<First Embodiment>
FIG. 1 is a block diagram showing a first embodiment of the reciprocal count value generation circuit of the present invention.

In the drawings, the signal to be measured is described as "Fx" and the reference clock (reference signal) is described as "Fs" (the same applies to the drawings of other embodiments).

Further, in the following description, signals having different phases of the measured signals are also referred to as “measured signals”.
Further, the case where the signal level is "Low" is also referred to as "0", and the case where the signal level is "High" is also referred to as "1".

Further, the signal inversion represents only the rising edge of the signal, that is, the case where the signal changes from "0" to "1", and the falling edge of the signal, that is, the signal changes from "1" to "0". There are cases where only the case is represented and cases where the signal rises and falls, that is, both when the signal changes from "0" to "1" and when the signal changes from "1" to "0". included.

Further, the inverting edge of the signal is a portion representing the inverting of the signal level, and as described above, the inverting edge of the signal may represent only the rising edge of the signal or only the falling edge of the signal. , The case where it represents both the rising edge and the falling edge (both edges) of the signal is included.

However, in the following description, each of the reference clock (reference signal) and the signal to be measured will be described by taking one of the above as an example. In the present embodiment, for the reference clock, the signal inversion is the rising edge of the signal, and for the signal under test, the signal inversion is both the rising edge and the falling edge of the signal.

The reciprocal count value generation circuit 1 (reciprocal count value generator) shown in FIG. 1 has a value (or the above) corresponding to the ratio of the frequency of the reference clock (reference signal) Fs whose frequency is known to the frequency of the signal to be measured Fx. It is a circuit (device) that generates a reciprocal count value (a signal indicating a reciprocal count value) which is a value (value used for generating a value). The reciprocal count value generation circuit 1 employs a reciprocal count method, uses a signal to be measured as an operating clock, and the frequency of the signal to be measured is lower than the frequency of the reference clock.

First, the outline of the reciprocal count value generation circuit 1 will be briefly described in correspondence with the scope of claims, and then will be described in detail.

The reciprocal count value generation circuit 1 is a circuit (reciprocal count value generation circuit) that counts a reference clock (Fs) at a timing defined by a signal to be measured (Fx). The reciprocal count value generation circuit 1 is electrically connected in parallel, a plurality of measured signals (Fx) having different phases are input to each, and a plurality of measured signals (Fx) are input using a reference clock (Fs). A plurality of counters 3 which are an example of a plurality of first counters for detecting an inverted edge representing the inversion of the level of, a counter 5 which is an example of a second counter for counting the reference clock (Fs), and a reference. The product of the number of detected inverted edges of the measured signal (Fx) at the timing specified by the clock (Fs) and the count value of the counter 5 at the timing is integrated in the section specified by the measured signal (Fx). It also includes a reciprocal count value generation unit 10 that generates a reciprocal count value. Hereinafter, "electrically connected" is also simply referred to as "connected".

Further, the reciprocal count value generation unit 10 includes not only the case where the product is integrated, but also a configuration capable of obtaining the same result as the case where the product is integrated.

According to the reciprocal count value generation circuit 1, since the phases of the plurality of signals to be measured are different, the power consumption can be reduced as compared with the case where the phases of the plurality of reference clocks having high frequencies are different. Further, by inputting the signals to be measured having different phases to each counter 3, the quantization noise caused by the idle tone can be suppressed, and thus the accuracy can be improved.

In addition, it can be counted without omission without a dead period, a primary noise shaping effect can be obtained, and noise can be effectively shifted to the high frequency side. As a result, for example, by providing a low-pass filter on the output side, the noise component can be reduced and the accuracy can be improved. Further, for example, when a moving average filter is provided on the output side, the configuration of the moving average filter and the moving average filter processing can be simplified.

Further, the number of detected inverted edges of the measured signal (Fx) at each counter is the total value of the number of rising and falling edges of the signal in the plurality of measured signals (Fx). As a result, the effective input frequency of the signal to be measured is doubled, so that the SN ratio can be improved by the oversampling effect.

Further, the number of detected inverted edges of the measured signal (Fx) at each counter is not limited to the total value, and may be the number of rising or falling edges of the signal in a plurality of measured signals (Fx). As a result, the circuit configuration can be simplified. Hereinafter, a specific description will be given.

The reciprocal count value generation circuit 1 includes at least one delay element 2, a plurality of counters 3 which are examples of a plurality of first counters, an adder 4, and a counter 5 which is an example of a second counter. , A multiplier 6, an integrator 7, and a difference calculator 8 are provided. Each counter 3 is electrically connected in parallel. Further, the number of delay elements 2 is one less than the number of counters 3. In the present embodiment, the number of counters 3 is n (n is an integer of 2 or more), and the number of delay elements 2 is n-1. The upper limit of n is not particularly limited, but may be, for example, about 1000.

Further, each counter 3, an adder 4, a multiplier 6, an integrator 7, and a differential calculator 8 are connected in this order from the input side to the output side.

In the present embodiment, the counter 3 is composed of a frequency delta sigma modulator (hereinafter, referred to as “FDSM (Frequency Delta Sigma Modulator)”).

That is, the counter 3 is synchronized with the rising edge of the reference clock (reference signal) Fs and the latch 31 (first latch) that latches the signal to be measured Fx and outputs the first data. Then, the latch 32 (second latch) that latches the first data and outputs the second data, and the exclusive logical sum of the first data and the second data are calculated to generate the output data. It includes a logic sum circuit 33. As the latch 31 and the latch 32, for example, a D latch or the like can be used, respectively, and the latch 31 and the latch 32 are composed of, for example, a D flip-flop circuit or the like.

The delay element 2 has a function of delaying the signal to be measured, and is connected between the two counters 3 on the input side of two adjacent counters 3. Therefore, the signal to be measured is input to the input terminal of the latch 31 of the predetermined counter 3, and the signal to be measured is delayed by the delay element 2 and input to the input terminal of the latch 31 of another counter 3. Similarly, the signal to be measured is further delayed by the delay element 2 and input to the input terminal of the latch 31 of another counter 3. Further, as the delay element 2, an inverter is used in this embodiment.

A reference clock is input to the input terminal of the counter 5, and the output terminal of the counter 5 is connected to one input terminal of the multiplier 6. Further, as the counter 5, for example, a free run counter or the like can be used. Further, the output terminal of the adder 4 is connected to the other input terminal of the multiplier 6.

Further, the integrator 7 includes an adder 71 and a latch 72 electrically connected to the output side of the adder 71. As the latch 72, for example, a D latch or the like can be used.

Further, the difference calculator 8 includes a latch 81 and a subtractor 82. The output terminal of the latch 81 is connected to the negative input terminal of the subtractor 82. As the latch 81, for example, a D latch or the like can be used.

Further, the output terminal of the latch 72 of the integrator 7 is connected to the positive input terminal of the subtractor 82 of the integrator 8 and the input terminal of the latch 81, and to one of the input terminals of the adder 71, respectively. ing. Further, the output terminal of the multiplier 6 is connected to the other input terminal of the adder 71.

The adder 4, the multiplier 6, the integrator 7, and the difference calculator 8 constitute the main part of the reciprocal count value generation unit 10.

Further, the signal to be measured is the input terminal of the latch 31 of the predetermined counter 3 among the plurality of counters 3, the input terminal of the first-stage delay element 2 among the plurality of delay elements 2, and the adder of the adder 7. It is input to the reset terminal of 71, the clock input terminal of the latch 81 of the difference calculator 8 and the clock input terminal of the subtractor 82, respectively.

Further, the reference clock is input to the clock input terminal of the latch 31 of each counter 3, the clock input terminal of the latch 32, the input terminal of the counter 5, and the clock input terminal of the latch 72 of the integrator 7, respectively. There is.

Next, the operation of the reciprocal count value generation circuit 1 will be described.
In the drawings, the signal to be measured is described as "Fx" and the reference clock is described as "Fs".

As shown in FIG. 1, the signal to be measured is integrated with the input terminal of the latch 31 of the predetermined counter 3 among the plurality of counters 3 and the input terminal of the first-stage delay element 2 among the plurality of delay elements 2. Inputs are made to the reset terminal of the adder 71 of the integrator 7, the clock input terminal of the latch 81 of the difference calculator 8, and the clock input terminal of the subtractor 82, respectively.

Further, the reference clock is input to the clock input terminal of the latch 31 of each counter 3, the clock input terminal of the latch 32, the input terminal of the counter 5, and the clock input terminal of the latch 72 of the integrator 7, respectively. ..

Further, the signal to be measured is delayed by the delay element 2 and input to the input terminal of the latch 31 of another counter 3. As a result, signals to be measured having the same frequency but different phases are input to the input terminals of the latch 31 of each counter 3.

At each counter 3, the latch 31 latches the signal to be measured in synchronization with the rising edge of the reference clock and outputs the first data, and the latch 32 synchronizes with the rising edge of the reference clock and outputs the first data. The data is latched and the second data is output, and the exclusive logical sum circuit 33 calculates the exclusive logical sum of the first data and the second data to generate and output the output data. That is, the exclusive OR circuit 33 outputs "0" if the number of inversions of the measured signal during one cycle of the reference clock is even, and "1" if it is odd. As a result, each counter 3 outputs "1" corresponding to the rising and falling edges of the signal to be measured, and outputs "0" for the others.

The signals output from each counter 3 are input to the adder 4, respectively. The adder 4 adds and outputs the numerical value indicated by the signal output from each counter 3.

Further, the counter 5 counts the reference clock and outputs the count value of the reference clock.

Next, the multiplier 6 multiplies the numerical value output from the adder 4 and the count value output from the counter 5, and outputs the multiplied value.

Next, in the integrator 7, the adder 71 adds and outputs the current multiplication value and the previous multiplication value latched by the latch 72. This output is the sum of the integrated reciprocal count values.

Next, in the difference calculator 8, the subtractor 82 subtracts the value indicated by the previous signal latched by the latch 81 from the value indicated by the signal output from the current integrator 7, and outputs the value. .. This output is the sum of the reciprocal count values. Dividing the sum of the reciprocal count values by the number of counters 3 gives the reciprocal count values corresponding to one counter 3.

Here, the reciprocal count value in the present embodiment is a value corresponding to the output of one of the plurality of counters 3, and is a rising edge of the reference clock included between the rising edge and the falling edge of the signal to be measured. Is the number of.

The sum of the reciprocal count values is the sum of the reciprocal count values obtained from the outputs of all the counters 3.

Further, the reciprocal count value in the present invention is not limited to the reciprocal count value in the narrow sense in the present invention, and includes the sum of the reciprocal count values, the integrated reciprocal count value, the total sum of the integrated reciprocal count values, and the like.

Although detailed description of the subsequent operations will be omitted, for example, a low-pass filter (filter) (not shown) is provided on the output side of the differential calculator 8 and the signal output from the differential calculator 8 by the low-pass filter. Is processed. As a result, the low-pass filter cuts off or reduces frequency components above a predetermined cutoff frequency. Further, for example, a moving average filter or the like may be provided.

As described above, according to the reciprocal count value generation circuit 1, since the phases of the plurality of measured signals are different from each other, the power consumption is reduced as compared with the case where the phases of the plurality of reference clocks having high frequencies are different from each other. be able to.

Further, by inputting the measured signals having different phases to each counter 3, the quantization noise caused by the idle tone can be suppressed. Thereby, the accuracy can be improved.

In addition, it can be counted without omission without a dead period, a primary noise shaping effect can be obtained, and noise can be effectively shifted to the high frequency side. As a result, for example, by providing a low-pass filter on the output side, the noise component can be reduced and the accuracy can be improved. Further, for example, when a moving average filter is provided on the output side, the configuration of the moving average filter and the moving average filter processing can be simplified.

Further, a modified example will be described below.
(1) The counter 3 and the counter 5 are not limited to the above-mentioned configurations, and counters having other configurations can be used. Examples of other counters include ripple counters and the like.

(2) The frequency of the signal to be measured may be higher than the frequency of the reference clock.
(3) For the circuit in the stage (output side) after the difference calculator 8 (edge detection number calculation circuit), a reference clock may be used as the operation clock, or a signal to be measured may be used.

(3-1) A reference clock is used as the operation clock for the circuit after the difference calculator 8 (edge detection number calculation circuit).

As a result, when the frequency of the reference clock is higher than the frequency of the signal to be measured, the calculation can be appropriately completed in time while distributing the processing.

(3-2) The signal to be measured is used as the operation clock for the circuit after the difference calculator 8 (edge detection number calculation circuit).

As a result, when the frequency of the reference clock is lower than the frequency of the signal to be measured, the power consumption can be reduced by the pipeline processing with the low frequency clock.

<Second Embodiment>
FIG. 2 is a block diagram showing a second embodiment of the reciprocal count value generation circuit of the present invention. FIG. 3 is a timing chart for explaining the operation of the reciprocal count value generation circuit shown in FIG. In FIG. 2, the bus in the circuit is shown by a thick line (the same applies to other figures).

In the drawings, subscripts (0, 1, ..., 31) are added to "Fx" in order to distinguish the signals to be measured having different phases (the same applies to the drawings of other embodiments).

Further, in the drawings, the signal output from each latch 31 is described as "S", and subscripts (0, 1, ..., 31) are added to distinguish each signal (other implementations). The same applies to the drawing of the form).

Hereinafter, the second embodiment will be described mainly on the differences from the above-described embodiment, and the description of the same matters will be omitted.

In the second embodiment, the signal inversion is both the rising edge and the falling edge of the signal for each of the reference clock and the signal to be measured.

That is, in the second embodiment, the counter 3 (first counter) detects the inverted edge by using the rising edge and the falling edge of the reference clock (Fs), and the counter 11 (second counter) , The reference clock (Fs) is counted by using the rising edge and the falling edge of the reference clock (Fs).

As a result, the frequency is effectively doubled, and the SN ratio can be improved. Hereinafter, a specific description will be given.

More specifically, the reciprocal count value generation circuit 1 of the second embodiment detects the rise and fall of the reference clock (Fs) and synchronizes with the rise and fall of the reference clock (Fs). The edge detection unit 9 is provided as an example of the detection circuit for generating the above. Then, the counter 3 (first counter) detects the inverted edge by using the pulse signal (P) generated by the edge detection unit 9, and the counter 11 (second counter) detects the inverted edge, and the counter 11 (second counter) detects the edge detection unit 9. The reference clock (Fs) is counted using the pulse signal (P) generated in.

As a result, the frequency can be effectively doubled with a simple configuration, and the SN ratio can be improved. Hereinafter, a specific description will be given.

As shown in FIG. 2, the reciprocal count value generation circuit 1 of the second embodiment includes an edge detection unit 9, a counter 11 which is an example of a second counter, at least one delay element 12, and a plurality of second counters. A plurality of counters 3 which are an example of one counter, a plurality of latches 13, a plurality of latches 14, and an adder 4 are provided. Each counter 3 is electrically connected in parallel. Further, the number of delay elements 12 is one less than the number of counters 3. In the present embodiment, the number of counters 3 is 32 and the number of delay elements 12 is 31. The number of latches 13 and 14 is 32, which is equal to the number of counters 3, respectively.

Further, the edge detection unit 9, the counter 11, each latch 14, and the adder 4 are connected in this order from the input side to the output side.

Further, the edge detection unit 9 includes a delay element 91 and an exclusive OR circuit 92. The output terminal of the delay element 91 is connected to one input terminal of the exclusive OR circuit 92. Further, as the delay element 91, a buffer is used in this embodiment.

The output terminal of the edge detection unit 9 is connected to the input terminal of the counter 11, and the output terminal of the counter 11 is connected to the input terminal of each latch 14. The output terminal of the latch 14 is connected to the input terminal of the adder 4. Further, as the counter 11, for example, an up counter or the like can be used.

Further, the output terminal of the edge detection unit 9 is connected to the clock input terminal of the latch 31 of each counter 3, the clock input terminal of the latch 32, and the clock input terminal of each latch 13. Further, the output terminal of each latch 13 is connected to the clock input terminal of each latch 14.

Further, the output terminal of each counter 3 is connected to the input terminal of the latch 13 corresponding to the counter 3. Further, the output terminal of each latch 13 is connected to the clock input terminal of the latch 14 corresponding to the latch 13. Further, as the latch 13 and the latch 14, for example, a D latch or the like can be used, respectively.

The delay element 12 has a function of delaying the signal to be measured, and is connected between the two counters 3 on the input side of two adjacent counters 3. Therefore, the signal to be measured is input to the latch 31 of a predetermined counter 3, and the signal to be measured is delayed by the delay element 12 and input to the latch 31 of another counter 3, and so on. The signal is further delayed by the delay element 12 and input to the latch 31 of another counter 3. Further, as the delay element 12, a buffer is used in this embodiment.

Further, the signal to be measured is input to the input terminal of the latch 31 of the predetermined counter 3 among the plurality of counters 3 and the input terminal of the first-stage delay element 12 among the plurality of delay elements 12, respectively. There is.

Further, the reference clock is applied to the input terminal of the delay element 91 connected to one input terminal of the exclusive OR circuit 92 of the edge detection unit 9 and to the other input terminal of the exclusive OR circuit 92, respectively. , Has been entered.

Next, the operation of the reciprocal count value generation circuit 1 will be described.
As shown in FIG. 2, the signal to be measured is sent to the input terminal of the latch 31 of the predetermined counter 3 among the plurality of counters 3 and the input terminal of the first-stage delay element 12 among the plurality of delay elements 12. Each is entered.

Further, the reference clock is applied to the input terminal of the delay element 91 connected to one input terminal of the exclusive OR circuit 92 of the edge detection unit 9 and the other input terminal of the exclusive OR circuit 92, respectively. , Is entered.

Further, the signal to be measured is delayed by the delay element 2 and input to the input terminal of the latch 31 of another counter 3. As a result, signals to be measured having the same frequency but different phases are input to the input terminals of the latch 31 of each counter 3 (see FIG. 3).

The edge detection unit 9 detects the rising edge and the falling edge of the reference clock (Fs). That is, the edge detection unit 9 outputs a pulse signal (P) having a pulse synchronized with the rising edge of the reference clock (Fs) and a pulse synchronized with the falling edge of the reference clock (Fs).

Further, the pulse signal (P) output from the edge detection unit 9 is input to the counter 11, and the counter 11 counts the pulse of the pulse signal (P) output from the edge detection unit 9 and counts the pulse. Output the value.

Further, the pulse signal (P) is input to the clock input terminal of the latch 31 of each counter 3, the clock input terminal of the latch 32, and the clock input terminal of the latch 13, respectively.

Further, in each counter 3, the latch 31 latches the measured signal (Fx0 to Fx31) in synchronization with the rising edge of the reference clock (the rising edge of the pulse of the pulse signal output from the edge detection unit 9). The first data is output, the latch 32 latches the first data in synchronization with the rising edge of the reference clock and outputs the second data, and the exclusive logical sum circuit 33 performs the first data and the above. The exclusive logical sum of the second data is calculated to generate the output data, and the output data is output. Further, at each counter 3, the latch 31 latches the signal to be measured in synchronization with the falling edge of the reference clock and outputs the first data, and the latch 32 synchronizes with the falling edge of the reference clock. The first data is latched and the second data is output, and the exclusive logical sum circuit 33 calculates the exclusive logical sum of the first data and the second data to generate and output the output data. .. That is, from each counter 3, "1" is output corresponding to the rise and fall of the signal to be measured, and "0" is output for the others.

Further, the signals output from each counter 3 are latched and output by the latch 13 in synchronization with the rising edge and the falling edge of the reference clock, respectively.

Further, the count value output from the counter 11 is input to each latch 14. Each latch 14 latches and outputs the count value in synchronization with the rising edge of the signal output from the latch 13.

In the example shown in FIG. 3, the count value output from the latch 14 of the predetermined counter 3 among the counters 3 is "6" at the rising edge and "34" at the falling edge of the signal to be measured. That is, focusing only on this counter 3, the integrated reciprocal count values are "6" and "34", and the reciprocal count value is 28 (= 34-6).

The count value output from the latch 14 of the other counter 3 is "7" at the rising edge of the signal to be measured and "34" at the falling edge. That is, focusing only on this counter 3, the integrated reciprocal count values are "7" and "34", and the reciprocal count value is 27 (= 34-7).

The count value output from the latch 14 of the other counter 3 is "7" at the rising edge of the signal to be measured and "35" at the falling edge. That is, focusing only on the counter 3, the integrated reciprocal count values are "7" and "35", and the reciprocal count value is 28 (= 35-7).

The count value output from the latch 14 of the other counter 3 is "10" at the rising edge of the signal to be measured and "37" at the falling edge. That is, focusing only on the counter 3, the integrated reciprocal count values are "10" and "37", and the reciprocal count value is 27 (= 37-10).

Next, the adder 4 adds and outputs the count values output from each latch 14. This output is the sum of the integrated reciprocal count values.

Here, the reciprocal count value in the present embodiment is a value corresponding to the output of one of the plurality of counters 3, and is a rising edge of the reference clock included between the rising edge and the falling edge of the signal to be measured. And the number of falling edges.

The sum of the reciprocal count values is the sum of the reciprocal count values obtained from the outputs of all the counters 3.

Although detailed description of the subsequent operations will be omitted, for example, the difference between the total sum of the current integrated reciprocal count values and the total sum of the previous integrated reciprocal count values is obtained and output. This output is the sum of the reciprocal count values. The method for obtaining the sum of the reciprocal count values is not limited to this method, and other methods may be used. Further, as described in the first embodiment, for example, a filter such as a low-pass filter or a moving average filter may be provided.

The second embodiment as described above can also exert the same effect as the above-described embodiment.

Further, in the second embodiment, not only the signal to be measured but also the reference clock is defined as both the rising edge and the falling edge of the signal, so that the accuracy can be further improved.

<Third Embodiment>
FIG. 4 is a block diagram showing a third embodiment of the reciprocal count value generation circuit of the present invention.

Hereinafter, the third embodiment will be described mainly on the differences from the above-described embodiment, and the description of the same items will be omitted.

In the third embodiment, the signal inversion is both the rising edge and the falling edge of the signal for each of the reference clock and the signal to be measured.

As shown in FIG. 4, the reciprocal count value generation circuit 1 of the third embodiment includes an edge detection unit 9, a counter 11 which is an example of a second counter, a latch 18, and at least one delay element (FIG. 4). (Not shown), a counter 30 (one shown), a plurality of latches 17 (one shown), a counting unit 19, a multiplier 25, and a counter 20 which are examples of a plurality of first counters. A latch 24, a latch 26, and an adder 27 are provided.

In the present embodiment, the counter 30 is the same as the counter 3 for 32 counters in the second embodiment, and one counter 30 indicates the counter 3 for 32 counters (the function of the counter 3 for 32 counters is provided). doing). That is, the counter 30 includes 32 latches (not shown) corresponding to the 32 latches 31 of the second embodiment, 32 latches 32 (only one is shown in the figure), and the second embodiment. It includes 32 exclusive OR circuits 330 (only one is shown in the figure) corresponding to the 32 exclusive OR circuits 33 of the embodiment. Similarly, the latch 17 is the same as the 32 latches 14 of the second embodiment, and one latch 14 indicates 32 latches 14 (having the function of 32 latches 14). There is). Therefore, the description of the counter 30 and the latch 17 will be omitted.

Further, the counter 30, the latch 17, the counting unit 19, the multiplier 25, and the adder 27 are connected in this order from the input side to the output side. Further, the counting unit 19 has a function of counting "1" bits.

Further, the edge detection unit 9, the counter 11, the latch 18, and the multiplier 25 are connected in this order from the input side to the output side.

Further, the counter 20 and the latch 24 are connected in this order from the input side to the output side.

Although not shown, a plurality of delay elements (31 in this embodiment) are connected to the input side of the counter 30 as in the second embodiment.

Further, the counter 20 includes a latch 21, a latch 22, and an exclusive OR circuit 23, and is configured in the same manner as the counter 3 of the first embodiment and the second embodiment. Then, the signal to be measured is input to the input terminal of the latch 21 of the counter 20.

Further, as the latch 17, the latch 18, the latch 21, the latch 22 and the latch 26, for example, a D latch or the like can be used.

Further, the output terminals of the edge detection unit 9 include a clock input terminal of each latch (not shown) corresponding to each latch 31 of the second embodiment of the counter 30, a clock input terminal of each latch 32, and an input terminal of the counter 11. The clock input terminal of the latch 18, the clock input terminal of the latch 26, the clock input terminal of each latch 17, the clock input terminal of the latch 21 of the counter 20, the clock input terminal of the latch 22, and the clock input terminal of the latch 24. Are connected to each other.

Further, the output terminal of the counter 11 is connected to the input terminal of the latch 18. Further, the output terminal of the latch 18 is connected to one input terminal of the multiplier 25. Further, the output terminal of the counting unit 19 is connected to the other input terminal of the multiplier 25.

Further, the output terminal of the multiplier 25 is connected to one input terminal of the adder 27. Further, the output terminal of the adder 27 is connected to the input terminal of the latch 26, and the output terminal of the latch 26 is connected to the other input terminal of the adder 27. Further, the output terminal of the latch 24 is connected to the reset terminal of the adder 27.

Further, the reference clock is applied to the input terminal of the delay element 91 connected to one input terminal of the exclusive OR circuit 92 of the edge detection unit 9 and to the other input terminal of the exclusive OR circuit 92, respectively. , Has been entered.

Next, the operation of the reciprocal count value generation circuit 1 will be described.
As shown in FIG. 4, the same as in the second embodiment is performed up to the middle, and “1” is output from the exclusive OR circuit 330 of the counter 30 corresponding to the rising and falling edges of the signal to be measured. And "0" is output for others.

Further, the pulse signals output from the edge detection unit 9 and having a pulse synchronized with the rising edge of the reference clock and a pulse synchronized with the falling edge of the reference clock are the counter 11, the clock input terminal of the latch 18, and the latch 26. Is input to the clock input terminal of the latch 17, the clock input terminal of the latch 17, the clock input terminal of the latch 21 of the counter 20, the clock input terminal of the latch 22, and the clock input terminal of the latch 24, respectively.

Further, each of the signals output from the counter 30 is latched and output by the latch 17 in synchronization with the rising edge of the reference clock (the rising edge of the pulse of the pulse signal output from the edge detection unit 9).

Next, the counting unit 19 counts the "1" bits of the signal output from the counter 30. That is, the number of "1" of the signal output from the counter 30 at each count value of the counter 11 is counted.

Further, the count value output from the counter 11 is input to the latch 18. The latch 18 latches and outputs the count value in synchronization with the rising edge of the reference clock (the rising edge of the pulse of the pulse signal output from the edge detection unit 9).

Next, the multiplier 25 multiplies the numerical value output from the counting unit 19 with the count value of the counter 11 output from the latch 18, and outputs the multiplied value. This multiplication value is input to one input terminal of the adder 27.

Further, in the counter 20, the latch 21 latches the signal to be measured in synchronization with the rising edge of the reference clock (the rising edge of the pulse of the pulse signal output from the edge detection unit 9) and outputs the first data. The latch 22 latches the first data in synchronization with the rising edge and the falling edge of the reference clock and outputs the second data, and the exclusive logic sum circuit 23 of the first data and the second data The exclusive logical sum is calculated to generate the output data and output it. That is, the counter 20 outputs "1" corresponding to the rising and falling edges of the signal to be measured, and outputs "0" for the others.

The signal output from the counter 20 is latched by the latch 24 in synchronization with the rising edge and the falling edge of the reference clock, is output, and is input to the reset terminal of the adder 27.

The multiplication value output from the multiplier 25 is input to one input terminal of the adder 27. Further, the output of the adder 27 is latched and output by the latch 26 in synchronization with the rising edge and the falling edge of the reference clock, and is input to the other input terminal of the adder 27.

The adder 27 adds and outputs the current multiplication value and the previous multiplication value latched on the latch 26. This output is the sum of the integrated reciprocal count values.

Although detailed description of the subsequent operations will be omitted, for example, the difference between the total sum of the current integrated reciprocal count values and the total sum of the previous integrated reciprocal count values is obtained and output. This output is the sum of the reciprocal count values. The method for obtaining the sum of the reciprocal count values is not limited to this method, and other methods may be used. Further, as described in the first embodiment, for example, a filter such as a low-pass filter or a moving average filter may be provided.

The third embodiment as described above can also exert the same effect as the above-described embodiment.

<Fourth Embodiment>
FIG. 5 is a block diagram showing a fourth embodiment of the reciprocal count value generation circuit of the present invention.

Hereinafter, the fourth embodiment will be described mainly on the differences from the above-described embodiment, and the description of the same items will be omitted.

In the fourth embodiment, for each of the reference clock and the signal to be measured, the signal inversion is both the rising edge and the falling edge of the signal.

The reciprocal count value generation circuit 1 of the fourth embodiment is a detection circuit that detects the rising and falling edges of the reference clock (Fs) and generates a pulse signal (P) synchronized with the rising and falling edges of the reference clock (Fs). The edge detection unit 9 which is an example of the above is provided. Further, the counter 110, which is an example of the second counter, has a first counting unit 111 that counts the rising edge of the reference clock (Fs) and a second counting section 112 that counts the falling edge of the reference clock (Fs). And have. Then, the counter 3 (first counter) detects the inverted edge using the pulse signal (P) detected by the edge detection unit 9, and the counter 110 (second counter) uses the reference clock (Fs). ), The first counting unit 111 counts the rising edge of the reference clock (Fs), and the second counting section 112 counts the falling edge of the reference clock (Fs).

As a result, the frequency is effectively doubled with a simple configuration, and the SN ratio can be improved. Hereinafter, a specific description will be given.

As shown in FIG. 5, the reciprocal count value generation circuit 1 of the fourth embodiment includes an edge detection unit 9, a counter 110 which is an example of a second counter, at least one delay element 12, and a plurality of second counters. A plurality of counters 3 which are an example of one counter, a plurality of latches 13, a plurality of latches 141, a plurality of latches 142, and an adder 4 are provided. Each counter 3 is electrically connected in parallel. Further, the number of delay elements 12 is one less than the number of counters 3. In the present embodiment, the number of counters 3 is 32 and the number of delay elements 12 is 31. The number of latches 13, latches 141, and latches 142 is 32, which is equal to the number of counters 3, respectively.

The edge detection unit 9, each delay element 12, and each counter 3 are the same as those in the second embodiment, and thus the description thereof will be omitted.

The counter 110 includes a first counting unit 111, a second counting unit 112, and an inverter 113 (phase inversion circuit). The second counting unit 112 is connected to the output side of the inverter 113. A series circuit including the inverter 113 and the second counting unit 112 and the first counting unit 111 are connected in parallel. Further, the output terminal of the first counting unit 111 is connected to the input terminal of each latch 141, and the output terminal of the second counting unit 112 is connected to the input terminal of each latch 142. The output terminal of each latch 141 and the output terminal of each latch 142 are connected to the input terminal of the adder 4, respectively. Further, as the first counting unit 111 and the second counting unit 112, for example, an up counter or the like can be used, respectively.

Further, the output terminal of the edge detection unit 9 is connected to the clock input terminal of the latch 31 of each counter 3, the clock input terminal of the latch 32, and the clock input terminal of each latch 13.

Further, the output terminal of each counter 3 is connected to the input terminal of the latch 13 corresponding to the counter 3. Further, the output terminal of each latch 13 is connected to the clock input terminal of the latch 141 and the clock input terminal of the latch 142 corresponding to the latch 13, respectively. Further, as the latch 13, the latch 141 and the latch 142, for example, a D latch or the like can be used.

Further, the signal to be measured is input to the input terminal of the latch 31 of the predetermined counter 3 among the plurality of counters 3 and the input terminal of the first-stage delay element 12 among the plurality of delay elements 12, respectively. There is.

Further, the reference clock is the input terminal of the delay element 91 connected to one input terminal of the exclusive OR circuit 92 of the edge detection unit 9, the other input terminal of the exclusive OR circuit 92, and the counter 110. Is input to the input terminal of the first counting unit 111 and the input terminal of the inverter 113, respectively.

Next, the operation of the reciprocal count value generation circuit 1 will be described.
As shown in FIG. 5, the same as that of the second embodiment is performed up to the middle, and "1" is output from each counter 3 corresponding to the rising and falling edges of the signal to be measured, and "0" for the others. Is output.

On the other hand, the reference clock is input to the counter 110. The first counting unit 111 counts the rising edge of the reference clock and outputs the count value of the rising edge of the reference clock.

The phase of the reference clock is inverted by the inverter 113 and input to the second counting unit 112. The second counting unit 112 counts the rising edge of the inverted reference clock formed by inverting the phase of the reference clock, that is, the falling edge of the reference clock, and outputs the count value of the falling edge of the reference clock.

The signals output from each counter 3 are latched and output by the latch 13 in synchronization with the rising edge and the falling edge of the reference clock.

Further, the count value output from the first counting unit 111 is input to each latch 141. Each latch 141 latches and outputs the count value in synchronization with the rising edge of the signal output from the latch 13.

Similarly, the count value output from the second counting unit 112 is input to each latch 142. Each latch 142 latches and outputs the count value in synchronization with the rising edge of the signal output from the latch 13.

Next, the adder 4 adds and outputs the count values output from each latch 141 and each latch 142. This output is the sum of the integrated reciprocal count values.

Although detailed description of the subsequent operations will be omitted, for example, the difference between the total sum of the current integrated reciprocal count values and the total sum of the previous integrated reciprocal count values is obtained and output. This output is the sum of the reciprocal count values. The method for obtaining the sum of the reciprocal count values is not limited to this method, and other methods may be used. Further, as described in the first embodiment, for example, a filter such as a low-pass filter or a moving average filter may be provided.

The fourth embodiment as described above can also exert the same effect as the above-described embodiment.

<Fifth Embodiment>
FIG. 6 is a block diagram showing a fifth embodiment of the reciprocal count value generation circuit of the present invention.

Hereinafter, the fifth embodiment will be described mainly on the differences from the above-described embodiment, and the description of the same items will be omitted.

In the fifth embodiment, the signal inversion is both the rising edge and the falling edge of the reference clock and the signal to be measured.

As shown in FIG. 6, the reciprocal count value generation circuit 1 of the fifth embodiment includes an inverter 115 (phase inversion circuit), a counter 110 which is an example of a second counter, and at least one delay element 12. A plurality of counters 280, which is an example of the plurality of first counters, a plurality of latches 141, a plurality of latches 142, an adder 4, and a difference calculator 8 are provided. Each counter 280 is electrically connected in parallel. Also, the number of delay elements 12 is one less than the number of counters 280. In the present embodiment, the number of counters 280 is 32 and the number of delay elements 12 is 31. The number of latches 141 and 142 is 32, which is equal to the number of counters 280, respectively.

The counter 280 includes a first counting unit 28, a second counting unit 29, a latch 131, a latch 132, and an or circuit 133.

The first counting unit 28 includes latches 281 and 282 and an exclusive OR circuit 283. The second counting unit 29 includes latches 291, 292 and an exclusive OR circuit 293. Since the first counting unit 28 and the second counting unit 29 are the same as the counter 3 of the first, second, and fourth embodiments, respectively, the description thereof will be omitted.

Further, the output terminal of the first counting unit 28 is connected to the input terminal of the latch 131, and the output terminal of the second counting unit 29 is connected to the input terminal of the latch 132. The series circuit composed of the first counting unit 28 and the latch 131 and the series circuit composed of the second counting unit 29 and the latch 132 are electrically connected in parallel. Further, the output terminal of the latch 131 and the output terminal of the latch 132 are each connected to the input terminal of the or circuit 133. Further, as the latch 131 and the latch 132, for example, a D latch or the like can be used. Since the delay element 12 is the same as the delay element 12 of the fourth embodiment, the description thereof will be omitted.

Further, the counter 110 includes a first counting unit 111 and a second counting unit 112 connected in parallel to each other. Further, the output terminal of the first counting unit 111 is connected to the input terminal of each latch 141, and the output terminal of the second counting unit 112 is connected to the input terminal of each latch 142. The output terminal of each latch 141 and the output terminal of each latch 142 are connected to the input terminal of the adder 4, respectively. Further, as the first counting unit 111 and the second counting unit 112, for example, an up counter or the like can be used, respectively. Further, as each latch 141 and each latch 142, for example, a D latch or the like can be used.

Further, the difference calculator 8 includes a latch 81 and a subtractor 82. The output terminal of the latch 81 is connected to the negative input terminal of the subtractor 82. As the latch 81, for example, a D latch or the like can be used.

Further, the output terminal of the adder 4 is connected to the positive input terminal of the subtractor 82 of the differential calculator 8 and the input terminal of the latch 81, respectively.

Further, the output terminals of the inverter 115 are the input terminal of the second counting unit 112 of the counter 110, the clock input terminal of the latch 281 of the first counting unit 28 of each counter 280, the clock input terminal of the latch 282, and the latch 131. It is connected to each of the clock input terminals of.

Further, among the counters 280, for the counter 280 to which the signal to be measured that is not delayed by the delay element 12 is input, the output terminals are the clock input terminal of the corresponding latch 141 and the clock input terminal of the corresponding latch 142. And the clock input terminal of the latch 81 of the difference calculator 8 and the clock input terminal of the subtractor 82, respectively. Further, for each of the other counters 280, the output terminals are connected to the clock input terminals of the corresponding latch 141 and the clock input terminals of the corresponding latch 142, respectively. Instead of the counter 280, the output terminals of the other counter 280 may be connected to the clock input terminal of the latch 81 of the differential calculator 8 and the clock input terminal of the subtractor 82. Further, as each of the latch 141, each latch 142, and the latch 81, for example, a D latch or the like can be used.

Further, the signal to be measured is sent to the input terminal of the latch 281 and the latch 291 of the predetermined counter 280 among the plurality of counters 280 and the input terminal of the first stage delay element 12 among the plurality of delay elements 12. , Each has been entered.

Further, the reference clocks are the input terminal of the first counting unit 111 of the counter 110, the input terminal of the inverter 115, the clock input terminal of the latch 291 of the second counting unit 29 of each counter 280, and the clock input of the latch 292. Inputs are made to the terminals and the clock input terminals of the latch 132, respectively.

Next, the operation of the reciprocal count value generation circuit 1 will be described.
As shown in FIG. 6, the reference clock is input to the first counting unit 111 and the inverter 115 of the counter 110, respectively. The first counting unit 111 counts the rising edge of the reference clock and outputs the count value of the rising edge of the reference clock.

The phase of the reference clock is inverted by the inverter 115 and input to the second counting unit 112. The second counting unit 112 counts the rising edge of the inverted reference clock formed by inverting the phase of the reference clock, that is, the falling edge of the reference clock, and outputs the count value of the falling edge of the reference clock.

Further, from the first counting unit 28 of each counter 280, "1" is output corresponding to the rise and fall of the signal to be measured, and "0" is output for the others.

Further, from the second counting unit 29 of each counter 280, "1" is output corresponding to the rise and fall of the signal to be measured, and "0" is output for the others.

However, in the first counting unit 28 and the second counting unit 29, the signal input to the clock input terminal is inverted in the phase of the reference clock by the inverter 115 in the first counting unit 28. It is an inverting reference clock, and the second counting unit 29 is different in that it is a reference clock.

Further, the signals output from the first count unit 28 of each counter 280 are the rising edges of the inverting reference clock formed by inverting the phase of the reference clock by the inverter 115 by the latch 131, that is, the reference clock. It is latched and output in synchronization with the falling edge.

Further, the signals output from the second counting unit 29 of each counter 280 are latched and output by the latch 132 in synchronization with the rising edge of the reference clock.

Next, at each counter 280, the signal output from the latch 131 and the signal output from the latch 132 are each input to the or circuit 133, and the or circuit 133 performs a predetermined arithmetic process and outputs the signal. Will be done.

Further, the count value output from the first counting unit 111 is input to each latch 141. Each latch 141 latches and outputs the count value in synchronization with the rising edge of the signal output from the corresponding counter 280.

Similarly, the count value output from the second counting unit 112 is input to each latch 142. Each latch 142 latches and outputs the count value in synchronization with the rising edge of the signal output from the corresponding counter 280.

Next, the adder 4 adds and outputs the count values output from each latch 141 and each latch 142. This output is the sum of the integrated reciprocal count values.

Next, in the difference calculator 8, the subtractor 82 subtracts the value indicated by the previous signal latched by the latch 81 from the value indicated by the signal output from the current adder 4 and outputs the value. .. This output is the sum of the reciprocal count values.

The fifth embodiment as described above can also exert the same effect as the above-described embodiment.

Further, since the edge detection unit 9 (analog element) is not used, more stable operation is possible.

<Physical quantity sensor embodiment>
FIG. 7 is a diagram showing an internal structure of a detection unit in an embodiment of an acceleration sensor which is an example of a physical quantity sensor of the present invention. FIG. 8 is a cross-sectional view taken along the line AA in FIG.

Hereinafter, the embodiment of the acceleration sensor, which is an example of the physical quantity sensor, will be described focusing on the differences from the above-described embodiment, and the description of the same matters will be omitted.

As shown in FIGS. 7 and 8, the acceleration sensor 100 (physical quantity sensor) of the present embodiment has a detection unit 200 that detects acceleration, which is an example of a physical quantity related to vibration, and a signal to be measured that is output from the detection unit 200. Is provided with a reciprocal count value generation circuit 1 (see FIG. 1 and the like for the reciprocal count value generation circuit 1) to which is input. The detection unit 200 and the reciprocal count value generation circuit 1 are electrically connected. Since the reciprocal count value generation circuit 1 has already been described, the description thereof will be omitted.

The detection unit 200 includes a flat plate-shaped base portion 210, a substantially rectangular flat plate-shaped movable portion 212 connected to the base portion 210 via a joint portion 211, and a physical quantity spanned between the base portion 210 and the movable portion 212. It includes an acceleration detection element 213, which is an example of a detection element, and a package 220 that houses at least each of the above components.

The detection unit 200 receives a drive signal applied to the excitation electrode of the acceleration detection element 213 via the external terminals 227 and 228, the internal terminals 224 and 225, the external connection terminals 214e and 214f, the connection terminals 210b and 210c, and the like. The vibrating beams 213a and 213b of the acceleration detection element 213 oscillate (resonate) at a predetermined frequency. Then, the detection unit 200 outputs the resonance frequency of the acceleration detection element 213, which changes according to the applied acceleration, as a signal to be measured (detection signal).

This measured signal is input to the reciprocal count value generation circuit 1, and the reciprocal count value generation circuit 1 operates as described in the above embodiment.

The number of detection units 200 is one in the present embodiment, but is not limited to this, and may be, for example, two or three. By providing three detection units 200 and crossing the detection axes of each detection unit 200 with each other, it is possible to detect the acceleration in each of the three detection axes orthogonal to each other.

Even with the acceleration sensor 100 as described above, the reciprocal count value generation circuit 1 included in the acceleration sensor 100 can exert the same effect as that of the above-described embodiment. As a result, the acceleration sensor 100 can accurately detect the acceleration.

The reciprocal count value generation circuit and the physical quantity sensor of the present invention have been described above based on the illustrated embodiment, but the present invention is not limited to this, and the configuration of each part is arbitrary having the same function. It can be replaced with the one of the configuration. Moreover, other arbitrary components may be added.

In addition, the present invention may be a combination of any two or more configurations (features) of each of the above embodiments.

Further, in the above embodiment, the acceleration sensor has been described as an example of the physical quantity sensor, but in the present invention, the physical quantity sensor can be used as long as it can detect the change in the physical quantity as the frequency change. In addition, the present invention includes, for example, a mass sensor, an ultrasonic sensor, an angular acceleration sensor, a capacitance sensor, and the like.

Further, the physical quantity sensor of the present invention is, for example, various electronic devices such as an inclinometer, a seismometer, a navigation device, an attitude control device, a game controller, a mobile phone, a smartphone, a digital still camera, and various mobile objects such as an automobile. Etc. can be applied. That is, in the present invention, it is possible to provide an electronic device provided with the physical quantity sensor of the present invention, a mobile body provided with the physical quantity sensor of the present invention, and the like.

1 ... Reciprocal count value generation circuit, 2 ... Delay element, 3 ... Counter, 4 ... Adder, 5 ... Counter, 6 ... Multiplier, 7 ... Integrator, 8 ... Difference calculator, 9 ... Edge detector, 10 ... Reciprocal count value generator, 11 ... counter, 12 ... delay element, 13 ... latch, 14 ... latch, 17 ... latch, 18 ... latch, 19 ... counting unit, 20 ... counter, 21 ... latch, 22 ... latch, 23 ... Exclusive logical sum circuit, 24 ... Latch, 25 ... Multiplier, 26 ... Latch, 27 ... Adder, 28 ... 1st count, 29 ... 2nd count, 30 ... Counter, 31 ... Latch, 32 ... Latch, 33 ... exclusive logic sum circuit, 71 ... adder, 72 ... latch, 81 ... latch, 82 ... subtractor, 91 ... delay element, 92 ... exclusive logic sum circuit, 100 ... acceleration sensor, 110 ... counter, 111 ... 1st count unit, 112 ... 2nd count unit, 113 ... inverter, 115 ... inverter, 131 ... latch, 132 ... latch, 133 ... or circuit, 141 ... latch, 142 ... latch, 200 ... detector, 210 ... base part, 210b ... connection terminal, 210c ... connection terminal, 211 ... joint part, 212 ... movable part, 213 ... acceleration detection element, 213a ... vibrating beam, 213b ... vibrating beam, 214e ... external connection terminal, 214f ... external Connection terminal, 220 ... Package, 224 ... Internal terminal, 225 ... Internal terminal, 227 ... External terminal, 228 ... External terminal, 280 ... Counter, 281 ... Latch, 282 ... Latch, 283 ... Exclusive logic sum circuit, 291 ... Latch , 292 ... Latch, 293 ... Exclusive logic sum circuit, 330 ... Exclusive logic sum circuit

Claims (8)

A reciprocal count value generation circuit that counts the reference clock at the timing specified by the signal to be measured.
A plurality of firsts, which are electrically connected in parallel and each of a plurality of measured signals having different phases are input, and the reference clock is used to detect an inverted edge representing an inversion of the level of the plurality of measured signals. Counter and
A second counter that counts the reference clock and
The product of the number of detected reciprocals of the measured signal at the timing specified by the reference clock and the count value of the second counter at the timing is integrated in the section specified by the measured signal. A reciprocal count value generation circuit including a reciprocal count value generation unit that generates a reciprocal count value. The first counter detects the inverted edge by using the rising edge and the falling edge of the reference clock.
The reciprocal count value generation circuit according to claim 1, wherein the second counter uses the rising edge and the falling edge of the reference clock to count the reference clock. A detection circuit for detecting the rise and fall of the reference clock and generating a pulse signal synchronized with the rise and fall of the reference clock is provided.
The first counter detects the inverted edge by using the pulse signal.
The reciprocal count value generation circuit according to claim 1, wherein the second counter uses the pulse signal to count the reference clock. A detection circuit for detecting the rise and fall of the reference clock and generating a pulse signal synchronized with the rise and fall of the reference clock is provided.
The second counter includes a first counting unit that counts the rising edge of the reference clock and a second counting section that counts the falling edge of the reference clock.
The first counter detects the inverted edge by using the pulse signal.
According to claim 1, the second counter counts the rise of the reference clock by the first counting unit and counts the fall of the reference clock by the second counting unit in counting the reference clock. The reciprocal count value generation circuit described. The reciprocal count value generation circuit according to claim 1, wherein the number of detected inverted edges of the signal to be measured is the number of rising edges or falling edges of the signals to be measured. The reciprocal count value generation circuit according to any one of claims 1 to 4, wherein the number of detected inverted edges of the signal to be measured is the total value of the number of rising edges and the number of falling edges of the plurality of measured signals. .. A detector that detects physical quantities and
A physical quantity sensor comprising the reciprocal count value generation circuit according to any one of claims 1 to 6, wherein a signal to be measured output from the detection unit is input. The physical quantity sensor according to claim 7, wherein the physical quantity is a physical quantity related to vibration.

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