JPH0653831A - Waveform sampling circuit - Google Patents

Abstract

PURPOSE:To obtain a sampling waveform with higher accuracy in resolution by shifting the sampling point of an output waveform synchronously with an input signal at the time of sampling an output waveform of a circuit block for inputting/outputting a synchronizing waveform. CONSTITUTION:An IC 16 to be measured sends an output signal corresponding to an input signal to a voltage sampling circuit 27. The circuit 27 executes sampling operation when a 360/n-ary counter 21 overflows. A 360-ary counter 22 executes count-up operation based upon a sampling start signal S10 outputted from the counter 21, the arithmetic result of an arithmetic circuit 23 is changed and the data of an output signal in each phase 1 deg. is stored in a data memory 28. The data of phases 0 deg. to 360 deg. are stored in the memory 28 in each 1 deg., and when data for one period are stored, the counter 22 overflows, so that an end command signal for ending the processing concerned is outputted and sampling processing is ended.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. Field of Industrial Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems (FIGS. 2 and 4) Actions (FIGS. 2 and 4) Embodiments (FIGS. 1 to 4) Effects of the Invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform sampling circuit, and is particularly suitable for application when sampling a high frequency signal.

[0003]

2. Description of the Related Art Conventionally, there is a measuring device which measures a characteristic of an IC by giving a predetermined input signal to the integrated circuit (IC) and sampling a signal output from the IC.

In this measuring apparatus, a pseudo-generated input signal is input to the IC to be measured via a digital analog conversion circuit (DA conversion circuit) and is output from the IC to be measured based on the input signal. The output signal is converted into digital data via an analog digital conversion circuit (AD conversion circuit), and this is sampled by a predetermined sampling circuit.

[0005]

However, in the measuring apparatus using the waveform sampling circuit of this type, when the frequency of the signal input to the IC to be measured becomes high, the DA conversion circuit and the AD conversion circuit having a high conversion speed are required. Therefore, there is a problem inevitable that the configuration becomes complicated.

As one method for solving this problem, a method of thinning the input signal waveform according to the conversion speed of the DA conversion circuit and the AD conversion circuit is considered. For example, when measuring a motor driving IC, the phase of the sine wave signal input to the motor driving IC is 0 °, 3 °, 6 ° ...
, The output signal corresponding to this gives accurate data at phases 0 °, 3 °, 6 °, ... Even when trying to obtain the signal data, the output signal at this time becomes an output signal corresponding to the input signal at the phase of 0 ° because the input signal for the phase of 1 ° of the output signal is thinned out.

Therefore, when such a method is used, there is a problem that it is difficult to obtain output signal data in a desired phase, and it has not been sufficient as a solution.

The present invention has been made in consideration of the above points, and accurately outputs the output waveform of an IC or a circuit block that inputs and outputs a high frequency signal without increasing the conversion speed of the DA conversion circuit and the AD conversion circuit. It is intended to propose a waveform sampling circuit capable of sampling.

[0009]

In order to solve such a problem, according to the present invention, in the waveform sampling circuit 10 for sampling the output signals S4, S5 and S6 of the circuit block 16 which inputs and outputs the periodic waveform, the circuit block 16
Of the circuit block 1 in synchronization with the phase in which the input signals S1, S2, S3 input to
6 output signals S4, S5, S6 are sampled, and the input signals S1, S2, S3 are targeted at a phase different from the phase where the input signals S1, S2, S3 have values corresponding to the targeted input waveform. The input signals S1, S2, S3 are changed so as to have values corresponding to the input waveform, and the sampling points of the output signals S4, S5, S6 are changed according to the change.

Further, in the present invention, the circuit block 16
The phase (360 °) for one cycle of the input signals S1, S2, S3 input to the input signal S1 is divided by the decimation number n of the input signals S1, S2, S3 to obtain the overflow value S10.
The count output D2 of the counter 21 is multiplied by the thinning-out number n, and the input signals S1 and S2 are input to the circuit block 16.
Overflow value S for the phase (360 °) of one cycle of S3
The output D3 of the second counter 22 to be _END is added to the multiplication result, and the addition result is divided by the phase (360 °) of one cycle of the input signals S1, S2, and S3 to obtain a circuit block based on the remainder P. Input signals S1, S2, and S3 to be input to 16 are generated.

Further, in the present invention, a first counter 21 which counts up by inputting a predetermined clock signal CLK, a second counter 22 which counts up when the first counter 21 overflows, and a first counter 21. Operation means 23 for generating phase data D4 that sequentially changes based on the respective count results D2, D3 output from the counter 21 and the second counter 22, and the phase data D
Input signal S to be input to the circuit block 16 based on 4
Input signal generating means 13 for generating 1, S2, S3, and an output signal S of the circuit block 16 obtained by inputting the input signals S1, S2, S3 into the circuit block 16.
Sampling means 27 for sampling 4, S5, S6 in synchronization with input signals S1, S2, S3, and sampling points of output signals S4, S5, S6 output from the circuit block 16 based on the phase data D4. To change.

[0012]

The output signal S output from the circuit block 16
4, S5 and S6 sampling points are input signals S1 and S
By changing in synchronization with 2 and S3, the output signals S4, S5, and S6 can be sampled with higher resolution.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

In FIG. 1, reference numeral 10 denotes a waveform sampling circuit for measuring the motor driving IC (IC 16 to be measured) as a whole, and an input command from the computer 11 is input to the DA converter 13 via the interface 12. D
The A converter 13 is a circuit that creates a signal to be input to the IC 16 to be measured based on an input command.
The input signal created in 1 is sent to the measurement circuit unit 14. The measurement circuit section 14 inputs the input signal created by the DA conversion section 13 to the input end of the IC 16 to be measured at a predetermined timing.

The IC 16 to be measured outputs an output signal from the output end based on the input signal input to the input end, and inputs the output signal to the measurement circuit section 14. The measurement circuit section 14 sends the output signal output from the IC 16 to be measured to the AD conversion section 15 at a predetermined timing.

The AD converter 15 AD-converts the output signal and samples the output signal, and then continues the interface 12.
This is output to the computer 11 via. Thus, the computer 11 can measure the output signal with respect to the input signal of the IC 16 to be measured.

The detailed configuration of the waveform sampling circuit 10 is shown in FIG. That is, FIG. 2 shows a waveform sampling circuit for measuring the driving IC (IC 16 to be measured) of the brushless three-phase bidirectional motor, and the timing of the input signal input to the IC 16 to be measured is obtained in the measuring circuit section 14. In the case of this embodiment, one cycle (360
Is measured every 1 °, and n °
The input signal is thinned out every 3 ° in the case of this embodiment and input to the IC 16 to be measured.

That is, the clock signal CLK obtained from a predetermined clock generating means is input to the latch circuit 25 and the 360 / n-adic counter 21. When the clock signal CLK is input, the 360 / n-ary counter 21 counts the clock signal CLK and outputs the count result to the arithmetic circuit 23 as 9-bit data D2.

When the 360 / n-ary counter 21 overflows, the sampling start signal S is generated accordingly.
10 to 360-adic counter 22 and voltage sampling circuit 2
Send to 7. The 360-adic counter 22 counts the sampling start signal S10 from the 360 / n-adic counter 21, and sends the count result to the arithmetic circuit 23 as 9 [bit] data D3.

The arithmetic circuit 23 sets the count result of the 360 / n-ary counter 21 to A and the count result of the 360-ary counter 22 to B, and

[Equation 1] Is calculated. Here, “%” in the equation (1) represents an operation for calculating the remainder of division, and the remainder obtained by dividing (A × n + B) by 360 is P.

The calculation result P is phase data D4 (9 [bit]) for creating an input signal to be input to the IC 16 to be measured.
(Comprising)) is sent to the subsequent phase conversion circuit 24.

Since the IC 16 to be measured is a brushless 3-phase bidirectional motor driving IC, the phase conversion circuit 24 has three input signal data D5, D6 and D7 of 12 [bit] each and 120 ° out of phase. To the latch circuit. The latch circuit 25 performs a latch operation based on the clock signal CLK, sends the input signal data D5, D6 and D7 to the pseudo input signal generation circuit 26, and digital-analog converts the data.

The input signals converted into the analog signals S1, S2 and S3 in the pseudo input signal generating circuit 26 are input to the input terminals U _IN , V _IN and W _IN of the IC 16 to be measured, respectively. The IC 16 to be measured has input terminals U _IN , V _IN and W _IN.
Output signals S4, S5 and S6 corresponding to the input signals S1, S2 and S3 input to the output terminals U _OUT , V _OUT and W
Output from _OUT to the subsequent voltage sampling circuit 27.

The voltage sampling circuit 27 starts the sampling operation based on the sampling start signal S10 from the 360 / n-adic counter 21, and samples the output signals S4, S5 and S6 output from the IC 16 to be measured. This sampling operation is executed at a timing synchronized with the phase of the input signal input to the IC 16 to be measured.

Thus, the output signals S4, S5 and S6 sampled by the voltage sampling circuit 27.
Are output to and stored in the data memory 28 as 12 [bit] output signal data D11, D12, and D13, respectively.

A description will be given of a case in which a similar sine wave signal is output from the IC 16 to be measured when a sine wave signal as shown in FIG. That is, the input signal to the IC 16 to be measured is thinned and generated at the timing of the phases 0 °, 3 °, 6 ° ... Based on the phase data D4 from the arithmetic circuit 23, and is input to the IC 16 to be measured.

The IC 16 to be measured sends an output signal corresponding to the input signal to the voltage sampling circuit 27. The voltage sampling circuit 27 executes a sampling operation when the 360 / n-ary counter 21 overflows. Therefore, Figure 4
As shown in (A), when one cycle (360 °) of the signal of each phase 0 °, 3 °, 6 ° input to the IC 16 to be measured has passed (that is, phase 360 ° (= phase 0 °) 2) is sampled by the voltage sampling circuit 27 and stored in the data memory 28.

At this time, the 360 / n-ary counter 2 receives the sampling start signal S10 from the 360 / n-ary counter 21.
2 counts up, the calculation result P in the calculation circuit 23 changes, and the input signal input to the IC 16 to be measured has phases 1 °, 4 °, and 7 ° as shown in FIG. 4B.
... data is entered. When this input signal has passed one cycle, the sampling start signal S10 from the 360 / n-adic counter 21 is input to the voltage sampling circuit 27, so that the phase 361 ° (that is, phase 1 °) is output after the one period has passed. The signal data is sampled,
It is stored in the data memory 28.

In this way, the phases are sequentially 0 °, 1 °, 2
The data of the output signal for each phase 1 ° is stored in the data memory 28 as in ° ..., so that the data memory 28 stores the data of the phase 0 ° to 360 ° for each 1 °. When all data for a minute is stored 360
When the advance counter 22 overflows, the end command signal S _END for ending the process is output, and the sampling process is ended.

By sequentially switching the sampling points in this way, the input signal is thinned out every 3 ° phase in accordance with the processing speed of the digital analog conversion circuit of the pseudo input signal generation circuit 26 and the analog digital conversion circuit of the voltage sampling circuit 27. Even when it is necessary, the data of the output signal can be obtained for each phase of 1 °.

Therefore, even when the frequency of the signal input to the IC 16 to be measured is high, the output signal is sampled with high resolution without increasing the speed of the signal processing system such as the digital analog conversion circuit and the analog digital conversion circuit. be able to.

According to the above configuration, sampling is performed in synchronization with the input signal input to the IC 16 to be measured, and the input signal and the sampling point are shifted so that the input signal is thinned by a predetermined phase. Even when inputting to the IC to be measured 16, the data of the output signal can be obtained with high resolution.

Therefore, it is possible to accurately sample a high frequency signal with a simple circuit configuration without using a circuit having a high processing speed as a signal processing system such as a digital analog conversion circuit and an analog digital conversion circuit. Further, the measurement circuit unit 14 can be configured by software.

In the above embodiment, the IC to be measured is
Although the case where the input signal input to 16 is thinned out every 3 ° of phase has been described, the present invention is not limited to this, and it is possible to thin out every various phases. In this case 360 /
The decimation number n of the n-ary counter 21 may be changed.

In the above embodiment, the IC to be measured is
16 is an IC for driving a brushless three-phase bidirectional motor
Although the present invention has been described above, the present invention is not limited to this, and can be widely applied to the case of measuring various ICs, and further to the case of sampling the output waveforms of other various circuit blocks.

[0036]

As described above, according to the present invention, when sampling the output waveform of the circuit block which inputs / outputs the periodic waveform, the sampling point of the output waveform is shifted in synchronization with the input signal. Thus, it is possible to realize a waveform sampling circuit that can obtain an accurate sampling waveform with a higher resolution.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a measuring apparatus using a waveform sampling circuit according to the present invention.

FIG. 2 is a block diagram showing a detailed configuration of a waveform sampling circuit according to the present invention.

FIG. 3 is a signal waveform diagram showing a signal waveform input to an IC to be measured.

FIG. 4 is a signal waveform diagram provided for explanation when sampling an output waveform of an IC to be measured.

[Explanation of symbols]

10 ... Waveform sampling circuit, 11 ... Computer, 13 ... DA conversion section, 14 ... Measurement circuit section, 15 ...
AD converter, 16 ... IC to be measured, 21 ... 360 / n-ary counter, 22 ... 360-ary counter, 23 ... Arithmetic circuit, 27 ... Voltage sampling circuit, 28 ... Data memory, S10 ... Sampling start signal, D4 ...
Phase data.

Claims (3)

[Claims] 1. A waveform sampling circuit for sampling an output signal of a circuit block for inputting / outputting a periodic waveform, wherein the input signal input to the circuit block is synchronized with a phase having a value corresponding to a target input waveform. The output signal output from the circuit block is sampled, and the input signal has a value corresponding to the target input waveform at a phase different from the phase at which the input signal has a value corresponding to the target input waveform. A waveform sampling circuit, characterized in that the input signal is changed to, and the sampling point of the output signal is changed according to the change. 2. One of the input signals input to the circuit block.
The count output of the first counter, whose overflow value is the result of dividing the phase of the cycle by the decimation number of the input signal, is multiplied by the decimation number, and the one cycle of the input signal input to the circuit block is multiplied. The input that adds the output of the second counter whose phase is the overflow value to the multiplication result, and inputs the addition result to the circuit block based on the remainder value obtained by dividing the addition result by the phase of one cycle of the input signal. The waveform sampling circuit according to claim 1, wherein the waveform sampling circuit is configured to generate a signal. 3. A first counter which counts up by inputting a predetermined clock signal, a second counter which counts up when the first counter overflows, a first counter and a first counter. Arithmetic means for generating phase data that sequentially changes based on the respective count results output from the second counter; input signal generation means for generating the input signal to be input to the circuit block based on the phase data; An output signal of the circuit block obtained by inputting the input signal to the circuit block; and sampling means for sampling in synchronization with the input signal, and outputting from the circuit block based on the phase data. The sampling point of the output signal to be changed is changed. The waveform sampling circuit according to 1.