JPS6338890B2 - - Google Patents
Info
- Publication number
- JPS6338890B2 JPS6338890B2 JP57212418A JP21241882A JPS6338890B2 JP S6338890 B2 JPS6338890 B2 JP S6338890B2 JP 57212418 A JP57212418 A JP 57212418A JP 21241882 A JP21241882 A JP 21241882A JP S6338890 B2 JPS6338890 B2 JP S6338890B2
- Authority
- JP
- Japan
- Prior art keywords
- amplitude
- output
- multiplier
- logarithmic converter
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000009466 transformation Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G11/00—Limiting amplitude; Limiting rate of change of amplitude ; Clipping in general
Landscapes
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
Description
【発明の詳細な説明】
本発明はデイジタル信号処理における直交二成
分Ｉ，Ｑに分解される複素信号の振幅制限方式に
関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an amplitude limiting method for a complex signal decomposed into orthogonal two components I and Q in digital signal processing.
従来、中間周波数帯における振幅制限方式は種
種あつたが、デイジタル信号処理における直交二
成分Ｉ，Ｑに分解される複素信号の振幅制限方式
に関するものはなかつた。 Conventionally, there have been various amplitude limiting methods in the intermediate frequency band, but none of them have been related to amplitude limiting methods for complex signals decomposed into orthogonal two components I and Q in digital signal processing.
本発明は入力複数信号のベタトル直交成分Ｉ信
号（Inphase；同相）およびＱ信号
（Quadrature；直交）よりその振幅を検出し、所
定の振幅制限値との比および大小関係を求め、入
力振幅が振幅制限値より小さい場合は乗数“１”
を、大きい場合は振幅制限値との比（１より小さ
い値）を、入力の直交成分Ｉ，Ｑにそれぞれ乗ず
ることにより、振幅制限できる振幅制限方式を提
供することを目的としている。 The present invention detects the amplitude from the Betator quadrature component I signal (Inphase) and Q signal (Quadrature) of input multiple signals, determines the ratio and magnitude relationship with a predetermined amplitude limit value, and determines whether the input amplitude is the amplitude Multiplier “1” if smaller than limit value
The purpose of this invention is to provide an amplitude limiting method that can limit the amplitude by multiplying the input orthogonal components I and Q by the ratio (value smaller than 1) to the amplitude limit value if it is large.
以下、この発明の一実施例を図について説明す
る。第１図において、１は入力複素信号のベクト
ル直交成分Ｉの入力端子、２は同Ｑの入力端子、
３は入力の直交成分Ｉ，Ｑより√2＋2演算して
振幅Ａを検出する振幅検出器、４は振幅Ａを対数
変換する対数変換器、５は対数表示された振幅制
限値Ｂより対数変換器５の結果を減ずる減算器、
６は減算器５の出力を逆対数変換し、B/Aを出
力する逆対数変換器、７は減算器５の出力の符号
ビツトにより符号が正の場合は“１”を、負の場
合は対数変換器出力のB/Aを切換えて出力する
切換器、８は入力の直交成分Ｉ，Ｑに切換器７の
出力を乗ずる乗算器、９は１０は振幅制限処理後
の出力端子である。 An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1 is the input terminal of the vector orthogonal component I of the input complex signal, 2 is the input terminal of the same Q,
3 is an amplitude detector that calculates the amplitude A by calculating √ 2 + 2 from the orthogonal components I and Q of the input, 4 is a logarithmic converter that converts the amplitude A logarithmically, and 5 is a logarithm converter that converts the amplitude limit value B expressed logarithmically. a subtractor that subtracts the result of the converter 5;
6 is an antilogarithmic converter that performs antilogarithmic transformation on the output of the subtracter 5 and outputs B/A. 7 is an antilogarithmic converter that performs antilogarithmic conversion on the output of the subtracter 5 and outputs B/A. 7 indicates a sign bit of the output of the subtracter 5, and if the sign is positive, it will be "1", if it is negative, it will be "1". A switch 8 switches and outputs B/A of the logarithmic converter output, a multiplier 8 multiplies input orthogonal components I and Q by the output of the switch 7, and 9 and 10 are output terminals after amplitude limiting processing.
第２図は第１図の動作説明図である。 FIG. 2 is an explanatory diagram of the operation of FIG. 1.
次に動作を説明する。 Next, the operation will be explained.
入力端子１，２から入力した複素信号の直交成
分Ｉ，Ｑは第２図に示すような振幅Ａ、位相角Θ
を有する複素入力信号を直交分離したものであ
る。 The orthogonal components I and Q of the complex signals input from input terminals 1 and 2 have an amplitude A and a phase angle Θ as shown in Fig. 2.
is obtained by orthogonally separating a complex input signal having .
先ず、入力複素信号の直交成分Ｉ，Ｑは振幅検
出器３に導びかれ√2＋2演算により振幅Ａを検
出する。次に振幅Ａを対数変換器４により対数変
換しLOG(A)を求める。減算器５では振幅制限値
Ｂの対数表示値LOG(B)からLOG(A)を減じて、
LOG(B)−LOG(A)＝Ｃを求める。この減算により
等価的に次のことが実現できることになる。 First, the orthogonal components I and Q of the input complex signal are led to the amplitude detector 3, and the amplitude A is detected by √ 2 + 2 calculation. Next, the amplitude A is logarithmically converted by a logarithmic converter 4 to obtain LOG(A). The subtracter 5 subtracts LOG(A) from the logarithmic display value LOG(B) of the amplitude limit value B.
Find LOG(B)−LOG(A)=C. By this subtraction, the following can be equivalently realized.
符号ビツトはＡとＢの大小関係を示し、符号
が正の時はＢＡ、符号が負の時はＢ＜Ａであ
る。 The sign bit indicates the magnitude relationship between A and B; when the sign is positive, it is BA, and when the sign is negative, B<A.
LOG(B)−LOG(A)の演算結果を逆対数変換す
ることによりB/Aを求めることができる。 B/A can be obtained by performing antilogarithmic transformation on the calculation result of LOG(B)−LOG(A).
このようにして得られた減算結果Ｃは次の逆対
数変換器６で対数から真数に変換され、B/Aを
得る。そして、この結果として減算器５の符号ビ
ツトにより切換器７では符号が正の時「１」を、
負の時「B/A」を出力する。この出力を乗算器
８で直交成分Ｉ，Ｑに乗じて振幅制限を行なう。 The subtraction result C thus obtained is converted from a logarithm to an antilogarithm in the next antilogarithm converter 6 to obtain B/A. As a result, when the sign bit of the subtracter 5 is positive, the switch 7 outputs "1".
Outputs "B/A" when negative. This output is multiplied by the orthogonal components I and Q in a multiplier 8 to limit the amplitude.
このことから、Ａ＞Ｂの時は直交成分Ｉ，Ｑに
「B/A」を乗ずることになり第２図に示す通り振
幅制限値Ｂに制限され、ＡＢの時は直交成分
Ｉ，Ｑに「１」を乗ずることにより、入力の直交
成分Ｉ，Ｑがそのまま出力されることになり、複
素数の振幅制限が成される。 From this, when A>B, the orthogonal components I and Q are multiplied by "B/A" and are limited to the amplitude limit value B as shown in Figure 2, and when AB, the orthogonal components I and Q are multiplied by "B/A". By multiplying by "1", the input orthogonal components I and Q are output as they are, and the amplitude of the complex number is limited.
ここで、逆対数変換器６は以上のような動作で
あるので、Ａ＞Ｂに関する逆対数変換が不要であ
ることは言うまでもない。 Here, since the anti-logarithmic converter 6 operates as described above, it goes without saying that anti-logarithmic conversion regarding A>B is unnecessary.
なお、上記実施例では、振幅検出器３は√2＋
Q2演算により求めたが、振幅制限結果が所要値
に対してある程度の誤差を含んでも良いならば、
直交成分Ｉ，Ｑの大小比較による簡易法、すなわ
ち、｜Ｉ｜｜Ｑ｜時は｜Ｉ｜＋｜Ｑ｜／２，｜Ｉ｜
＜｜Ｑ｜時は｜Ｉ｜／２＋｜Ｑ｜による振幅検出を
行なつてもかまわない。 In addition, in the above embodiment, the amplitude detector 3 is √ 2 +
It was obtained by Q 2 calculation, but if it is okay for the amplitude limit result to include a certain amount of error from the required value, then
A simple method by comparing the magnitude of orthogonal components I and Q, that is, |I||Q| time is |I|+|Q|/2, |I| <|Q| time is |I|/2+|Q| Amplitude detection may also be performed.
また、対数変換器４と減算器５および逆対数変
換器６による除算機能は一般的な除算回路を用い
ても同じ効果を得ることができる。 Further, the division function of the logarithmic converter 4, subtractor 5, and antilogarithmic converter 6 can achieve the same effect even if a general division circuit is used.
以上のように、この発明によれば複素入力信号
の直交成分Ｉ，Ｑから入力振幅Ａを求め、振幅制
限値Ｂとの比B/Aと振幅の大小関係によりＡ
Ｂ時は「１」を、Ａ＞Ｂ時は「B/A」を複素入
力信号の直交成分Ｉ，Ｑに乗ずるようにしたの
で、精度の高い振幅制限結果が得られる効果があ
る。 As described above, according to the present invention, the input amplitude A is obtained from the orthogonal components I and Q of a complex input signal, and A
Since the orthogonal components I and Q of the complex input signal are multiplied by "1" when B is applied and by "B/A" when A>B, a highly accurate amplitude limiting result can be obtained.
第１図は本発明の一実施例を示す図、第２図は
その動作説明図である。
１と２は入力端子、３は振幅検出器、４は対数
変換器、５は減算器、６は逆対数変換器、７は切
換器、８は乗算器、９と１０は出力端子。
FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is an explanatory diagram of its operation. 1 and 2 are input terminals, 3 is an amplitude detector, 4 is a logarithmic converter, 5 is a subtracter, 6 is an antilogarithmic converter, 7 is a switch, 8 is a multiplier, and 9 and 10 are output terminals.
Claims (1)
（Inphase，同相）およびＱ（Quadrature，直交）
により√2＋2演算して振幅を検出する振幅検出
器と、この振幅を対数変換する対数変換器と、こ
の対数変換器出力を対数表示による所定振幅制限
値から減じる減算器と、この減算器出力を逆対数
変換する逆対数変換器と、前記減算器出力の符号
が正の場合は乗数“１”を、符号が負の場合は前
記逆対数変換器出力を切換えて出力する乗数切換
器と、入力のベクトル直交成分Ｉ，Ｑに乗数切換
器出力を乗ずる乗算器とを備え、直交二成分に分
割される複素信号の振幅制限を行なうようにした
ことを特徴とする振幅制限方式。1 Vector orthogonal component I of complex input signal
(Inphase) and Q (Quadrature)
An amplitude detector that detects the amplitude by calculating √ 2 + 2 , a logarithmic converter that logarithmically converts this amplitude, a subtractor that subtracts the output of this logarithmic converter from a predetermined amplitude limit value expressed in logarithm, and this subtracter. an anti-logarithmic converter for anti-logarithmically converting an output; and a multiplier switcher for switching and outputting a multiplier "1" when the sign of the output of the subtracter is positive, and switching the output of the anti-logarithmic converter when the sign is negative. , a multiplier for multiplying input vector orthogonal components I and Q by the output of a multiplier switch, and limiting the amplitude of a complex signal divided into two orthogonal components.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57212418A JPS59101917A (en) | 1982-12-01 | 1982-12-01 | Amplitude limiting system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57212418A JPS59101917A (en) | 1982-12-01 | 1982-12-01 | Amplitude limiting system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59101917A JPS59101917A (en) | 1984-06-12 |
| JPS6338890B2 true JPS6338890B2 (en) | 1988-08-02 |
Family
ID=16622253
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57212418A Granted JPS59101917A (en) | 1982-12-01 | 1982-12-01 | Amplitude limiting system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59101917A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0534776Y2 (en) * | 1987-10-07 | 1993-09-02 |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05218774A (en) * | 1992-01-31 | 1993-08-27 | Nec Corp | Digital amplitude limiter |
-
1982
- 1982-12-01 JP JP57212418A patent/JPS59101917A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0534776Y2 (en) * | 1987-10-07 | 1993-09-02 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59101917A (en) | 1984-06-12 |
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