JPS6349418B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a single frequency signal receiver that detects a pulse code modulated single frequency signal using digital signal processing technology.

As a conventional single frequency signal receiver of this type, the one shown in FIG. 1 is known. (In the following, we will explain the case where the input signal frequency is in the range of 1/2 to 1/4 of the sampling frequency.) In Figure 1, 1 is the input terminal for the pulse code modulated single frequency signal, and 2 is the input terminal for the non-pulse code modulated single frequency signal. 3 is a band pass filter that tunes to the signal frequency to be detected; 4 is a band pass filter; 5 is a rectifier circuit that rectifies the output of 3 to obtain a DC output; 5 is a rectifier circuit 4; A detection circuit compares the output of 1 with a threshold value to determine the presence or absence of a signal, and 6 indicates an output terminal for the signal detection result.

In such a configuration, the nonlinear code of the single frequency signal inputted from the input terminal 1 is converted into a linear code in the expansion circuit 2, and only the signal frequency to be detected is passed by the bandpass filter 3.

Next, the output of the bandpass filter 3 is converted into a rectifier circuit 4.
The detection circuit 5 compares the rectified output with a threshold value to determine the presence or absence of a signal, and outputs the determination result from the output terminal 6.

In such a conventional single-frequency signal receiver, when the dynamic range of the input signal is large, the selectivity required of the bandpass filter 3 becomes large, and as a result, the filter order of the bandpass filter 3 increases, and the operational word This has resulted in a significant increase in length, which has the disadvantage of increasing the amount of hardware in the device.

It is an object of the present invention to provide a single frequency signal receiver with a very low amount of construction hardware.

In order to achieve such an objective, in the present invention, after amplitude modulating an input signal pulse code modulated at a sampling frequency fs with a sine wave of a single frequency 1/2 fs,
The amplitude is limited by a limiter, and the output of this limiter is subjected to a convolution operation using a finite impulse response filter that includes multiplication using an exclusive OR circuit, and the result is vector-evaluated to obtain an evaluation value. The feature is that signal detection is performed by comparing with a threshold value.

Hereinafter, embodiments of the present invention will be described in detail with reference to FIG.

In FIG. 2, 11 is an input terminal for a single frequency signal, 12 is a multiplier circuit for multiplying the input signal by (-1) ⁿ , and 1
3 is a limiter, 14 and 15 are exclusive OR circuits,
16 and 17 are integration circuits, 18 are multipliers 19 and 2
0, a vector evaluation circuit consisting of an adder 21, 22
2 is a detection circuit, 23 and 24 are threshold generation circuits, and 2
5 is an output terminal.

In such a configuration, it is assumed that the input signal x(n) from the input terminal 11 is a pulse code modulated signal (PCM signal) sampled at 8 KHz. By multiplying this input signal x(n) by (-1) ⁿ in the multiplication circuit 12, that is, by inverting the sign pit every other sample, the spectrum is shifted by 4 KHz.

This modulation is provided for the following purposes. The input signal is converted into a square wave by the action of the downstream limiter 13, but since the fundamental wave component is lower in frequency and has a higher sampling density, the level is more stable than the signal wave. , 2K signal wave of 2KHz or more
It was installed to invert the frequency below Hz.

The limiter 13 converts a signal with a level higher than the emotional level range determined by the threshold generation circuit 23 into a square wave of a constant level. This is directly 8
This is done by processing a bit pulse code modulated signal.

If the threshold value is L, the output x'(n) of the limiter 13 can only have two values of ±L.

Next, bandpass filtering is performed by the convolution operation shown in equation (1).

However, h _e (n) and h ₀ (n) are filter coefficients to obtain a 90° phase difference output.

Since x'(n) at this time has two values of ±L,
This can be easily realized using exclusive OR circuits 14 and 15. If the filter coefficients are quantized to, for example, 8 bits, subsequent arithmetic processing can also be performed with a word length of 8 bits, which, together with the fact that the multiplier can be implemented with an exclusive OR circuit, reduces the hardware requirements. It is possible to make large-scale reductions.

A vector evaluation circuit 18 performs vector evaluation on the calculation result of equation (1) to obtain the power of the input signal. That is, the squares of A and B obtained by the exclusive OR circuits 14 and 15 are calculated by the multiplier circuits 19 and 20, and the sum A ² +
Find B ² .

The result evaluated by the evaluation circuit 18 is sent to the detection circuit 22 and compared with the threshold value generated by the threshold generation circuit 24 to determine the presence or absence of the signal.

According to the present invention as described above, the following effects can be obtained.

(1) Directly process the nonlinear code with a limiter, and
Since a value output is obtained and a convolution operation is performed on the binary output, multiplication can be realized using an exclusive OR circuit, and all processing can be performed using a short word length (for example, 8 bits). This makes the configuration hardware extremely simple.

(2) Since the input signal is modulated and shifted to the lower frequency side and then limited by the limiter, it is possible to minimize the impression ambiguity width in the receiver level direction and receive high frequency single frequency signals. It is particularly effective for

It goes without saying that the present invention is not limited to the embodiments described above, and that various modifications can be made.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional single frequency signal receiver, and FIG. 2 is a block diagram of an embodiment of a single frequency signal receiver according to the present invention. 12... Multiplier circuit, 13... Limiter circuit, 1
4, 15...exclusive OR circuit, 16, 17...
Integration circuit, 18...Vector evaluation circuit, 22...
detection circuit.

Claims (1)

[Claims] 1. means for inputting a single frequency signal pulse code modulated at a sampling frequency fs; means for amplitude modulating the input signal from the means with a sine wave having a frequency of 1/2 fs;
limiter means for amplitude limiting the signal from the limiter means; means having an exclusive OR circuit for performing a convolution operation on the output from the limiter means; means for vector evaluation of the operation results of the means; 1. A single-frequency signal receiver comprising means for detecting a signal by comparing an evaluation value of said means with a threshold value.