JPS5936463A - Receiver of single frequency signal - Google Patents

Abstract

PURPOSE:To reduce the amount of hardware, by shifting an input signal subjected to pulse code modulation into a low-frequency region with amplitude modulation and processing BPF with convolutional operation after passing through a limiter. CONSTITUTION:The input signal sampled in a sampling frequency fs is multiplied by signals of (-1)<n>=+1, -1+1 and the spectrum of the input signal is shifted to the low frequency. An output of the multiplier 12 is inputted to a limiter 13 and + or -L binary signals are outputted from the limiter 13. The output of the limiter 13 is inputted to the convolutional operation circuit (exclusive OR circuits 14, 15 and integration circuits 16, 17) processing the band pass filtering. The output of the circuits 16, 17 is squared by square circuits 19, 20 and the sum is discriminated by a detection circuit 22.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a single frequency signal receiver that detects a pulse code modulated single frequency signal using digital signal processing technology.

As a conventional single frequency signal receiver of this type, the one shown in FIG. 1 is known. (Below, the case where the input signal frequency is in the range of ) to ) of the sampling frequency will be explained. ) In Fig. 1, l is an input terminal for a pulse code modulated single frequency signal, an expansion circuit converts a 2Fi non-linear code into a linear code, 3 is a bandpass filter tuned to the signal frequency to be detected, and 4 is a bandpass filter tuned to the signal frequency to be detected. A bandpass filter, a rectifier circuit that rectifies the output of 3 to obtain a DC output, 5 a detection circuit that compares the output of the rectifier circuit number with a threshold value and determines the presence or absence of a signal, 6 an output terminal for the signal detection result. show.

In such a configuration, the nonlinear code of the single frequency signal inputted from the input terminal l is converted into a linear code in the expansion circuit 2, and only the signal frequency to be detected is passed by the bandpass filter 3.

Next, the output of the bandpass filter 3 is rectified by a rectifier circuit 4, the rectified output is compared with a threshold value by a detection circuit 5, the presence or absence of a signal is determined, and the determination result is outputted from an output terminal 6.

In such a conventional single frequency signal receiver, when the input signal has a large dynamic range, the bandpass filter 3
The selectivity di required for the band pass filter 3 increases, and as a result, the filter order of the bandpass filter 3 increases, and the calculation word length increases significantly, resulting in an increase in the amount of hardware in the device. there were.

SUMMARY OF THE INVENTION An object of the present invention is to provide a single-frequency signal receiver with an extremely small amount of hardware. After the code-modulated input signal is amplitude-modulated with a sine wave of frequency ÷ fs, the amplitude is limited by a limiter, and the output of the limiter is multiplied by a finite impulse response filter using an exclusive OR circuit. The feature is that signal detection is performed by performing a convolution operation, vector-evaluating the result, and comparing the evaluation value with a threshold.

Hereinafter, a practical example of the present invention will be explained in detail with reference to FIG.

In Figure 2, 11 is an input terminal for a single frequency signal, 12 is a multiplication circuit for the input signal and (-1)n, 13 is a limiter, 14 and 15 are exclusive OR circuits, and l and l are integration circuits. , 18 is a vector evaluation circuit consisting of a multiplier 19.20 and an adder 21, 22 is a detection circuit, 23.24 is a threshold generation circuit, and 25 is an output terminal. The input signal x(rL) from 11 is a pulse code modulated signal (P
CM signal). This input signal X←) is applied to the multiplier circuit 12
+11 by multiplying by (-1)n, i.e. by inverting the sign bit at every other sample.
Shift the spectrum by 2.

This modulation is provided for the following purposes.

The input signal is converted into a square wave by the action of the downstream limiter 13, but the level of the fundamental wave component is stable when the sampling density is small at the low frequency where the signal wave is generated. It was installed to invert signal waves of 2Kllz or higher to 2KH2 or lower.

The limiter 13 converts a signal with a level greater than the emotional level range determined by the threshold generation circuit 23 into a square wave of a constant level. This is performed by directly processing the 8-bit pulse code modulated signal. The output x'(rL) of this limiter 13 sets the threshold to L
Then, +11. It is possible only with two values.

Next, band-pass filtering is performed using the convolution calculation shown in equation +11.

However, A, (n), A o (n) are 90
It is a filter coefficient that obtains a phase difference output.

Since =C-) at this time is a binary value, it can be easily realized by the antagonistic OR circuit 15. Now, if the filter coefficient is condensed to 8 bits, for example,
The subsequent operations can also be performed using word-length bits, and this combined with the fact that the multiplier can be realized with an exclusive OR circuit,
/S-Dware can be greatly reduced.

A vector evaluation circuit 18 performs vector evaluation on the calculation result of the +11 formula to obtain the power of the input signal. That is, the squares of A and B obtained by exclusive OR circuits 14 and 15 are obtained by multiplier circuits 19 and 20, and furthermore, the sum of the sum 10B' is obtained by addition circuit 21.

Then, the result evaluated by the evaluation circuit 18 is sent to the detection circuit relative, and compared with the threshold value generated by the threshold generation circuit 24, thereby determining the presence or absence of the signal.

According to the present invention as described above, the following effects can be obtained.

(1) Process the nonlinear code directly with a limiter, and
Since we obtain a value output and perform the convolution performance of the binary output, it can be realized with an exclusive OR circuit, and also,
Since all processing can be performed with a short length (e.g. 8 bits), the configuration hardware can be extremely simple.

(2) Since the input signal is modulated and shifted to the lower frequency side and then limited by the limiter, it is possible to minimize the impression ambiguity width in the receiver level direction and receive high frequency single frequency signals. It is particularly effective for

It goes without saying that the present invention is not limited to the embodiments described above, and that various modifications can be made.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional single frequency signal receiver, and FIG. 2 is a block diagram of an embodiment of a single frequency signal receiver according to the present invention. 12...Multiplication circuit 13...Limiter circuit 1415...Exclusive OR circuit 17...Integrator circuit 1st...Vector evaluation circuit 22...Detection circuit

Claims (1)

[Claims] means for inputting a single frequency signal pulse code modulated at a sampling frequency is;
means for amplitude modulating with a sine wave of s, limiter means for limiting the amplitude of the signal from the means, and means having an exclusive OR circuit for performing a convolution operation on the output from the limiter means; A single-frequency signal receiver comprising means for vector-evaluating the p1-result of the means, and means for detecting a signal by comparing the evaluation value of the means with a threshold.