JPS6158065B2 - - Google Patents

Info

Publication number
JPS6158065B2
JPS6158065B2 JP53098884A JP9888478A JPS6158065B2 JP S6158065 B2 JPS6158065 B2 JP S6158065B2 JP 53098884 A JP53098884 A JP 53098884A JP 9888478 A JP9888478 A JP 9888478A JP S6158065 B2 JPS6158065 B2 JP S6158065B2
Authority
JP
Japan
Prior art keywords
class
sampling
result
value
partial response
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53098884A
Other languages
Japanese (ja)
Other versions
JPS5525296A (en
Inventor
Kojiro Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP9888478A priority Critical patent/JPS5525296A/en
Publication of JPS5525296A publication Critical patent/JPS5525296A/en
Publication of JPS6158065B2 publication Critical patent/JPS6158065B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/38Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40Transmitting circuits; Receiving circuits
    • H04L25/49Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/497Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems by correlative coding, e.g. partial response coding or echo modulation coding transmitters and receivers for partial response systems

Landscapes

  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)

Description

【発明の詳細な説明】 本発明はクラス4パーシヤルレスポンスを用い
たデータ伝送受信機におけるサンプリング位相制
御装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sampling phase control device in a data transmission receiver using class 4 partial response.

クラス4パーシヤルレスポンスは第1図に示さ
れるインパルス応答で特徴づけられる相関伝送の
1つのクラスであるが、このようなインパルス応
答を持つ波形は従来用いられている波形の対称性
を探査するサンプリング位相制御方法の適用が困
難とされてきた。本発明はクラス4パーシヤルレ
スポンスの相関を一旦逆変換により取り除くこと
により、通常の相関伝送と同様の意味で波形の対
称点にサンプリング位相を制御する手段を提供す
る。
Class 4 partial response is a class of correlated transmission characterized by the impulse response shown in Figure 1, and waveforms with such impulse responses are produced by conventional sampling methods used to explore the symmetry of waveforms. It has been difficult to apply phase control methods. The present invention provides means for controlling the sampling phase to a symmetric point of a waveform in the same sense as normal correlation transmission by once removing the correlation of class 4 partial responses by inverse transformation.

以下、本発明の原理につき詳細に述べる。 The principle of the present invention will be described in detail below.

ランダムな送信シンボル系列を{ai}、インパ
ルス応答のサンプル値を第1図のようにh-k……
h0,h1,h2,……hkとすると受信されたベース
バンド信号のt=nTにおけるサンプル値yoは雑
音を除いて と表わされる。クラス4パーシヤルレスポンスで
はh0〓1,h2〓−1であるから、 となり、yoからは(ao−ao-2)の推定値bo
得られる。
The random transmission symbol sequence is {ai}, and the sample value of the impulse response is h -k as shown in Figure 1.
Let h 0 , h 1 , h 2 , ... h k be the sample value y o of the received baseband signal at t=nT, excluding noise. It is expressed as In class 4 partial response, h 0 〓1, h 2 〓-1, so Therefore, the estimated value b o of (a o −a o-2 ) is obtained from yo .

今、boに対してクラス4パーシヤルレスポン
スの相関を取り除く逆変換を施すと、 co=co-2+bo =ao+c とaoの推定値aoと不定々数cとの和が得られ
る。
Now, if we apply inverse transformation to b o to remove the correlation of the class 4 partial response, c o = c o -2 + b o = a o + c and the estimated value of a o and the indeterminate number c. You can get peace.

ここでco-1とyoとの相関をRoとすると、Ro
の平均値は ここでデータ系列{ak}は平均値0のランダ
ム系列であると仮定する(この仮定はスクランブ
ラーを用いた通常のデータ伝送で成立つ)と、 は符号平均電力i =0 が成立するので上式右辺第1項は判定結果ao-1
が殆んど正しいとするとi=n−1の時のみ非零
の値をとり、第2項は零となる。
Here, if the correlation between c o-1 and y o is R o , then R o
The average value of Here, assuming that the data sequence {a k } is a random sequence with an average value of 0 (this assumption holds true in normal data transmission using a scrambler), 2 holds that the code average power i = 0, so the first term on the right side of the above equation is the judgment result a o-1
If is almost correct, it takes a non-zero value only when i=n-1, and the second term becomes zero.

従つて o 2ho-(o-1)2h1 更に通常平均電力は1に正規化するので結
o=h1 となり第1図のインパルス応答サンプル値h1に対
応する値となる。
Therefore, R o = 2 h o-(o-1) = 2 h 1 Furthermore, since the average power 2 is normally normalized to 1, o = h 1 , which corresponds to the impulse response sample value h 1 in Figure 1. becomes.

h1の値は、第1図に示すようにサンプリング位
相が遅いと負の値をとり、サンプリング位相が早
いと正の値をとることとなり、h1が零交叉する所
が最適のサンプリング位相となることがわかる。
したがつて、このoを、サンプリング位相制御
情報として用いることができ、この方法によれば
データ送信間隔T秒毎の情報のみで制御をかけら
れる。クラス4パーシヤルレスポンスのインパル
ス応答、すなわち第1図に示したような応答にお
いてh1の値でサンプリング位相を制御すること
が、相関符号を用いない通常の伝送系においてど
のようなことに対応するかを考えてみる。クラス
4パーシヤルレスポンスは送信側で(1、0、−
1)の応答を持つフイルタと通常のナイキストフ
イルタを組合わせて第1図のような相関のある応
答を作るか、符号系列に相関の操作、即ち、bo
=ao−ao-2を施して、このboの系列を通常の
相関のない伝送系に通す形で実現される。今、相
関のない伝送系のインパルス応答のサンプル値を
{Pi}とする。(伝送路歪がなく理想的なサンプ
ル時点ではP0=1、Pi=0(i≠0のとき)
と、hiはPiとPi-2の差で表わされるから hi=P1−P-1 であり、本発明の如く、h1→0にサンプリング位
相を制御することは従来よく用いられるインパル
ス応答ピークの両側のサンプル値を平衡させ対称
点を見出す方法と同様の性質を持つことがわか
る。
As shown in Figure 1, the value of h 1 takes a negative value when the sampling phase is slow, and takes a positive value when the sampling phase is fast, so the point where h 1 crosses zero is the optimal sampling phase. I know what will happen.
Therefore, this o can be used as sampling phase control information, and according to this method, control can be performed only with information for each data transmission interval T seconds. What does controlling the sampling phase with the value of h1 in the impulse response of a class 4 partial response, that is, the response shown in Figure 1, correspond to in a normal transmission system that does not use a correlation code? Let's think about it. Class 4 partial responses are (1, 0, -
Either a filter with response 1) and a normal Nyquist filter are combined to create a correlated response as shown in Figure 1, or a correlation operation is applied to the code sequence, i.e., b o
=a o -a o-2 , and this sequence of b o is passed through a normal uncorrelated transmission system. Now, suppose that the sample value of the impulse response of the uncorrelated transmission system is {P i }. (At the ideal sampling point with no transmission path distortion, P 0 = 1, P i = 0 (when i≠0)
Since h i is expressed as the difference between P i and P i -2 , h i = P 1 - P -1 , and controlling the sampling phase to h 1 → 0 as in the present invention has been commonly used in the past. It can be seen that this method has similar properties to the method of finding a point of symmetry by balancing the sample values on both sides of the impulse response peak.

なお前述の逆変換は誤りが起ると次々に伝播す
る性質を持つているが、これは不定々数Cが誤り
対応して一定値だけ増減するだけであり、誤りの
頻度が著しく高くなければ相関値Roをバイアス
することはない。
Note that the above-mentioned inverse transformation has the property that when an error occurs, it propagates one after another, but this only means that the indeterminate number C increases or decreases by a constant value in response to the error, and unless the frequency of errors is extremely high, The correlation value Ro is not biased.

以下、本発明の実施例を第2図にしたがつて説
明する。
Embodiments of the present invention will be described below with reference to FIG.

端子1より入来するベースバンド信号は線路2
を流れサンプリングクロツクにより制御されるサ
ンプラー3でT秒毎にサンプルされる。サンプル
された系列は、レベル判定器4でao−ao-2の推
定値に対応するレベルが判定され線路5に判定結
果が出力される。線路5の判定結果は2つに分岐
し一方は、パーシヤルレスポンス逆変換器6で逆
変換されaoの推定値が得られる。aoの推定値は
遅延素子7でT秒遅延され、遅延されたaoの推
定値は乗算器8において前記サンプラーの出力信
号と乗算され乗算結果は積分器9で積分される。
積分器出力はパーシヤルレスポンスインパルス応
答h1の推定値に対応し、この値によりデイジタル
位相ロツクループ10が制御され、線路2に位相
制御されたサンプリングクロツクが得られる。2
つに分岐した判定結果の他方は復号器11で復号
され、送信データ推定値が端子12に出力され
る。
The baseband signal coming from terminal 1 is on line 2
The current flow is sampled every T seconds by a sampler 3 controlled by a sampling clock. A level determiner 4 determines the level of the sampled sequence corresponding to the estimated value of a o -a o-2, and outputs the determination result to a line 5. The determination result for the line 5 is branched into two parts, and one part is inversely transformed by a partial response inverse transformer 6 to obtain an estimated value of ao . The estimated value of a o is delayed by T seconds in a delay element 7, the delayed estimated value of a o is multiplied by the output signal of the sampler in a multiplier 8, and the multiplication result is integrated in an integrator 9.
The integrator output corresponds to an estimate of the partial response impulse response h1 , which controls the digital phase lock loop 10 to provide a phase controlled sampling clock on line 2. 2
The other of the branched judgment results is decoded by the decoder 11, and the transmission data estimated value is output to the terminal 12.

前記逆変換器は加算器13と2T秒遅延素子1
4とで構成され、逆変換器入力は遅延素子14の
出力と加算器13で加算され、加算結果は逆変換
器出力となると同時に遅延素子14にフイードバ
ツクされ、積分形の逆変換を行なう。
The inverse converter includes an adder 13 and a 2T second delay element 1.
4, the inverse transformer input is added to the output of the delay element 14 in the adder 13, and the addition result becomes the inverse transformer output and simultaneously fed back to the delay element 14 to perform integral type inverse transform.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はクラス4パーシヤルレスポンスのイン
パルス応答を示す図、第2図は本発明の実施例を
示すブロツク図で、図中3はサンプラー、4はレ
ベル判定器、6は逆変換器、7および14は遅延
素子、8は乗算器、9は積分器、10はデイジタ
ル位相ロツクループ、13は加算器である。
Fig. 1 is a diagram showing an impulse response of a class 4 partial response, and Fig. 2 is a block diagram showing an embodiment of the present invention. 14 is a delay element, 8 is a multiplier, 9 is an integrator, 10 is a digital phase lock loop, and 13 is an adder.

Claims (1)

【特許請求の範囲】[Claims] 1 クラス4パーシヤルレスポンスを用いたデー
タ伝送受信機において、受信ベースバンド信号を
サンプルする手段と、そのサンプルされた信号の
レベル判定を行なう手段と、そのレベル判定結果
にクラス4パーシヤルレスポンス逆変換を施す手
段と、その逆変換結果をデータ送信間隔Tだけ遅
延する手段と、その遅延された逆変換結果と前記
サンプルされた信号とを乗算する手段と、その乗
算結果を積分する手段と、その積分結果により前
記サンプラーに供給するサンプリングクロツクの
位相を制御する手段とを備えたことを特徴とする
サンプリング位相制御装置。
1. In a data transmission receiver using class 4 partial response, means for sampling a received baseband signal, means for determining the level of the sampled signal, and inverse transformation of the class 4 partial response for the level determination result. means for delaying the inverse transform result by a data transmission interval T; means for multiplying the delayed inverse transform result by the sampled signal; and means for integrating the multiplication result; A sampling phase control device comprising means for controlling the phase of a sampling clock supplied to the sampler based on the integration result.
JP9888478A 1978-08-14 1978-08-14 Sampling phase control unit Granted JPS5525296A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9888478A JPS5525296A (en) 1978-08-14 1978-08-14 Sampling phase control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9888478A JPS5525296A (en) 1978-08-14 1978-08-14 Sampling phase control unit

Publications (2)

Publication Number Publication Date
JPS5525296A JPS5525296A (en) 1980-02-22
JPS6158065B2 true JPS6158065B2 (en) 1986-12-10

Family

ID=14231564

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9888478A Granted JPS5525296A (en) 1978-08-14 1978-08-14 Sampling phase control unit

Country Status (1)

Country Link
JP (1) JPS5525296A (en)

Also Published As

Publication number Publication date
JPS5525296A (en) 1980-02-22

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