JPH0846658A - Burst signal demodulation circuit - Google Patents

Abstract

PURPOSE:To provide the burst signal demodulation circuit using a preamble for carrier recovery and clock recovery in common to reduce the preamble. CONSTITUTION:As a preamble in common to carrier recovery and clock recovery, 1001, 0110, 1100 or repetition of 0011 are used. A received input is applied to an orthogonal detection circuit 10 and a sample circuit 11, from which a sampled value (CA) is outputted. Correlation (C, S) of a cosine and a sine signal with the same frequency as that of the sampled value (CA) and the preamble signal is obtained. A carrier phase estimate circuit 30 obtains a carrier phase estimate signal (U) from the correlation (C, S) and a detection circuit 14 provides a demodulation signal (E) based on the multiplication between the signal (U) and the sampled value (CA). A clock signal (F) applied to the sample circuit 11 is obtained from the correlation (C, S) by a clock recovery circuit 40.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a burst signal demodulation circuit used in digital radio communication.

[0002]

2. Description of the Related Art The structure of a conventional burst signal demodulation circuit is shown in FIG. The burst signal demodulation circuit is a quadrature detection circuit 1
0, a sample circuit 11, a carrier recovery circuit 12, a clock recovery circuit 13 and a detection circuit 14. Further, the burst signal has a carrier reproduction preamble section 1, a clock reproduction preamble section 2, as shown in FIG.
Further, it comprises a data section 3. In FIG. 1, a received input signal A is converted by a quadrature detection circuit 10 into a complex signal B having I and Q channel components orthogonal to each other. The complex signal B is sampled by the sampling circuit 11 at the timing of the clock signal F supplied from the clock reproduction signal, and the sampled complex signal C is input to the carrier reproduction circuit 12 and the detection circuit 14. The deviation (clock phase) from the identification point of the clock signal F has a random value before the clock reproduction. The carrier reproduction circuit 12 performs carrier reproduction based on the carrier reproduction preamble included in the complex signal C. The carrier reproduction preamble to be used is a bit sequence in which all are not modulated and is "1", and the carrier reproduction circuit 12 reproduces the carrier signal D (phase difference between the reference carrier signal and the carrier reproduction circuit output) regardless of the clock phase. Ask for.
The reproduced carrier signal D is input to the detection circuit 14. The detection circuit 14 uses the reproduced carrier signal D to sample the sample circuit 1.
The carrier phase error is removed from the complex signal C supplied from No. 1 and the result is output as the signal E after carrier reproduction. The clock regeneration circuit 13 inputs the signal E after carrier regeneration and performs clock regeneration using the clock regeneration preamble included in the signal E. The clock recovery circuit 13 estimates and corrects the clock phase from the signal E, and supplies the result as a recovered clock signal F to the sampling circuit 14. After that, the signal E output from the detection circuit 14 becomes a demodulated signal after carrier recovery and clock recovery.

[0003]

By the way, in the above-mentioned conventional burst signal demodulation circuit, in order to perform carrier reproduction and clock reproduction, a burst signal structure using individual preambles for carrier reproduction and clock reproduction is adopted, and Carrier reproduction and clock reproduction were sequentially performed using the preamble. In this case, the preamble length becomes long and the information transmission efficiency deteriorates.

The present invention has been made to solve such problems, and it is possible to shorten the preamble by sharing the preamble for carrier reproduction and clock reproduction and simultaneously performing carrier reproduction and clock reproduction. An object is to provide a burst signal demodulation circuit.

[0005]

SUMMARY OF THE INVENTION The present invention relates to digital phase modulation 1001, 0110, 1100, 0011.
, A quadrature detection circuit for converting the input signal into a complex signal having an I channel component and a Q channel component which are orthogonal to each other, and a timing of a sample clock. A sampling circuit for sampling the complex signal twice or more per symbol, a correlation calculation circuit for calculating a correlation between a sampled preamble signal of the burst signal and a cosine and a sine having the same frequency component for a certain period, and the correlation A carrier phase estimation circuit that estimates a carrier phase and outputs a carrier phase estimation signal for an arbitrary carrier phase and a clock phase by using the two systems of signals output from the calculation circuit, and based on the carrier phase estimation signal. The carrier level from the output of the sample circuit A detection circuit that removes an error, a clock phase estimation circuit that estimates a clock phase based on the output of the correlation calculation circuit at the same time as the carrier estimation, and a phase of the sample clock is corrected based on the output of the clock phase estimation circuit. And a clock recovery circuit having a timing correction circuit for

[0006]

In the present invention, the carrier estimation circuit can reproduce the carrier without being influenced by the clock phase, and at the same time, the clock can be reproduced without being influenced by the carrier phase error, so that the preamble included in the burst signal is included. Can share signals.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure and burst signal format of a burst signal demodulation circuit according to the present invention are shown in FIGS. An example will be described in which a repetitive bit sequence of 1001, 0110, 1100, or 0011 is used as a preamble signal shared for carrier reproduction and clock reproduction, and QPSK modulation is performed on this preamble signal.

In FIG. 3, the received signal A is input to the quadrature detection circuit 10 and the I channel component and Q which are orthogonal to each other.
It is converted into a complex signal B divided into channel components. The complex signal B is sampled by the clock signal F in the sampling circuit 11 at a sampling rate of 2 [samples / symbol] to obtain a complex signal CA. Here, the clock signal F has an arbitrary clock phase before clock reproduction. FIG. 5 shows a signal space diagram when QPSK modulation is performed on the preamble signal. When there is no carrier and clock phase error, the signal point moves on the solid line in FIG. 5 and, as described above, 2 [samples / symbo]
1], the sample points are located at four points A to D. However, when the carrier phase changes by φ, the signal point moves on the broken line, and when the clock phase changes by θ, the sampling points are located at points A ′ to D ′.

When the carrier phase changes by φ and the clock phase changes by θ, the I channel component and the Q channel component (X _k ,
Y _k ) is given by the equation (1). Furthermore, (X _k , Y
_k ) and N _S [symbol] (N _S : preamble length), the correlation signal C of cos ωt _k and sin ωt _k
(C _I , C _Q ) and S (S _I , S _Q ) are given by equations (2) and (3).

[0010]

[Equation 1]

In the correlation calculation circuit 20, the above (2) and (3)
Compute the complex signal of an expression.

The above two signals C and S from the correlation calculating circuit 20 are simultaneously supplied to the carrier phase estimating circuit 30 and the clock reproducing circuit 40.

The carrier phase estimation circuit 30 compares the absolute values of C and S, and if the absolute value of the correlation signal C is larger, the sign of the correlation signal S is adjusted to the sign of the correlation signal C. On the contrary, when the absolute value of the correlation signal S is larger, the operation of matching the sign of the correlation signal C with the sign of the correlation signal S is performed, and the I channel components of the correlation signals C and S and the Q channel components of the correlation signals S are The carrier phase φ is calculated by using the signal obtained by summing the above as the carrier phase estimation signal U (Xφ, Yφ). (Xφ, Yφ) is calculated as follows depending on the case.

(When C is large) (Xφ, Yφ) = {C _I + sign [C _I ] · | S _I |, C _Q + sign [C _Q ] · | S _Q |} (4) (S is large Case) (Xφ, Yφ) = {S _I + sign [S _I ] · | C _I |, S _Q + sign [S _Q ] · | C _Q |} (5) where | C | = | S | Uses the above formula (4) or (5).

The carrier phase estimation signal is detected by the detection circuit 14
Is input to

For example, in FIG. 7, when the correlation signal C is the vector C, the correlation signal S is the vector S, and the carrier phase estimation signal is the vector U, the absolute values of the vector C and the vector S are compared. Is large,
The vector U is given by the above equation (4).

The clock reproduction circuit 40 comprises a clock phase estimation circuit 50 and a timing correction circuit 60. In the clock estimation circuit 50, the respective I channel components (C _I and S _I ) of the correlation calculation signal outputs C and S of the above equations (2) and (3) and Q
The absolute values of the four components of the channel components (C _Q and S _Q ) are compared and the maximum component is extracted. The components C _I and C _Q and the S _I are added so that the maximum component becomes larger.
The sum or difference components and S _Q component are calculated, the component C _I and C _Q the sum or difference I channel component of components, the S _I component and S _Q component clock phases the sum or difference and Q channel components of The estimated signal V (Xθ, Yθ) is obtained, and (Xθ, Y
θ) is estimated. Clock phase estimation circuit 50
Then, the following calculation is performed according to the maximum component.

(When C _I is maximum) (Xθ, Yθ) = {C _I + sign [C _I ] · | C _Q |, S _I + sign [C _I · C _Q ] · | S _Q |} (6 ) (When C _Q is maximum) (Xθ, Yθ) = {C _Q + sign [C _Q ] · | C _I |, S _Q + sign [C _I · C _Q ] · | S _I |} (7) ( (When S _I is maximum) (Xθ, Yθ) = {C _I + sign [S _I · S _Q ] · | C _Q |, S _I + sign [S _I ] · | S _Q |} (8) (S _Q Is the maximum) (Xθ, Yθ) = {C _Q + sign [S _I · S _Q ] · | C _I |, S _Q + sign [S _Q ] · | S _I |} (9)

The timing correction circuit 60 corrects the timing of the reproduced clock signal F to a desired timing based on the clock phase estimation signal V and outputs it to the sampling circuit 11.

For example, in FIG. 8, assuming that the correlation signal C is the vector C, the correlation signal S is the vector S, and the clock phase estimation signal is the vector V, the absolute values of the components of the vector C and the vector S are compared. Since the I channel component (C _I ) of the vector becomes maximum, the vector V becomes (6) above.
It is given by the formula.

As described above, the carrier phase estimation circuit 30
And the clock recovery circuit 40 simultaneously performs carrier recovery and clock recovery using the shared preamble 4 of the supplied complex signal C. After that, the signal E output from the detection circuit 14 becomes a demodulated signal after carrier reproduction and clock reproduction. When there is a carrier frequency error, the broken line 90 in FIG.
The carrier phase shift can be corrected by the conventional carrier reproducing circuit 12a (for example, an inverse modulation type carrier reproducing circuit or the like). It is to be noted that reference numeral 92 gives an initial value to the carrier reproducing circuit 12a when switching to the data section. After switching to the data section, the output U of the carrier estimation circuit 30 is not given to the detection circuit 14.

[0022]

As described above, according to the present invention, the preamble used for the carrier reproduction and the clock reproduction can be shared, so that the preamble length can be shortened and the information transmission efficiency can be improved.

FIG. 6 is an example showing the effect of the present invention. Here, the modulation method is QPSK, the root roll-off rate of the waveform shaping filter is 0.5, the data length of the burst signal is 1000 [symbol], and the preamble length is a parameter. As a result, the preamble length is 10
If [symbol], required Eb / No from theoretical value
The deterioration amount can be suppressed to about 0.1 [dB].

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a conventional burst signal demodulation circuit.

FIG. 2 is a diagram showing a format of a conventional burst signal.

FIG. 3 is a block diagram showing a configuration of a burst signal demodulation circuit according to an embodiment of the present invention.

FIG. 4 is a diagram showing a format of a burst signal according to an embodiment of the present invention.

FIG. 5 is a signal space diagram [preamble part] in QPSK modulation according to an embodiment of the present invention.

FIG. 6 is a diagram showing an example of the effect of the present invention.

FIG. 7 is a diagram illustrating carrier phase estimation according to the present invention.

FIG. 8 is a diagram illustrating clock phase estimation according to the present invention.

[Explanation of symbols]

 10 quadrature detection circuit 11 sample circuit 12 carrier recovery circuit 13 and 40 clock recovery circuit 14 detection circuit 20 correlation calculation circuit 30 carrier phase estimation circuit 50 clock phase estimation circuit 51 timing correction circuit

Claims (1)

[Claims] 1. In digital phase modulation, a burst signal having a preamble part and a data part having a repetitive bit sequence of 1001, 0110, 1100 or 0011 is used as an input signal, and the input signal is orthogonal to the I channel component and the Q channel. A quadrature detection circuit for converting a complex signal having a component, a sampling circuit for sampling the complex signal at least twice per symbol at the timing of a sample clock, and a cosine having the same frequency component as the sampled preamble signal of the burst signal And a sine for a certain period of time, a correlation calculation circuit for calculating a correlation and a two-system signal output from the correlation calculation circuit, with respect to an arbitrary carrier phase and clock phase,
A carrier phase estimation circuit that estimates a carrier phase and outputs a carrier phase estimation signal, a detection circuit that removes a carrier phase error from the output of the sample circuit based on the carrier phase estimation signal, and the carrier estimation and the correlation at the same time. A clock phase estimating circuit for estimating a clock phase based on the output of the calculating circuit; and a clock regenerating circuit having a timing correcting circuit for correcting the phase of the sample clock based on the output of the clock phase estimating circuit. Burst signal demodulation circuit.