JP3086144B2 - Burst demodulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an offset QP
More particularly, the present invention relates to a burst demodulator for receiving and demodulating an SK-modulated burst signal, and in particular, receives a preamble signal composed of a non-modulated signal (CW signal) and a bit timing recovery signal (BTR signal) to perform carrier wave reproduction and bit timing reproduction. Pertaining to a burst demodulator to perform.

[0002]

2. Description of the Related Art When transmitting a burst signal subjected to offset QPSK modulation, for example, a preamble signal including a CW signal and a BTR signal is added to a burst signal to be transmitted. On the receiving side, the arrival of the burst signal is detected as the arrival of a preamble signal, especially a CW signal (burst detection), and a carrier is reproduced from the CW signal. When the carrier is reproduced, the local oscillation frequency used in the quadrature detector or the like on the receiving side is corrected according to the reproduction result. On the receiving side, the arrival timing (BTR position) of the BTR signal is further detected, and the receiving clock (clock for A / D conversion of the output of the quadrature detector) with respect to the transmitting clock is detected.
To compensate for the timing shift.

[0003]

The processing relating to the carrier frequency offset estimation and the clock timing estimation is as follows.
It must be completed in a short time while receiving the preamble signal. In order to terminate the carrier frequency offset in the preamble period, a process of obtaining power by DFT (Discrete Fourier Transform) or the like must be performed for several tens to several hundreds of frequency points, and large-scale hardware is required. In addition, in order to end the clock timing estimation in the preamble period, high-speed sampling must be performed at a speed that is ten and several times the symbol rate, resulting in an increase in power consumption and a difficulty in circuit configuration.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and the power is detected for several tens to several hundreds of frequency points by updating the frequency points for detecting the power. An object of the present invention is to make it possible to estimate a carrier frequency offset without finding it, and to reduce the hardware scale. Another object of the present invention is to make it possible to estimate clock timing without performing high-speed sampling by performing rough estimation and threshold value determination by focusing on the specification of a BTR signal, thereby realizing reduction of power consumption and the like. With the goal.

[0005]

In order to achieve such an object, a clock timing shift time estimating method according to the present invention is provided.
Preamble on the burst modulated phase modulated signal
Signal is added as a signal and its value is
Of the BTR signal that changes alternately in synchronization with the receiving clock
Detecting the arrival and synchronizing with the receiving clock
BTR signal value in one symbol interval at timing
Power index values indicating the change of power and the plurality of power values
Step for obtaining a magnitude relation index value indicating the magnitude relation between index values
And the timing at which the value of the BTR signal changes
-Rough estimation by comparing index values and transmission
The deviation of the receiving clock with respect to the receiving clock is roughly estimated.
Based on the obtained timing and the above-mentioned magnitude relation index value.
And a step of determining

Also, the burst demodulator of the present invention has
The CW signal and the subsequent BTR signal
Receives and demodulates the phase-modulated signal including burst transmission
In the burst demodulator, the received signal is
Means for quadrature detection of signals and sampling
Receive signal that has been quadrature detected while
Means for sampling the signal and outputting it as demodulated data;
Divide the frequency range to which the frequency that the carrier can take belongs
Calculate signal power for each of multiple available bands
If the calculated signal power satisfies the specified conditions,
Means for determining that a received signal has arrived,
Based on the behavior, the detected burst signal is a CW signal
Means for determining whether or not the signal is a CW signal.
The frequency offset of the local signal with respect to the carrier.
Estimate and match the carrier frequency based on the result
Means for controlling the frequency of the local signal, and
Execute the clock timing lag time estimation method and
Based on the result, the receiving side clock is set to match the transmitting side clock.
Means for controlling the timing of the clock .

The burst demodulator according to the present invention further comprises
The frequency offset of the local signal with respect to the carrier
Estimate and control the frequency of the local signal based on the result
The frequency range to which the carrier can take
Signal at each of the multiple frequency points
Signal power according to the detection of the arrival of the unmodulated signal, and
Select the frequency point where the signal power is maximum, and
Within the frequency range that includes the wave point and is narrower than before,
More frequency points to find signal power
The operation of setting at narrow intervals is performed when the interval between frequency points is
Repeat until the interval is equivalent to the wave number accuracy.
The frequency at which the maximum signal power was obtained at the
It is characterized in that several points are determined to be carrier frequencies .

[0008]

According to the present invention, a method for estimating a clock timing deviation time according to the present invention is provided.
First, the arrival of the BTR signal is detected. Next
In addition, during one symbol interval, the value (of each component) of the BTR signal is
Several power index values to show how much
A magnitude relation index value that indicates the magnitude relation of multiple power index values
Is obtained at a timing synchronized with the receiving clock.
You. The value of the BTR signal is
Since the signal changes alternately in synchronization with the lock,
The timing at which the value of the BTR signal changes depends on the power index.
A rough estimation can be made by comparing the values. further,
By using the magnitude relation index value, the
To see how the values of
Processing such as threshold value judgment for the magnitude relation index value
And correct the rough estimation result based on the result.
The deviation of the receiving clock from the transmitting clock
Can be known with higher accuracy. Resulting
The timing of the receiving clock is adjusted according to the timing deviation.
By correcting, the receiving clock relative to the transmitting clock
Lock timing deviation can be compensated. Ma
The sampler required to perform this method
At most, the BTR signal is
How much the value (for each component) has changed
Rate, for example, about twice the symbol rate.
, High-speed sampling such as ten and several times the symbol rate
Clock timing can be estimated without performing
As a result, power consumption can be reduced.

In the burst demodulator of the present invention ,
The received signal is quadrature detected and the quadrature detected
Is sampled and the result is output as demodulated data
Is done. Next, the frequency to which the possible frequency of the carrier belongs
A process is performed to divide the range into bands and obtain the signal power.
You. If the obtained signal power satisfies the specified conditions,
If the threshold is exceeded, a burst signal
Is determined. After detecting the arrival of the burst signal,
Number offset estimation and clock timing deviation time estimation
The local signal frequency and reception depending on the result.
The timing of the receiving clock is controlled. However, berth
High amplitude noise was detected as the
Or a modulated signal with a missing preamble signal.
Frequency offset estimation and
Clock timing lag time estimation is based on the detected burst
Executed only when the signal is a CW signal. Therefore,
In this burst demodulator, the above-described operation occurs.
In addition, noise and modulation signals are detected as burst signals
Therefore, a malfunction due to this is suitably prevented.

[0010] In the burst demodulator of the present invention, the estimation of the frequency offset is preferably performed as follows.
Follow the method. First, the frequencies that the carrier can take
A plurality of frequency points are initially set within a frequency range to be set.
Then, the signal power at each of these multiple frequency points is
Is calculated according to the detection of the arrival of the unmodulated signal, and the obtained signal power is obtained.
Select the frequency point at which the maximum is reached. Selected frequency point
Is considered closer to the carrier frequency than the other frequency points.
Can be In addition, the selected frequency points are included and
Find signal power within a narrower frequency range
Set multiple frequency points at smaller intervals
You. From the derivation of the signal power to the setting of the frequency point
Is performed when the interval between frequency points corresponds to the predetermined frequency accuracy.
Repeat until the interval is reached. And finish this repetition
The frequency point at which the maximum signal power was obtained at the time
It can be estimated to be the frequency of the carrier. Therefore, the present invention
In all cases, the carrier frequency covers all possible frequency ranges.
To calculate the signal power
Frequency points to be calculated can be reduced, and hardware
AThe scale can be reduced.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a burst demodulator according to one embodiment of the present invention. The demodulator shown in this figure is a demodulator that receives and demodulates an offset QPSK modulated wave transmitted in bursts.

The burst demodulator shown in FIG. 1 includes a quadrature detector 1 for quadrature detecting an input signal using a local signal supplied from a local oscillator 9. Quadrature detector 1
Is sampled by an analog-to-digital (A / D) converter 2 and supplied to each subsequent circuit. What
The delay detection described later provided at the input of each circuit
The bowl can be shared. Since the sampling clock has a frequency that is twice the symbol frequency, two sample data are obtained during one symbol period. In the following description,
The data obtained first among them is called even data, and the data obtained next is called odd data.

When a burst signal arrives, A / D
A demodulation result is obtained from converter 2. The burst signal has, for example, a configuration as shown in FIG.
In this figure, a preamble signal composed of a CW signal and a BTR signal is transmitted prior to transmission of a unique word (UW) or data.

The output of the A / D converter 2 is supplied to a circuit (not shown), and also to a burst detector 3 for controlling the frequency of a local signal and controlling the timing of a sampling clock. As shown in FIG. 3, the burst detection unit 3 has N bursts allocated to different frequency bands.
(N: integer of 2 or more) band power calculator / comparator 1
1 is comprised. When assigning a frequency band to the N band power calculation / comparators 11, first, it is assumed how much the carrier frequency of the signal input to the quadrature detector 1 can be offset, and the assumed frequency offset range Is divided into N bands, and individual frequency bands obtained by the division are assigned to the respective band power calculators / comparators 11.

Each band power calculator / comparator 11 has the configuration shown in FIG.
, The complex multiplier 21, the moving average adder 2
2. It is composed of a power calculator 23 and a comparator 24. The complex multiplier 21 performs complex rotation on the signal supplied from the A / D conversion unit 2 so that the assigned frequency band shifts in frequency to near DC. Moving average adder 2
2 performs a moving average of the frequency-shifted signal over M samples (M: an integer of 2 or more), thereby removing high-frequency noise and the like. The power calculator 23 obtains signal power (band power) existing in the assigned frequency band by squaring the moving average value. The comparator 24 is
By comparing the band power with a predetermined threshold value, it is determined whether or not the band power has increased to a predetermined value or more. If the determination is satisfied, a burst detection signal is output.

[0017] If the burst detection signal is output by at least one of the N are provided band power calculation and comparator 11, regarded as a burst signal arrives. Therefore, a value obtained by multiplying a band power value by a constant g in a state where only noise is input to the quadrature detector 1 is set in advance as the threshold value used in the comparator 24. Normally, a CW signal arrives before a modulated wave, so that a burst detection signal is generated by the arrival of a CW signal. However, when a preamble is missing, a burst detection signal is generated by the arrival of a modulated wave. Also outputs burst detection signal.
There is only one band power calculator / comparator 11
When the burst signal arrives,
May be added.

As shown in FIG. 1, the burst detector 3
In the subsequent stage, a CW determination unit 4 and a buffer memory 5 are provided. The CW determination unit 4 determines whether or not the burst signal detected by the burst detection unit 3 is a CW signal. By providing a CW determination unit 4 and performing frequency offset estimation and the like only when a CW signal arrives, even if a modulated wave or noise with a large amplitude is detected as a burst signal, erroneous estimation in subsequent processing is prevented. can do. The buffer memory 5 stores data over, for example, R symbols during CW determination (R: an integer of 2 or more) so that the subsequent-stage frequency offset estimating unit 6 can appropriately execute processing. By using the buffer memory 5, the preamble signal arrival period, which continues only for a short time, can be effectively used.

FIG. 5 shows the configuration of the CW determination unit 4. As shown in this figure, the CW determination unit 4 has a delay detector 31. The delay detector 31 performs delay detection on the sampling result obtained by the A / D converter 2, and among the results, the I channel (even-phase component) of the even data.
Adding cumulative delay detection value _{e I} 32 and the power calculator 36
And supplies the I-channel (in-phase component) differential detection value o _I of the odd data to the accumulator 34 and the power calculator 36.

The cumulative adder 32 cumulatively adds across the _{e I} to m samples. The accumulator 34 accumulatively adds o _I over m samples.累積_{m is the} cumulative addition over m samples.
When be represented by, those obtained by the cumulative adder 32 is sigma _m e _I, the obtained by the cumulative adder 34 is a sigma _m o _I. Power calculator 33 by squaring the sigma _m e _I seek (Σ _m e _I) ^2, a power calculator 35
Finds the (Σ _m o _I) ² by squaring the sigma _m o _I. For comparator 38, both the sum of (Σ _m e _I) ² +
(Σ _m o _I) ² comparator input signal 39 indicating a is supplied. The delayed detection values e _I and o _I tend to be biased toward positive values when the CW signal arrives, but tend to change randomly when a modulated wave or noise arrives, so the value of the comparator input signal 39 ( ^{_{Σ m e I) 2 + (}} Σ m o I) 2 is,
When the CW signal arrives, the value becomes large.

On the other hand, the power calculator 36 calculates the power e _I ² + o of the differential detection value of the I channel value over one symbol period.
Determine the _I ^2. The accumulator 37 calculates e _I ² + o _I ² by m
Cumulative addition is performed over the samples, and the obtained cumulative addition value Σ _m
The comparator input signal 40 indicating (e _I ² + o _I ² ) is supplied to the comparator 38. The value of e _I ² + o _I ² does not depend on whether the incoming signal is a CW signal.

Therefore, when the burst detection signal is generated in response to the arrival of the CW signal, the comparator input signal 39 becomes relatively larger than the comparator input signal 40, and conversely, the CW signal
If the burst detection signal is generated in response to the arrival of a modulated wave or noise having a large amplitude instead of the arrival of a signal, for example,
The value of the comparator input signal 40 becomes larger than the value of the comparator input signal 39. Therefore, the comparator 38 calculates β · | using predetermined scaling factors α and β.
^{_{(Σ m e I) 2 +}} (Σ m o I) 2 -α · Σ m (e I 2 +
o _I ²⁾ | is calculated and the result (Σ _m e _I) ² +
(Σ _m o _I) is smaller than ^2, the incoming to that signal C
It is determined that the signal is a W signal. If it is determined that the signal is a CW signal, the comparator 38 outputs a CW identification signal.

When the CW identification signal is output, data corresponding to R symbols in the buffer memory 5 is input to the frequency offset estimator 6 shown in FIG.
The frequency offset estimating unit 6 calculates the frequency offset d at coarse and uniform frequency intervals W over the range of the assumed frequency offset.
(D: an integer of 2 or more) frequency points (see FIG. 6) are set, and D is added to the input data for the set frequency points.
FT processing is performed, and a frequency point F (0) at which the maximum power is obtained as a result is detected. Frequency offset estimator 6
Is centered on the frequency point F (0) at which the maximum power is obtained,
The same processing is executed after narrowing the frequency range for setting the frequency point related to DFT. For example, in addition to the frequency point F (0) for which the power has been calculated, F (0) -W / 2 and F (0)
Set a total of three frequency points by adding two points of + W / 2,
For the set frequency point, DFT is applied to the input data.
Processing is performed, and the frequency point F (1) at which the maximum power is obtained as a result is detected. By repeating this until a predetermined frequency accuracy is obtained, the frequency having the maximum power, that is, the frequency offset can be estimated precisely. Also, F (0), F (0) -W / 2 and F
Since the power is calculated for three points (0) + W / 2, the hardware scale can be minimized. Note that the present invention is not limited to such set points and intervals. Frequency offset estimator 6
Feeds back the frequency offset thus obtained to the local oscillator 9. The oscillation frequency of the local oscillator 9 is modified accordingly to match the carrier frequency.

A BTR position detecting section 7 provided at a stage subsequent to the frequency offset estimating section 6 detects a boundary between the CW signal and the BTR signal, that is, a start timing of the BTR signal. Determine the timing. Since the offset QPSK is assumed here, the BTR signal has the signal position (I, Q) = (-1, 1) and the signal position (I, Q) =, as shown in FIG.
(-1, -1) are signals alternately taken every other symbol.

FIG. 8 shows the configuration of the BTR position detecting section 7. The BTR position detection unit 7 in FIG.
It has a delay detector 41 that performs delay detection on data and odd data. The e _I moving average adder 42 of the delay detection output of the differential detector 41, o _I is the moving average adder 44 is supplied. Delay detector 41
The delayed Q-channel signal output e _Q of even data of the detection output moving average adder 46, the Q-channel signal output o _Q of odd data to the moving average adder 48, after being multiplied by -1 for each symbol , Respectively. The moving average adders 42, 44, 46 and 48 perform a moving average of the supplied signal over k samples (k: an integer of 2 or more),
Removes high frequency noise.

Power calculators 43, 45, 47 and 49
Are the corresponding moving average adders 42, 44, 46 or 48
By squaring the moving average value obtained by
The power is determined for each of d and even and each of the I channel and the Q channel. The comparator input signal 51 input to the comparator 50 at the subsequent stage is a value obtained by adding the result of the calculation by the power calculator 43 and the result of the calculation by the power calculator 45, and is (Σ _{ke I} ) ² + ( it represents the Σ _k o _I) ^2. Another comparator input signal 52 input to the comparator 50 is a value obtained by adding the result of the calculation by the power calculator 47 and the result of the calculation by the power calculator 49.
_k (−1) ^ke _Q ) ² + (Σ _k (−1) ^k o _Q ) ² .

Therefore, the comparator input signal 51 takes a large value when the CW signal arrives, and the comparator input signal 52 takes a large value when the BTR signal arrives. The latter is due to the fact that the Q channel signal amplitude at the time of arrival of the BTR signal becomes a sine wave amplitude having one cycle of two symbols. The comparator 50 detects a transition from the CW signal to the BTR signal by comparing the comparator input signals 51 and 52. More specifically, the comparator 50 performs scaling using a predetermined scaling factor γ,

## EQU1 ## γ ｛(Σ _k (−1) ^ke _Q ) ² + (Σ _k (−
1) At the time when ^k o _Q ) ² ｝> (Σ _{ke I} ) ² + (Σ _k o _I ) ² is satisfied, a BTR detection signal is output to the BTR phase estimating section 8.

FIG. 9 shows the configuration of the BTR phase estimating section 8. The BTR phase estimating unit 8 includes a delay detector 61 that performs delay detection on both even data and odd data. On differential detector 61 is multiplied by -1 every other symbol, the _{e Q} in the cumulative adder _62, the e Q + _{o Q} in the accumulator 64, the _{o Q} in the accumulator _66, o Q -e _Q is supplied to each of the accumulators 68. Cumulative adder 6
2, 64, 66 and 68 accumulate the supplied signals over b samples (b: an integer of 2 or more). The obtained cumulative addition value is stored in the corresponding power calculator 63, 65, 6
Squared by 7 or 69. The result is input to the comparator 70 as comparator input signals 71 to 74 after the outputs of the power calculators 63 and 67 are multiplied by 、 and the outputs of the power calculators 65 and 69 are multiplied by ２. You.

Therefore, the value R ₁ of the comparator input signal 71 becomes { _j (-1) ^je _Q } ² , and the comparator input signal 72
The value ^{_{R 2 {Σ j (-1)}} j (e Q + o Q)} 2/2 , and the value _{R 3} of the comparator input signal 73 {Σ ^{_j (-1)} _j
o _Q ｝ ² and the value R ₄ of the comparator input signal 74 becomes ｛Σ _j
^(-1) becomes ^{_{j (o Q -e Q)}}} 2/2. When the BTR signal is detected by delay detection, the amplitude of the Q-channel signal becomes a sine wave. )
On the other hand, R _{1 to} R ₄ change in a tendency as shown in FIG. As is clear from this figure, R ₁ is 0 °,
R ₂ is 90 °, R ₃ is 180 °, and R ₄ is 270 °, which is the maximum. Since R _{1 to} R ₄ have such a behavior, the BTR phase becomes equal to the comparator input signal 71.
The BTR phase can be roughly estimated by detecting which has the largest value among .about.74 and which has the next largest value. That is, as shown in Table 1, the BTR phase can be estimated with a coarse accuracy of ± 45 °. Comparator 70
Performs such a rough estimation.

[0030]

[Table 1] Thus, the rough estimation of the BTR phase (coarse clock estimation)
, The comparator 70 determines the estimation accuracy from ± 45 ° to ± 2
The result is fed back to the A / D converter 2 as a clock timing shift time, and the timing of the sampling clock is corrected so as to match the transmission side.

Specifically, the comparator 70 first determines whether R _{1 to} R ₄
Of the largest value R _max and the next largest value R
Absolute value of _2nd difference

S ₁ = | R _max −R _2nd | and the absolute value of the difference between R _2nd and the next larger value R _3rd

S ₂ = | R _2nd -R _3rd | These difference absolute values S ₁ and S ₂ are shown in FIG.
In each case, the value becomes 0 every 90 °. Also, S ₁ becomes 0 at 45 °, 135 °, 225 °,
Whereas it is 315 °, become a _{S 2} 0 0 °, 9
0 °, 180 °, and 270 °. Therefore, S ₁ and S
_If any of ₂ takes a small value, the BTR phase is 4
It can be considered to have a value near an integral multiple of 5 °. The comparator 70 pays attention to this point, and determines S ₁ and S ₂ as threshold values, respectively. As the threshold, R _{1 to} R
₄ is a constant value because it is a sine wave at equal phase intervals

Equation 4] _{R T = R 1 + R 2} + R 3 + R 4 a constant _C 1, a value multiplied by _{C 2 C} 1 _· R _T, using a C 2 · _{R T.} The comparator 70 corrects the result of the rough estimation according to the result of the threshold value determination. For example, the result BT of the coarse estimation
Assuming that S ₁ <C ₁ · _RT and S ₂ > C ₂ · _RT are obtained as a result of the threshold value determination when the R phase is 67.5 °, the BTR phase is actually Since the value is recognized as being lower than 67.5 °, the comparator 70 outputs 45 ° which is a value obtained by correcting the value of −22.5 ° as the clock timing shift time. In this manner, + 22.5 ° or -2 as appropriate according to the result of the threshold value determination.
By performing the correction of 2.5 °, the estimation accuracy can be improved.

In the above-described configuration, each member performs the delay detection, the cumulative addition, the moving average, the power calculation and other processes. However, hardware or software for executing these processes is possible. It is better to share as much as possible.

[0033]

As described above, according to the clock of the present invention,
According to the timing shift time estimation method, the arrival of the BTR signal
Signal is detected during one symbol interval.
Multiple parameters that show how much the value (for each component)
Power index values and the magnitude relationship between these multiple power index values.
The index value indicating the magnitude relation is synchronized with the receiving clock.
The timing at which the value of the BTR signal changes
Rough estimation by comparing power index values
Using the value to correct the coarse estimation result,
Improved to calculate the deviation of the receiving clock with higher accuracy.
Therefore, at most, during one symbol interval, each component of the BTR signal
Of the value)
The sampling rate, for example, about twice the symbol rate
Only need to sample at the rate, consumption
Reduction of power and the like can be realized.

According to the burst demodulator of the present invention,
The above effects can be obtained, and noise and modulation signals
Malfunction due to detection of
Can be properly prevented.

According to the burst demodulator of the present invention, the signal is transmitted within the frequency range to which the carrier can take a frequency.
Initialize multiple frequency points for which signal power is to be obtained at predetermined intervals
After the arrival of the CW signal is detected,
The signal power at which the maximum signal power was obtained.
Signal within several points and within a narrower frequency range
Narrower frequency points for which power is required
Set at intervals and repeat until the required frequency accuracy is obtained
Carrier frequency can be taken
To calculate signal power for all frequency ranges
Frequency points for calculating signal power
Can be. This can reduce the hardware scale
You.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a burst demodulator according to one embodiment of the present invention.

FIG. 2 is a diagram illustrating an example configuration of a burst signal.

FIG. 3 is a block diagram illustrating an example configuration of a burst detection unit.

FIG. 4 is a block diagram illustrating an example configuration of a band power calculator / comparator.

FIG. 5 is a block diagram illustrating an example configuration of a CW determination unit.

FIG. 6 is a diagram showing an arrangement of frequency points for calculating power by DFT.

FIG. 7 is a diagram illustrating a locus of a modulation vector of a BTR signal subjected to offset QPSK modulation.

FIG. 8 is a block diagram illustrating an example configuration of a BTR position detection unit.

FIG. 9 is a block diagram illustrating an example configuration of a BTR phase estimating unit.

FIG. 10 is a diagram illustrating a behavior of a comparator input signal with respect to a BTR phase when one symbol is a BTR phase of 360 °.

FIG. 11 is a diagram illustrating a behavior of a difference absolute value with respect to a BTR phase.

[Explanation of symbols]

1 quadrature detector, 2 analog-to-digital converter, 3
Burst detection unit, 4CW determination unit, 5 buffer memory,
6 frequency offset estimator, 7 BTR position detector,
8 BTR phase estimator, 9 local oscillator, 11 band power calculator / comparator, 21 complex multiplier, 22, 4
2, 44, 46, 48 Moving average adders, 23, 33,
35, 36, 43, 45, 47, 49, 63, 65, 6
7, 69 Power calculator, 24, 38, 50, 70 Comparator, 31, 41, 61 Delay detector, 32, 34, 3
7, 62, 64, 66, 68 Cumulative adder, 39, 4
0, 51, 52, 71-74 Comparator input signal.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 27/00-27/38 H04L 7/00

Claims (3)

(57) [Claims] 1. A method in which a burst modulated phase modulated signal is pre-
It is added as an amble signal and its value
Bit that changes alternately in synchronization with the transmitter clock in accordance with
Detecting the arrival of the timing recovery signal
And one symbol at the timing synchronized with the receiving clock
Change of the bit timing recovery signal value
The plurality of power index values and the plurality of power index values
A step of obtaining a magnitude relation index value indicating a magnitude relation; and a timing of changing a value of a bit timing recovery signal.
To roughly estimate the power by comparing the power index values.
And the deviation of the receiving clock from the transmitting clock
To the timing obtained by the
Clock timing shift time and a step of obtaining, based, the
Estimation method. 2. An unmodulated signal and a preamble signal.
A bit timing recovery signal that follows
Burst demodulation for receiving and demodulating the phase-modulated signal transmitted
In the modulator, a means for performing quadrature detection of the received signal using the local signal and using the receiving clock as a sampling clock should not be used.
Then, the orthogonally detected received signal is sampled and demodulated.
Data and the frequency range to which the carrier can take
Calculate signal power for each of multiple available bands
If the calculated signal power satisfies the specified conditions,
Means for determining that a burst signal has arrived , and detecting no burst signal based on the behavior of the received signal value.
Means for determining whether or not the signal is a modulated signal; and determining whether or not the signal is a non-modulated signal.
The frequency offset of the local signal, and based on the result,
The frequency of the local signal to match the frequency of the carrier.
Means for controlling the number of clocks, and thereafter the clock timing offset time according to claim 1.
Performs the estimation method and, based on the result,
The timing of the receiving clock to match
Burst demodulator, characterized in that it comprises a means. 3. A burst demodulator according to claim 2, wherein
To estimate the frequency offset of the local signal with respect to the carrier
Control the frequency of the local signal based on the results.
The stage is initially set within the frequency range to which the possible carrier frequencies belong.
Signal power at each of the defined frequency points
Is calculated according to the detection of the arrival of the unmodulated signal, and the obtained signal power is calculated.
Select the frequency point at which the
Signal power within the included and narrower frequency range
The frequency points for which
The operation set in the step is changed so that the interval between the frequency points corresponds to the
Until the end of this repetition.
The frequency point at which the signal power was determined is determined as the carrier frequency.
Burst demodulator, characterized by a constant.