JPH10200587A - Complex sampling circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a circuit scale by eliminating a need for increasing a sampling frequency, in the case that a result of sampling an input signal is converted into a value of a complex number expression. SOLUTION: A correction coefficient A, that is a real part in the case that a frequency value of an input signal for a sampling frequency is expressed in a complex number, is multiplied with a sampling result. The result of multiplication and the one preceding sampling result that is obtained by delaying the sampling result with a delay circuit 4 and expressed in a complex number are added by an adder circuit 5. The result of the sum is multiplied with a correction coefficient B, that is a reciprocal of the imaginary part in the case that the frequency value of the input signal for the sampling frequency, is expressed in a complex number. Since the circuit is constituted so that the real part and the imaginary part are obtained by multiplying the correction coefficients, the sampling is not high them required for increasing, and the circuit scale is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a complex sampling circuit, and more particularly to a complex sampling circuit for converting an input analog signal into a complex signal having a real part and an imaginary part.

[0002]

2. Description of the Related Art Conventionally, there are two methods of quantizing an input analog signal into a digital signal as a complex signal of a real part and an imaginary part, as follows: an analog method and a digital method.

First, the analog system quantizes an input analog signal into a digital part by using a real part as an imaginary part and an analog signal passed through a phase shift circuit that shifts the phase by 90 ° as an imaginary part. This method will be described with reference to FIG. As shown in the figure, in the analog system, a sample-and-hold circuit 8 for quantizing an input analog signal into a digital value as it is, and a phase shift circuit 7 for shifting the phase by 90 ° at a desired frequency. A sample and hold circuit 9 for quantizing the output of the phase shift circuit 7 into a digital value; a multiplexer circuit 10 for switching between the output of the sample and hold circuit 8 and the output of the sample and hold circuit 9; This is realized by the A / D conversion circuit 11 which quantizes the held analog signal into a digital value.

On the other hand, the digital method is a method in which, when an input analog signal is quantized into a digital value, sampling is performed at a desired frequency at 90 ° steps or 45 ° steps. This method will be described with reference to FIG. As shown in the figure, in the digital system, a sample / hold circuit 12 for quantizing an input analog signal to a digital value, and an A / A circuit for quantizing the sampled and held analog signal to a digital value. D conversion circuit 1
3 and the digital signal quantized to a digital value is 1
This is realized by a delay circuit 14 that delays by a sample or two samples. The delay circuit 14 is a delay circuit for one sample when sampling at a desired frequency at 90 ° steps, and a delay circuit for two samples when sampling at 45 ° steps.

[0005]

Among the above-mentioned prior arts, in an analog circuit, a real part and an imaginary part are separated by an analog circuit. Therefore, a sample-and-hold circuit for quantizing the analog signal on the real part into a digital value, a 90 ° phase shift circuit on the imaginary part,
It is necessary to separately provide a sample and hold circuit for quantizing the analog output signal of the 0 ° phase shift circuit into a digital value. Further, a multiplexer circuit for switching between the sampled and held real part and imaginary part analog signals, and an A circuit for quantizing the analog signals into digital values.
/ D conversion circuit is required, and there is a disadvantage that the scale of hardware is increased.

In a digital circuit, the sampling frequency of A / D conversion for quantizing an analog signal into a digital value must be four times or eight times the desired frequency. For this reason, there is a disadvantage that the sampling frequency must be increased more than necessary.

Japanese Patent Application Laid-Open No. Hei 7-30499 also has a disadvantage that a sampling frequency four times or more is required.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks of the prior art, and an object of the present invention is to provide a complex sampling circuit which does not need to increase the sampling frequency and has a small circuit scale.

[0009]

SUMMARY OF THE INVENTION A complex sampling circuit according to the present invention is a complex sampling circuit for converting a sampling result obtained by sampling an input signal at a predetermined sampling frequency into a complex number value comprising a real part and an imaginary part, First multiplying means for multiplying the sampling result by a first correction coefficient which is a value of a real part when the value of the frequency of the input signal with respect to the sampling frequency is represented by a complex number, and 1 of the multiplication result and the sampling result Adding means for adding the sampling result before the sample and a second correction coefficient which is the reciprocal of the value of the imaginary part when the value of the frequency of the input signal with respect to the sampling frequency is represented by a complex number; Second multiplying means, wherein the sampling result is a real part, The multiplication results of the calculation means, characterized in that as the imaginary part.

In short, the present complex sampling circuit uses the input signal and the vector signal one sample before to multiply by a first correction coefficient, which is a constant for shifting the phase by 90 degrees, and to adjust the amplitude to one. That is, the second correction coefficient is multiplied. As a result, it is not necessary to increase the sampling frequency, and the circuit scale can be reduced.

[0011]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a complex sampling circuit according to the present invention. In the figure,
The complex sampling circuit according to the present embodiment includes a sampler for quantizing an input analog signal into a digital value.
A hold circuit 1, an A / D conversion circuit 2 for quantizing an analog signal sampled and held into a digital value,
A delay circuit 4 for delaying the A / D-converted digital signal by one sample, a multiplication circuit 3 for multiplying the A / D-converted digital signal by a correction coefficient A, and a delay of one sample from the output of the multiplication circuit 3 It comprises an adding circuit 5 for adding the output of the delay circuit 4 and a multiplying circuit 6 for multiplying the output of the adding circuit 5 by a correction coefficient B.

In such a configuration, the input analog signal is sampled and held by the sample and hold circuit 1 to quantize it into a digital value.
The digital signal is quantized by the D conversion circuit 2. At this time, a sampling signal (fs) 1 for A / D conversion is used.
00 is a sampling theorem and aliasing that sampling must be performed at a frequency twice or more the frequency of the signal to be sampled.
An arbitrary frequency that satisfies the condition of the suppression amount of g).

One of the output signals 101 of the A / D converter circuit 2 becomes a real part as it is. The other one of the output signals 101 is input to the delay circuit 4. The delay circuit 4 delays one sample.

The imaginary part is the output signal 1 of the A / D conversion circuit 2.
01 is multiplied by the correction coefficient A (102) by the multiplication circuit 3, and the output signal 103 of the multiplication circuit 3 and the output signal 104 of the delay circuit 4 are vector-added by the addition circuit 5 to obtain the result. Since the amplitude of the output signal 105 of the addition circuit 5 is smaller than “1” as it is, the multiplication circuit 6 multiplies the correction coefficient B (106) to adjust the amplitude to “1”.

Next, a more specific example will be described. First, it is assumed that the input signal (f0) = 10 [KHz] and the sampling frequency (fs) = 25 [KHz]. Then, the signal delayed by one sample is 360 × 10 [KHz] / 25
From [KHz] = 144 [deg], in complex expression, −
0.809017-j0.587785. In addition,
j is an imaginary unit, and j = (− 1) ^1/2 .

Here, a correction coefficient A (1
(02) is multiplied by the multiplying circuit 3 (0.809017). Then, the output signal 103 of the multiplication circuit 3 and the signal 104 delayed by one sample are vector-added by the addition circuit 5. Then, the result 105 obtained by the 90 ° phase shift is obtained. However, since the amplitude is 0.587785, it is the correction coefficient B (106) (1.701301 =
1 / 0.587785) in the multiplication circuit 2 to adjust the amplitude to 1. The result of this adjustment is the imaginary part output 107.

The above operation will be described with reference to the vector diagram of FIG. In the figure, the same reference numerals are given to the vectors equivalent to the signals of the respective parts in FIG. Also, the vertical axis in the figure indicates the imaginary number, and the horizontal axis indicates the real number.

First, as shown in FIG.
A sample-hold and A / D-converted input signal 101 (1
When + j) and the signal 104 one sample before are added as they are, a signal 108 is obtained, and the phase shift cannot be performed by 90 degrees. Therefore, as shown in FIG. 2B, after multiplying the input signal 101 by the first correction coefficient A to obtain the signal 103 and adding the signal 103, the signal 105 which has been phase-shifted by 90 degrees is obtained. can get.

The signal 105 which has been phase-shifted by 90 degrees
Has an amplitude other than 1. Therefore, as shown in FIG. 3C, the signal 105 is multiplied by a second correction coefficient B,
Adjust the amplitude to 1. By doing so, the amplitude becomes 1
Is obtained.

As described above, the first correction coefficient A is a constant for shifting the phase by 90 degrees using the input signal and the signal one sample before, and the second correction coefficient B is set to the amplitude of 1 It is a constant for adjustment. Since the complex sampling circuit is configured to multiply these two coefficients, the sampling does not need to be made unnecessarily high and the circuit scale can be reduced.

[0022]

As described above, according to the present invention, by multiplying a correction coefficient and performing a vector operation, a real number part can be increased without excessively increasing a sampling frequency when an analog signal is quantized into a digital value. And the imaginary part can be obtained. Further, the vector operation can be realized by two times of multiplication and one time of addition, and the A / D converter has only one system. The vector operation is performed by a DSP (Digit
al Signal Processor), etc., and in a multi-channel device, 1
The same result can be obtained by executing processing of a plurality of channels by one DSP or the like.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a complex sampling circuit according to an embodiment of the present invention.

FIGS. 2A to 2C are vector diagrams for explaining the operation of the complex sampling circuit of FIG. 1;

FIG. 3 is a block diagram illustrating an example of a conventional complex sampling circuit.

FIG. 4 is a block diagram showing another example of a conventional complex sampling circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 sample and hold circuit 2 A / D conversion circuit 3, 6 multiplication circuit 4 delay circuit 5 addition circuit

Claims (3)

[Claims] 1. A complex sampling circuit for converting a sampling result obtained by sampling an input signal at a predetermined sampling frequency into a value of a complex number expression including a real part and an imaginary part, wherein the value of the frequency of the input signal with respect to the sampling frequency is a complex number. First multiplication means for multiplying the sampling result by a first correction coefficient which is a value of a real part in the case of expression, and addition means for adding the multiplication result and a sampling result one sample before the sampling result. Second multiplication means for multiplying the result of the addition by a second correction coefficient which is the reciprocal of the value of the imaginary part when the value of the frequency of the input signal with respect to the sampling frequency is represented by a complex number. Is a real part, and the multiplication result of the second multiplication means is an imaginary part. And a complex sampling circuit. 2. The complex sampling circuit according to claim 1, wherein the sampling frequency is a value that is at least twice the frequency of the input signal. 3. The complex sampling circuit according to claim 1, wherein said adding means performs vector addition of a multiplication result of said first multiplication means and said sampling result of one sample before.