JPH01149134U - - Google Patents
Info
- Publication number
- JPH01149134U JPH01149134U JP4635288U JP4635288U JPH01149134U JP H01149134 U JPH01149134 U JP H01149134U JP 4635288 U JP4635288 U JP 4635288U JP 4635288 U JP4635288 U JP 4635288U JP H01149134 U JPH01149134 U JP H01149134U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- analog
- digital
- conversion
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 9
- 230000002457 bidirectional effect Effects 0.000 claims description 4
- 238000005070 sampling Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図は本考案の構成を示す原理図、第２図は
本考案の一実施例を示す回路ブロツク図、第３図
は本考案の一実施例のタイムチヤート、第４図ａ
，ｂは本考案のタイミング回路の説明図、第５図
は従来の一実施例を示す回路ブロツク図、第６図
は従来の一実施例のタイムチヤート、を示す。
図において、１はサンプリング回路、２は双方
向器、３は変換信号出力回路、４はタイミング回
路、５はクロツク生成回路、である。
Fig. 1 is a principle diagram showing the configuration of the present invention, Fig. 2 is a circuit block diagram showing an embodiment of the invention, Fig. 3 is a time chart of an embodiment of the invention, and Fig. 4 a.
, b are explanatory diagrams of the timing circuit of the present invention, FIG. 5 is a circuit block diagram showing a conventional embodiment, and FIG. 6 is a time chart of a conventional embodiment. In the figure, 1 is a sampling circuit, 2 is a bidirectional device, 3 is a conversion signal output circuit, 4 is a timing circuit, and 5 is a clock generation circuit.
Claims (1)
よりサンプリングし、アナログ／デジタル変換を
してデータを送出し、逆に、外部よりデータを入
力してデジタル／アナログ変換を行いアナログ信
号として入力するものにおいて、 アナログ／デジタル変換機能とデジタル／アナ
ログ変換機能とを有する双方向器２と、 前記双方向器２を切り換えるための変換信号を
出力する変換信号出力回路３と、 前記変換信号出力回路３の出力と一定の位相差
を有するパルス信号を出力するすタイミング回路
４と、 該パルス信号を基準として、アナログ信号のデ
ジタル信号への変換、およびデジタル信号のアナ
ログ信号への変換に用いるクロツクを生成して双
方向器２に出力するクロツク生成回路５と、を設
けることを特徴とするアナログ／デジタル変換イ
ンタフエース回路。[Claims for Utility Model Registration] An input analog signal is sampled by the sampling circuit 1, analog/digital conversion is performed, and the data is sent out; conversely, data is input from the outside, digital/analog conversion is performed, and the analog signal is output. A bidirectional device 2 having an analog/digital conversion function and a digital/analog conversion function, a conversion signal output circuit 3 that outputs a conversion signal for switching the bidirectional device 2, and the conversion signal. a timing circuit 4 that outputs a pulse signal having a certain phase difference with the output of the output circuit 3; and a timing circuit 4 that uses the pulse signal as a reference for converting an analog signal into a digital signal and converting a digital signal into an analog signal. An analog/digital conversion interface circuit comprising: a clock generation circuit 5 which generates a clock and outputs it to a bidirectional device 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4635288U JPH01149134U (en) | 1988-04-05 | 1988-04-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4635288U JPH01149134U (en) | 1988-04-05 | 1988-04-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01149134U true JPH01149134U (en) | 1989-10-16 |
Family
ID=31272624
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4635288U Pending JPH01149134U (en) | 1988-04-05 | 1988-04-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01149134U (en) |
-
1988
- 1988-04-05 JP JP4635288U patent/JPH01149134U/ja active Pending
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