JPS6035640U

JPS6035640U - Analog-digital converter

Info

Publication number: JPS6035640U
Application number: JP12778383U
Authority: JP
Inventors: 本間　康司
Original assignee: 株式会社明電舎
Priority date: 1983-08-18
Filing date: 1983-08-18
Publication date: 1985-03-12

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は従来のＡ−Ｄ変換方式の概略工程図、第２図は
従来のメモリ格納状態を示す図、第３図は周知の帰還逐
次比較形Ａ−Ｄ変換器の概略的構成図、第４図は本考案
の一実施例の構成図、第５図は本考案実施例のＤ−Ａ変
換器の出力を制御するカウンタの時間−出力特性図、第
６図は本実施例のメモリ格納状態を示す図である。２０・・・Ｄ−Ａ変換器、２１・・・第１カウンタ、２
２・・・被変換アナログデータ、２４・・・つき合せ回
路、２６・・・コンパレータ、２７・・・レジスタ、２
８・・・制御回路、２９・・・カウンタ、３０・・・デ
ィジタルデータ、３１・・・メモリ、３２・・・第２カ
ウンタ、３３・・・モノマルチ、３４・・・クロック。FIG. 1 is a schematic process diagram of a conventional A-D conversion method, FIG. 2 is a diagram showing a conventional memory storage state, and FIG. 3 is a schematic configuration diagram of a well-known feedback successive approximation type A-D converter. FIG. 4 is a block diagram of an embodiment of the present invention, FIG. 5 is a time-output characteristic diagram of a counter that controls the output of the D-A converter of the embodiment of the present invention, and FIG. 6 is a memory of the embodiment of the present invention. It is a figure showing a storage state. 20... D-A converter, 21... First counter, 2
2... Analog data to be converted, 24... Matching circuit, 26... Comparator, 27... Register, 2
8... Control circuit, 29... Counter, 30... Digital data, 31... Memory, 32... Second counter, 33... Monomulti, 34... Clock.

Claims

[Scope of utility model registration request]

a plurality of matching circuits to which a plurality of analog data are individually supplied to a first human power; a first counter that sends out a step-like signal and returns to an initial state when the step-like signal reaches a predetermined step; a digital-to-analog converter to which the step signal of the first counter is supplied, outputs an analog signal controlled by the step signal, and supplies the analog signal to the second input circuit of the matching circuit; Addresses are sequentially designated by a plurality of comparators to which each output of the combining circuit is supplied separately and digital data is sent to the output, and an output of a second counter that synchronizes the digital data output from these comparators with the first counter. 1. An analog-to-digital conversion device comprising: