JPS6423122U - - Google Patents
Info
- Publication number
- JPS6423122U JPS6423122U JP11767087U JP11767087U JPS6423122U JP S6423122 U JPS6423122 U JP S6423122U JP 11767087 U JP11767087 U JP 11767087U JP 11767087 U JP11767087 U JP 11767087U JP S6423122 U JPS6423122 U JP S6423122U
- Authority
- JP
- Japan
- Prior art keywords
- phase
- phase shifter
- memory
- controls
- input signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
- 230000037431 insertion Effects 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
Description
第１図は本考案の一実施例によるデイジタル制
御移相器の構成を示すブロツク図、第２図はハイ
ブリツド型移相器の位相量と挿入損失の関係を示
した図、第３図はオーバラツプ機能の動作を示す
図、第４図はハイブリツド型移相器の構成を示す
図である。
１：ハイブリツド型移相器、２：Ｄ／Ａコンバ
ータ、３：メモリ、４：オーバラツプ回路。
FIG. 1 is a block diagram showing the configuration of a digitally controlled phase shifter according to an embodiment of the present invention, FIG. 2 is a diagram showing the relationship between the phase amount and insertion loss of a hybrid phase shifter, and FIG. 3 is a diagram showing the relationship between the phase amount and insertion loss of a hybrid phase shifter. FIG. 4 is a diagram showing the structure of a hybrid phase shifter. 1: Hybrid phase shifter, 2: D/A converter, 3: Memory, 4: Overlap circuit.
Claims (1)
ナスの数度の余裕を与えるオーバラツプ回路と、 前記オーバラツプ回路からの位相制御値を前記
移相器への印加電圧へ変換するためのメモリと、 前記メモリで変換された印加電圧をデイジタル
値からアナログ値に変換して前記移相器へ供給す
るＤ／Ａコンバータとから構成されることを特徴
とするデイジタル制御移相器。[Claims for Utility Model Registration] A phase shifter that controls the phase of an input signal, an overlap circuit that provides a margin of several degrees plus or minus for a phase control value of 0 to 360 degrees, and a phase shifter that controls the phase of an input signal; a memory for converting a phase control value into a voltage applied to the phase shifter; and a D/A converter that converts the applied voltage converted by the memory from a digital value to an analog value and supplies it to the phase shifter. A digitally controlled phase shifter comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11767087U JPS6423122U (en) | 1987-07-31 | 1987-07-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11767087U JPS6423122U (en) | 1987-07-31 | 1987-07-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6423122U true JPS6423122U (en) | 1989-02-07 |
Family
ID=31361331
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11767087U Pending JPS6423122U (en) | 1987-07-31 | 1987-07-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6423122U (en) |
-
1987
- 1987-07-31 JP JP11767087U patent/JPS6423122U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS62112221U (en) | ||
| JPS6423122U (en) | ||
| JPS63111030U (en) | ||
| JPS62191230U (en) | ||
| JPS6160340U (en) | ||
| JPH0224642U (en) | ||
| JPS60148657U (en) | Analog multiplier for satellite installation | |
| JPH0157825U (en) | ||
| JPS61107236U (en) | ||
| JPH0160282U (en) | ||
| JPS6356826U (en) | ||
| JPS639644U (en) | ||
| JPS63196126U (en) | ||
| JPS58139738U (en) | Digital-to-analog conversion circuit | |
| JPS6433218U (en) | ||
| JPH0177037U (en) | ||
| JPS6035640U (en) | Analog-digital converter | |
| JPS6298346U (en) | ||
| JPH0210640U (en) | ||
| JPS6190329U (en) | ||
| JPS62198896U (en) | ||
| JPS61103967U (en) | ||
| JPS5899931U (en) | Digital-to-analog conversion circuit | |
| JPH01159438U (en) | ||
| JPH0182523U (en) |