JPH01159438U - - Google Patents

Info

Publication number
JPH01159438U
JPH01159438U JP5347988U JP5347988U JPH01159438U JP H01159438 U JPH01159438 U JP H01159438U JP 5347988 U JP5347988 U JP 5347988U JP 5347988 U JP5347988 U JP 5347988U JP H01159438 U JPH01159438 U JP H01159438U
Authority
JP
Japan
Prior art keywords
circuit
serial
parallel
correction delay
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5347988U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5347988U priority Critical patent/JPH01159438U/ja
Publication of JPH01159438U publication Critical patent/JPH01159438U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案実施例におけるPCM受信回路
のブロツク図である。 1:補正用遅延回路、1a:データ補正用の遅
延回路、1b:クロツク補正用の遅延回路、2:
遅延量制御回路、3:シリアル/パラレル変換回
路、4:ラツチ回路。
FIG. 1 is a block diagram of a PCM receiving circuit according to an embodiment of the present invention. 1: Delay circuit for correction, 1a: Delay circuit for data correction, 1b: Delay circuit for clock correction, 2:
Delay amount control circuit, 3: serial/parallel conversion circuit, 4: latch circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] データとクロツク信号との位相を調整する補正
用遅延回路と、この補正用遅延回路の制御を行な
う遅延量制御回路と、上記補正用遅延回路から出
力されるシリアル信号をパラレル信号に変換する
シリアル/パラレル変換回路と、このシリアル/
パラレル変換回路からのパラレルデータをラツチ
するラツチ回路とを具備したことを特徴とするP
CM受信回路。
A correction delay circuit that adjusts the phase of data and a clock signal, a delay amount control circuit that controls this correction delay circuit, and a serial/transformer that converts the serial signal output from the correction delay circuit into a parallel signal. Parallel conversion circuit and this serial/
P characterized by comprising a latch circuit that latches parallel data from a parallel conversion circuit.
CM receiving circuit.
JP5347988U 1988-04-22 1988-04-22 Pending JPH01159438U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5347988U JPH01159438U (en) 1988-04-22 1988-04-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5347988U JPH01159438U (en) 1988-04-22 1988-04-22

Publications (1)

Publication Number Publication Date
JPH01159438U true JPH01159438U (en) 1989-11-06

Family

ID=31279452

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5347988U Pending JPH01159438U (en) 1988-04-22 1988-04-22

Country Status (1)

Country Link
JP (1) JPH01159438U (en)

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