JPS6273356U - - Google Patents
Info
- Publication number
- JPS6273356U JPS6273356U JP16275785U JP16275785U JPS6273356U JP S6273356 U JPS6273356 U JP S6273356U JP 16275785 U JP16275785 U JP 16275785U JP 16275785 U JP16275785 U JP 16275785U JP S6273356 U JPS6273356 U JP S6273356U
- Authority
- JP
- Japan
- Prior art keywords
- clock
- signal
- time axis
- axis error
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims 6
- 238000005070 sampling Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Television Signal Processing For Recording (AREA)
- Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
Description
第１図は、本考案の一実施例を示すブロツク図
、第２図は、従来の時間軸誤差制御装置を示すブ
ロツク図である。
主要部分の符号の説明、２……ＣＣＤ、１５…
…ＶＣＯ、１６……非線形回路。
FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional time axis error control device. Explanation of symbols of main parts, 2...CCD, 15...
...VCO, 16...nonlinear circuit.
Claims (1)
に応じた信号遅延時間を有しかつ基準信号のレベ
ルに応じた利得を有するクロツク応答遅延素子に
よつて制御する時間軸誤差制御装置であつて、前
記クロツクの周波数に応じたレベルを有する制御
信号を発生する制御信号発生手段を含み、前記制
御信号を前記クロツク応答遅延素子に前記基準信
号として供給したことを特徴とする時間軸誤差制
御装置。 (2) 前記クロツク応答遅延素子は、前記入力信
号を前記クロツクによつて標本化して得た瞬時レ
ベルを前記基準信号のレベルに応じた変換率で電
荷に変換する第１変換手段と、電荷を所定の変換
率で電圧に変換する第２変換手段と、前記第１変
換手段によつて得られた電荷を前記クロツクによ
つて前記第２変換手段に転送する転送手段とから
なる電荷転送素子であることを特徴とする実用新
案登録請求の範囲第１項記載の時間軸誤差制御装
置。[Claims for Utility Model Registration] (1) Controlling the time axis error of the input signal by a clock response delay element having a signal delay time corresponding to the frequency of the clock and a gain corresponding to the level of the reference signal. The time axis error control device is characterized in that it includes a control signal generating means for generating a control signal having a level corresponding to the frequency of the clock, and the control signal is supplied to the clock response delay element as the reference signal. A time axis error control device. (2) The clock response delay element includes a first conversion means for converting an instantaneous level obtained by sampling the input signal by the clock into an electric charge at a conversion rate corresponding to the level of the reference signal; A charge transfer element comprising a second conversion means for converting into voltage at a predetermined conversion rate, and a transfer means for transferring the charge obtained by the first conversion means to the second conversion means using the clock. A time axis error control device according to claim 1 of the utility model registration claim.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16275785U JPS6273356U (en) | 1985-10-23 | 1985-10-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16275785U JPS6273356U (en) | 1985-10-23 | 1985-10-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6273356U true JPS6273356U (en) | 1987-05-11 |
Family
ID=31090324
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16275785U Pending JPS6273356U (en) | 1985-10-23 | 1985-10-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6273356U (en) |
-
1985
- 1985-10-23 JP JP16275785U patent/JPS6273356U/ja active Pending
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