JPH0182523U - - Google Patents
Info
- Publication number
- JPH0182523U JPH0182523U JP1987178479U JP17847987U JPH0182523U JP H0182523 U JPH0182523 U JP H0182523U JP 1987178479 U JP1987178479 U JP 1987178479U JP 17847987 U JP17847987 U JP 17847987U JP H0182523 U JPH0182523 U JP H0182523U
- Authority
- JP
- Japan
- Prior art keywords
- digital
- analog converter
- analog
- significant bit
- converter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図は本考案の一実施例を示すブロツク図、
第２図はその動作説明図、第３図は従来例を示す
回路図である。
２，７…モードスイツチ、３…ＤＡコンバータ
、４…加算器、９…制御装置。
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is an explanatory diagram of its operation, and FIG. 3 is a circuit diagram showing a conventional example. 2, 7...Mode switch, 3...DA converter, 4...Adder, 9...Control device.
Claims (1)
デイジタルアナログ変換器において、前記デイジ
タルアナログ変換器を調整モードに設定する手段
と、該調整モードにおいて前記入力デイジタル信
号に換えて、最上位ビツトのみオンとなる第１の
デイジタル信号と、最上位ビツトのみオフとなる
第２のデイジタル信号とを交互に前記デイジタル
アナログ変換器に印加する手段と、上記第１及び
第２のデイジタル信号のうちの一方に対応するデ
イジタルアナログ変換器の出力に最下位ビツトに
対応するアナログ変換出力を加算もしくは減算す
る手段と、第１及び第２のデイジタル信号印加期
間にそれぞれ得られる上記アナログ変換出力のレ
ベル差を最少にする様に上記デイジタルアナログ
変換器の最上位ビツトに対応するアナログ変換出
力を調整する手段とを有することを特徴とするデ
イジタルアナログ変換器。 A digital-to-analog converter for converting an input digital signal into an analog signal, comprising: means for setting the digital-to-analog converter to an adjustment mode; and a first circuit that turns on only the most significant bit in place of the input digital signal in the adjustment mode. means for alternately applying to the digital-to-analog converter a digital signal and a second digital signal in which only the most significant bit is turned off; and a digital-to-analog converter corresponding to one of the first and second digital signals. means for adding or subtracting the analog conversion output corresponding to the least significant bit to the output of the converter; A digital-to-analog converter comprising means for adjusting an analog conversion output corresponding to the most significant bit of the digital-to-analog converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987178479U JPH0182523U (en) | 1987-11-24 | 1987-11-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987178479U JPH0182523U (en) | 1987-11-24 | 1987-11-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0182523U true JPH0182523U (en) | 1989-06-01 |
Family
ID=31470093
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987178479U Pending JPH0182523U (en) | 1987-11-24 | 1987-11-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0182523U (en) |
-
1987
- 1987-11-24 JP JP1987178479U patent/JPH0182523U/ja active Pending