JPS62225027A - Variable frequency divider - Google Patents

Abstract

PURPOSE:To obtain an optional frequency division output signal stable at all times with a simple circuit by using a triangle wave whose frequency is equal to the frequency division, smapling and holding it by a clock pulse, converting the result into an analog signal and obtaining a desired output via an LPF. CONSTITUTION:In obtaining a 4/30 frequency division output of an input clock pulse CP, when an output of a latch circuit 14 is zero at first, an addend 4 is given to an addition/subtraction circuit 11 to apply the addition of 0+4=4. Then 4 is added to the result of addition at each arrival of the pulse CP and when the result reaches the relation of 12+4=16, since it exceeds 15, an overflow signal Cl is outputted to bring an addition/subtraction circuit 12 into the subtraction mode, a minuend 30 is inputted to the circuit 12 to apply subtraction of 30-16=14. In such a case, the circuit 11 is brought into the subtraction mode by an output Q of the circuit 14 to output the result of 14&-4=10 and when the result reaches '2', an underflow signal C2 is outputted, '0' is inputted to the circuit 12 to apapaly subtraction of 0-(&-2)=2 and the state is restored to the initial state. An output of a latch circuit 13 is inputted to an LPF 18 via a ROM 16 and a D/A converter 17 and a desired frequency division output signal is obtained from the output.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] [Technical Background of the Invention and Problems Therewith] A conventional frequency divider circuit inputs an input signal fin (square wave) to a flip-flop and divides it into percentages as shown in FIG. It is common to obtain the circumferential output. Further, by cascading multiple stages of flip-flops as shown in the figure, an output of 3 AM can be obtained. In addition, the output duty is not 50% but 1/N (
Many frequency divider circuits have been devised where Nl is an integer greater than or equal to 2.5 On the other hand, a frequency divider circuit with an arbitrary frequency division ratio such as M/N (however, 822M) has been devised using 1/(an integer ), and by inserting a certain number of pulses into the input clock pulse or thinning it out by one, the desired output can be written using the divided output. However, in this method, the output duty is completely random, and the number of pulses within a certain period of time is simply M/N compared to the input.

Conventionally, a PLL (7A locked loop) has been used for this purpose as shown in FIG.

In other words, 1 output frequency is 1/1/H to input frequency Thl/H.
Divide the frequency into M, input the outputs of both divisions to the phase comparator (P, D), P, D output 'lt filter (L, P, F) all through VC
0 (voltage controlled oscillator) and loop control is performed so that the output frequency fout becomes the input M/N.

However, with this method, the PLL pull-in time.

Problems with output frequency stability and jitter often occur due to pull-in ranges, lock ranges, etc.

[Purpose of the invention]

The present invention has been made to solve the above-mentioned problems, and its purpose is to always stably output all M/H branch outputs [Summary of the Invention] ,
The output of the latch circuit that samples and holds the digital value in synchronization with the clock pulse is added.

Holding this addition result in the latch circuit in synchronization with the clock pulse is repeated for each clock pulse,
If the addition result (N3) is greater than or equal to the predetermined value (Nl), the addition result (N3) is subtracted from 2×N1, and this subtraction result is held in the latch circuit (in synchronization with the clock). Subtracting the integer (M) from the output from the latch circuit and inputting this subtraction result to the latch circuit is repeated every time a clock pulse is input to make sure that the subtraction result (N4) is less than or equal to a predetermined value (N2). Case 2 above
subtracting the subtraction result (N4) Th from ×N2, and holding this subtraction result in the latch circuit in synchronization with the clock;
Thereafter, the output from the latch circuit and the integer M are added together, and the digital value output from the latch circuit is input to a DA converter to convert it into an analog value. According to the present invention, an output of an arbitrary frequency division ratio of M/N can be stably obtained by using a simple circuit.

[Embodiments of the invention]

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, which will be explained by taking as an example a case where an output is obtained by dividing the input frequency by 4/3°. Input f to be divided
in is supplied to each circuit as a clock pulse. 1st
The summand of the adder/subtractor 11 is the output Dou of the latch circuit 13.
t is added, and the addend is given the number Dio of the numerator of the frequency division ratio (4 in this case). As an initial state, the output of the latch circuit 13 is set to Do u t =0. First, Din and Dout are added in the first addition/subtraction circuit 11, and the output is 0+4=4.If the output of the first addition/subtraction circuit is 15 or more, OverflowC1 is output, and if it is O or less, Unde is output.
rflow C2 is output. In the first step above, since it is 0 (4 (15), neither CI nor C2 is output.
The addition output of the first addition/subtraction circuit 11 is input to the augend input A of the second addition/subtraction circuit 12, and the addition input is O, and its output is the same as the first addition output, and is latched by the clock pulse Cp. The circuit 13 holds the output result of the second addition/subtraction circuit 12 and sets it as Dout (4 in this case).

In the second step, the output of the addition/subtraction circuit 11 is Dout
+Din=4+4=8, and with subsequent clock pulses, the latch circuit holds 8 and Dout=8.

Similarly, in the third step, Dout=8+4=12.

In the fourth step, the output of the first addition/subtraction circuit 11 is 12+
4 to 16) OverflowC1 is output.

The C1 output passes through the gate circuit 15 to the second addition/subtraction circuit 12.
is in subtraction mode. On the other hand, the denominator of frequency division=30 is inputted to the output of C1 as the subtractable number of the second addition/subtraction circuit 12. The output of the second addition/subtraction circuit 12 is 3O-16=14. On the other hand, the c1 output is stored by the gate circuit 15 and an output p-6 is obtained. With subsequent clock pulses, the latch circuit 14 obtains an output Q'. In the fifth step, the first addition/subtraction circuit 11 converts Dou into subtraction mode by Q into Di.
Output n (14-4=10). Neither C1 nor C2 is output, and the second addition/subtraction circuit 12 adds the addition mode and diO, and its output becomes 10, and the p latch circuit 13 outputs Dout.
=10. Similarly, in the sixth step, Dout=10
4=6 In the seventh step, Dout=6-4=2. In the eighth step, the output of the first addition/subtraction circuit 11 is 2-4.
=-2, Underfluw C2 is output, and the second addition/subtraction circuit 12 is in the subtraction mode and O is input as the subtractable number. Therefore, the 12 output of the addition/subtraction circuit of the broom 2 becomes 0-(-2)=2, and the subsequent clock pulse makes 5Dout=2. On the other hand, C
2, the output P of the switching gate circuit 15 is reset, and the clock pulse returns the output Q to the initial state. In the ninth step, the process returns to the first step and becomes Dout=2+4=6. Thereafter, addition and subtraction are repeated in the same manner to sequentially obtain Dout.

The above operation timing is shown using FIG. 2.

First, in Figure 2 (a), Dout repeats addition and subtraction by 4 each time an input clock pulse is applied, and is equal to the sampled triangular wave with an amplitude of 151 and a frequency of 4/3 of the clock pulse using a clock pulse. Become. Dout is converted into an analog signal by the DA converter 17 in FIG. 1, and a fundamental wave is obtained by the low-pass filter (or band-pass filter) 18. A sine wave of 4/30 of the clock pulse is obtained from the filter output.

A square wave output can be easily obtained by shaping the sine wave using a comparator. In the above explanation, 4/3
゜We have explained about frequency division, but by changing the value of Dln, a frequency division ratio of j70/30 to 15/30 can be obtained. Various branching ratios (0 to 3A) can be easily obtained.

If the secondary input fin is a square wave with a duty of 50, any division ratio between 0 and 1 can be obtained by operating the latch circuit at both the rise and fall of the square wave.

Furthermore, it is also possible to input the filter output to a flip-flop circuit to obtain an output with a higher frequency division ratio.

In the circuit shown in Fig. 1, the output of the D-A converter 17 samples a triangular wave as shown in Fig. 2, and the filter has many high frequencies, so the filter must be able to remove frequencies higher than the secondary high frequency. .

When changing the value of Din and changing the output frequency, it is inconvenient that the characteristics of the filter must be evaluated each time. In such a case, the latch circuit 13 and the D-A
A ROM (or AM) s6 is inserted between the converters 17 to convert a triangular wave to an 8 inch wave. By inserting ROM16, the generation of high frequencies can be suppressed and the filter L,
P and f13 may be any filter that satisfies the Nyquist condition and completely removes fin/2 or more.

The same symbols are used for the same functional blocks shown in the detailed configuration diagram of FIG. 3 in FIG. flIJ4. 1st. Second addition/subtraction circuit (11, 12) 12 is a 6-bit circuit;
5-bit output of addition/subtraction circuit 11 1kQverfln
w output and used as 6-bit f Underf low output4. Din is 4 or 100 in binary
'' is input. When the control terminals C of the addition/subtraction circuits 11 and 12 become H level, the subtraction mode is based on two's complement, and when it is at Lo level, it is the addition mode. The gate circuit 1 described above
5 is 0verf low, Underfl as shown in the figure.
EX-OR2G with ow output as input, AND 2
1. Hydrocyanic acid can be easily generated using 0R23 and the RS latch circuit 23.

The overflow output causes the second addition/subtraction circuit 12 to enter the subtraction mode and outputs 30. Binary” 1
1110'' is given by EX-0 几20.Ove
When there is no rflow output, that is, FX-OR20
When is at the LO level, all the subtractive inputs of the second addition/subtraction circuit 12 become 0. The ROMte may be a 16×4=64-bit memory, and the ROMt, D, and /A may also be 4-bit precision ones.

FIG. 5 shows the operation timing chart of FIG. 4. The output of the latch 13 described above has an amplitude of 15. Sampled with a triangular wave tan of frequency -fin, the same as the above ROM
The output of 16 is a sine wave tfin with amplitude 15 frequency ↓fin
and the above fin,
EX-OR20, AND21.

The timing of each output signal of 0R22, latches 23 and 24 is as shown in the figure.

FIG. 6 is an example in which an addition/subtraction circuit is implemented using only the adder 25 described above, and SW is Hi.

As the adder output, the addition/subtraction result of A-B or A+B can be obtained.

FIG. 7 is another specific configuration diagram of FIG. 1.

Overflow and Underflow digital comparators 31 and 32 are used to determine whether the flow is overflow or underflow. That is, Over
The flow output is outputted by the comparator 32 at the set value N1 or more, and the Underflow is outputted by the comparator 31 at the set value N2.
The following is output. For example, N1=13. N2: set to 2, and the second addition/subtraction circuit 12a sets 4 or 2 as the minuend.
If 6 is given, the latch circuit 13 is equivalent to a sampled triangular wave between 2 and 13, and the DA converter 17
゜The output after passing through L, P, F 18 is a sine wave called -fin.Of course, the contents of ROM 16 are data 2~
It is changed so that the optimum sine wave is output when changing within the range of 13. N1=15. If Nz=:0, the same output as the example '' in FIG. 4 can be obtained.

Above, Din is 4 bits, addition/subtraction circuit is 6 bits precision, R
Although the OM, D/A conversion circuit, etc. have been described with 4-bit precision, expanding the number of bits will reduce deviceization errors and improve frequency precision. For example, if Din is 8 bits, the addition/subtraction circuit may be 10 bits, and the ROM, A-A converter, etc. may be 8 bits.

As explained above, according to the present invention, M/N (M≦N/2)
An output with an arbitrary division ratio can be obtained with a simple circuit, no adjustment is required, the division ratio can be set as a digital value, it can be easily changed, and there is no long-term fluctuation.

[Brief explanation of drawings]

FIG. 1 is a principle diagram of the present invention, FIG. 2 is a timing chart for explaining FIG. 1, FIG. 3 is a configuration diagram of an embodiment of the present invention, and FIG. 4 is an embodiment of the present invention. 5 is a timing chart for explaining FIG. 4, FIG. 6 is a configuration diagram of an adder, FIG. 7 is a configuration diagram of an embodiment according to the present invention, and FIG. 8 is an outer peripheral circuit. FIG. 9 is a block diagram of a conventional frequency dividing circuit using PLIe. Busik tV person 77A Figure 6

Claims (1)

[Claims] 1) An integer M (M
≧0) and the output of a latch circuit that samples and holds digital values in synchronization with clock pulses, and this addition output is held in the latch circuit in synchronization with clock pulses, which is repeated every clock pulse. , if the addition output (N_3) is equal to or greater than a predetermined value (N_1), subtract the addition output (N_3) from 2×N_1;
This subtraction result is held in the latch circuit in synchronization with the clock, and then the integer (M) is subtracted from the output from the latch circuit, and a clock pulse is input to input this subtraction output to the latch circuit. If the subtraction output (N_4) becomes less than a predetermined value (N_2), the subtraction output (N_4) is subtracted from the 2×N_2, and this subtraction output is synchronized with the clock and held in the latch circuit. , After that, the digital value output from the latch circuit is input to a DA converter to convert it into an analog value, and this analog value is converted to the clock pulse by M/{3(N_1-N_2)}( M≦N_
A variable frequency divider that obtains a divided output signal of 1-N_2). 2) Data conversion is performed on the digital value output from the latch circuit using a memory, and then digital-to-analog conversion is performed. This digital-to-analog output is divided and output using a low-pass filter that passes a frequency of 1/2 or less of the clock pulse. A variable frequency divider characterized by obtaining a signal. 3) The predetermined values (N_1) and (N_2) are N_1=2^k-
1 (k>0), N_2=0, and when the integer (M) is expressed by K bits of binary number, the addition/subtraction circuit is used as a K+2 bit operation, and the K+1 bit of the addition result (N_3) is "1". , if the K+2nd bit becomes 0, 2(2^k1)
-N_3 is held in the latch circuit, and after that, the integer (M) is subtracted from the latch circuit output using two's complement in binary notation, and both the K+1 bit and K+2 bit of the subtraction output (N_4) become "1". Then hold 0-N_4 in the latch circuit, and then convert the output from the latch circuit and the integer (M) to 2.
The variable component according to claim 1, wherein data output from a ROM or RAM is added in base format, and the data output from a ROM or RAM using an output from a latch circuit as an address is converted into digital/analog to obtain a frequency-divided output using a low-pass filter. Peripheral organs.