CN114204937B - Frequency divider circuit and frequency synthesizer - Google Patents
Frequency divider circuit and frequency synthesizer Download PDFInfo
- Publication number
- CN114204937B CN114204937B CN202210139588.3A CN202210139588A CN114204937B CN 114204937 B CN114204937 B CN 114204937B CN 202210139588 A CN202210139588 A CN 202210139588A CN 114204937 B CN114204937 B CN 114204937B
- Authority
- CN
- China
- Prior art keywords
- input end
- clock signal
- trigger
- phase
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000010363 phase shift Effects 0.000 claims description 35
- 230000000630 rising effect Effects 0.000 claims description 10
- 230000002441 reversible effect Effects 0.000 claims description 4
- 230000008859 change Effects 0.000 abstract description 7
- 230000003111 delayed effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 13
- 238000000034 method Methods 0.000 description 6
- 230000009977 dual effect Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 3
- 230000002411 adverse Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
The invention relates to the field of integrated circuits, and discloses a frequency divider circuit and a frequency synthesizer, which comprise a phase deviation unit, an integer frequency divider and a phase control unit, wherein the input end of the phase control unit inputs a parameter i, the phase control unit outputs i-time pulses in each period of an output clock signal, then the phase deviation unit outputs the ith deviation clock signal, and the phase of the input clock signal of the integer frequency divider is delayed every time i is increased by 1
The output clock signal of the integer frequency divider needs to be delayed
At a period of the initial clock signal, a division ratio of the final divider circuit is
The variation step diameter of the frequency dividing ratio is
And the step diameter is smaller than the change step diameter of the frequency dividing ratio in the prior art, so that the jitter of the output signal is reduced, and the stability of the output signal is improved.
Description
Technical Field
The present invention relates to the field of integrated circuit design, and in particular, to a frequency divider circuit and a frequency synthesizer.
Background
Frequency synthesizers are commonly used in the field of integrated circuits to multiply the frequency of an input signal, and the frequency multiplication function of a frequency synthesizer is essentially performed by a frequency divider circuit. Sometimes, it is necessary to set the dividing ratio of the frequency divider circuit to a small number, for example, the dividing ratio N = M + F, where M is an integer and F is a decimal, and the prior art often adopts the purpose of changing the dividing ratio of the integer frequency divider circuit between M and M +1, and adjusting the ratio of the output signal with the dividing ratio M and the output signal with the dividing ratio M +1 in time to realize the dividing ratio N = M + F. However, when the frequency division ratio is changed, the output signal of the frequency synthesizer may jitter, and the jitter of the output signal is in positive correlation with the variation step of the frequency division ratio, the variation step of the frequency division ratio of the integer frequency divider in the prior art is 1, and the jitter of the output signal is large, which may adversely affect the stability of the output signal.
Disclosure of Invention
The invention aims to provide a frequency divider circuit and a frequency synthesizer, which can reduce the change step diameter of a frequency dividing ratio on the basis of dividing an initial clock signal by any decimal frequency dividing ratio, thereby reducing the jitter of an output signal and improving the stability of the output signal.
In order to solve the above technical problem, the present invention provides a frequency divider circuit, which includes a phase offset unit, an integer frequency divider, and a phase control unit;
the phase shift unit is used for generating based on an initial clock signal
An offset clock signal and outputs the ith offset clock signal, wherein i is a parameter input by the input end of the phase control unit,
the frequency of each offset clock signal is the same as that of the initial clock signal, and the phase difference between two adjacent offset clock signals is
I is a positive integer, k is a positive integer not less than 2;
the integer frequency divider is used for generating an output clock signal with the frequency being 1/M of the frequency of the input clock signal based on the input clock signal of the integer frequency divider, wherein M is a positive integer;
the phase control unit is used for generating i times of pulses in one period of the output clock signal;
The input end of the phase deviation unit is used for inputting an initial clock signal, the output end of the phase deviation unit is connected with the input end of the integer frequency divider, the output end of the integer frequency divider is connected with the control end of the phase control unit, and the output end of the phase control unit is connected with the control end of the phase deviation unit.
Preferably, the phase control unit comprises a trigger, a reset unit and a trigger control unit;
the input end of the reset unit is the control end of the phase control unit, the input end of the trigger control unit is the input end of the phase control unit, and the positive output end of the trigger is the output end of the phase control unit;
the output end of the reset unit is connected with the control end of the trigger control unit, the output end of the trigger control unit is connected with the input end of the trigger, and the clock signal input end of the trigger is connected with the input end of the integer frequency divider;
the clock signal input end of the trigger is used for inputting a clock signal, the trigger is used for outputting the level corresponding to the input end of the trigger when the clock signal is at a rising edge, and outputting the low level when the clock signal is at a falling edge;
The reset unit is used for controlling the trigger control unit to work once in one period of the output clock signal, and the trigger control unit is used for controlling the level of the input end of the trigger so that the trigger can output i-time pulses.
Preferably, the trigger control unit comprises a thermometer code converter and
each trigger control subunit comprises a two-way selector and a first D trigger;
the input end of the thermometer code converter is the input end of the trigger control unit,
the control end of each trigger control subunit is the control end of the trigger control unit,
of a control subunit of said flip-flopA first input terminal and
the output ends of the trigger control subunits are sequentially connected in series, one end of the circuit after the series connection is grounded, the other end of the circuit after the series connection is connected with the input end of the trigger, and the thermometer code converter
An output terminal and
the second input ends of the trigger control subunits are correspondingly connected one by one;
the first input end of the two-way selector is the first input end of the trigger control subunit, the second input end of the two-way selector is the second input end of the trigger control subunit, the control end of the two-way selector is the control end of the trigger control subunit, the output end of the two-way selector is connected with the input end of the first D trigger, the in-phase output end of the first D trigger is the output end of the trigger control subunit, and the clock signal input end of the first D trigger is connected with the input end of the integer frequency divider;
The thermometer code converter is used for outputting a thermometer code corresponding to i, and the number of bits of the thermometer code is
And the two-way selector is used for outputting the value of the first input end of the two-way selector when the reset unit outputs the first level and outputting the value of the second input end of the two-way selector when the reset unit outputs the second level.
Preferably, the reset unit includes a second D flip-flop and an and gate;
the non-inverting input end of the second D trigger is the input end of the reset unit, and the output end of the AND gate is the output end of the reset unit;
and the reverse output end of the second D trigger is connected with the first input end of the AND gate, and the clock signal input end of the second D trigger is respectively connected with the input end of the integer frequency divider and the second input end of the AND gate.
Preferably, the phase shift unit includes a phase generator, a multiplexer, and a phase shift control module, and the phase shift control module includes k third D flip-flops;
the phase generator is used for generating based on the initial clock signal
-said offset clock signal;
the phase offset control module is used for generating a phase offset control signal based on the number of times of the pulse output by the phase control unit;
The multiplexer is used for outputting an offset clock signal corresponding to the phase offset control signal;
the input terminal of the phase generator is the input terminal of the phase shift unit
The output ends are connected with the input end of the multiplexer in a one-to-one correspondence manner, the output end of the multiplexer is the output end of the phase deviation unit, the control end of the multiplexer is connected with the output end of the phase deviation control module, and the input end of the phase deviation control module is the control end of the phase deviation unit;
the clock signal input end of k third D flip-flops and the in-phase output end of k third D flip-flops are sequentially connected in series, the clock signal input end of the first third D flip-flop is the input end of the phase deviation control module, the in-phase output end of the kth third D flip-flop is the output end of the phase deviation control module, and the in-phase input end of the third D flip-flop is connected with the reverse output end of the third D flip-flop.
Preferably, the flip-flop comprises a first tri-state inverter, a second tri-state inverter, a third tri-state inverter, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter and a nand gate;
The input end of the first tri-state inverter is the input end of the trigger, the input end of the first inverter is the clock signal input end of the trigger, and the output end of the fourth inverter is the positive output end of the trigger;
the clock signal input end of the first tri-state inverter, the clock signal input end of the second tri-state inverter and the clock signal input end of the third tri-state inverter are all connected with the input end of the first inverter, and the inverted clock signal input end of the first tri-state inverter, the inverted clock signal input end of the second tri-state inverter and the inverted clock signal input end of the third tri-state inverter are all connected with the output end of the first inverter;
the output end of the first tri-state inverter is connected with the output end of the second tri-state inverter and the input end of the second inverter respectively, the input end of the second tri-state inverter and the output end of the second inverter are connected, the public end of the connection is connected with the input end of the third tri-state inverter, the output end of the third tri-state inverter is connected with the input end of the third inverter, the input end of the fourth inverter and the output end of the NAND gate respectively, the output end of the third inverter is connected with the input end of the fifth inverter, the public end of the connection is connected with the first input end of the NAND gate, and the second input end of the NAND gate is connected with the input end of the first inverter.
In order to solve the above technical problem, the present invention further provides a frequency synthesizer, which includes the above frequency divider circuit.
The beneficial effects of the invention are as follows: a frequency divider circuit and a frequency synthesizer are provided, which comprises a phase offset unit, an integer divider and a phase control unit, wherein the input end of the phase control unit inputs a parameter i, and the phase of the input end of the phase control unit is within each period of the output clock signal of the integer dividerThe bit control units output i times of pulses, then the phase shift unit outputs the ith shift clock signal, because the period of the shift clock signal is consistent with that of the initial clock signal and the phase difference between two adjacent shift clock signals is
So that the phase of the input clock signal of the integer divider is delayed every time i is increased by 1
The output clock signal of the integer frequency divider needs to be delayed
At a period of the initial clock signal, a division ratio of the final divider circuit is
The variation step diameter of the frequency dividing ratio is
And the step diameter is smaller than the change step diameter of the frequency dividing ratio in the prior art, so that the jitter of the output signal is reduced, and the stability of the output signal is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a frequency divider circuit according to the present invention;
fig. 2 (a) is a partial circuit diagram of a frequency divider circuit provided in the present invention;
FIG. 2 (b) is another circuit diagram of a frequency divider circuit according to the present invention;
fig. 3 is a circuit diagram of a flip-flop according to the present invention.
Detailed Description
The core of the invention is to provide a frequency divider circuit and a frequency synthesizer, which reduce the change step diameter of the frequency dividing ratio on the basis of realizing the frequency division of the initial clock signal by any decimal frequency dividing ratio, thereby reducing the jitter of the output signal and improving the stability of the output signal.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a frequency divider circuit according to the present invention, which includes a phase shift unit 001, an integer frequency divider 002 and a phase control unit 003;
The phase shift unit 001 is used for generating based on an initial clock signal
An ith offset clock signal, wherein i is a parameter input by the input terminal of the phase control unit 003,
the frequency of each offset clock signal is the same as that of the initial clock signal, and the phase difference between two adjacent offset clock signals is
I is a positive integer, k is a positive integer not less than 2;
the integer divider 002 is configured to generate an output clock signal having a frequency of 1/M of the frequency of the input clock signal based on the input clock signal of the integer divider 002, where M is a positive integer;
the phase control unit 003 is for generating pulses i times within one cycle of the output clock signal;
the input end of phase shift unit 001 is used for inputting an initial clock signal, the output end of phase shift unit 001 is connected with the input end of integer frequency divider 002, the output end of integer frequency divider 002 is connected with the control end of phase control unit 003 for the output end of frequency divider circuit, and the output end of phase control unit 003 is connected with the control end of phase shift unit 001.
In the prior art, for the purpose of realizing that the frequency division ratio of the frequency divider circuit is a decimal number, the frequency division ratio of the frequency divider circuit is usually adjusted by using 1 as a change step diameter, but the problem that the output signal of the frequency divider circuit is easy to fluctuate due to a large change step diameter of the frequency division ratio exists.
In order to solve the above technical problem, the present application provides a frequency divider circuit, which includes a phase shift unit 001, an integer frequency divider 002, and a phase control unit 003. The integer divider 002 divides the frequency of the input clock signal by the edge of the input clock signal, and based on the above principle, the present application delays the phase of the input clock signal
A period of the initial clock signal is realized
The frequency dividing ratio of the frequency divider circuit is adjusted for the purpose of varying the step size.
Fig. 1 is a schematic structural diagram of a frequency divider circuit according to the present invention, where i is an input of the phase control unit 003, Fin is an initial clock signal, and Fbk is an output clock signal.
Specifically, the integer divider 002 realizes a function of dividing the frequency of the initial clock signal by an integer part of the division ratio of the frequency divider circuit, and the phase shift unit 001 generates an offset clock signal having a frequency identical to that of the initial clock signal based on the initial clock signal and having a phase difference of two adjacent offset clock signals of
The phase control unit 003 generates i pulses in each period of the output clock signal of the integer divider 002, and then the phase shift unit 001 outputs the ith shifted clock signal to the integer divider 002, the period of the ith shifted clock signal is identical to that of the initial clock signal, and the phase difference between the phase of the ith shifted clock signal and the i-1 th shifted clock signal is 
Therefore, every time i increases by 1, the output clock signal of the integer divider 002 is delayed
A period of an initial clock signal, is implemented
And adjusting the frequency dividing ratio of the frequency divider circuit for the purpose of changing the step diameter, wherein k can be set according to practical application, and k is a positive integer not less than 2.
In addition, the value of the parameter i in the frequency divider circuit provided by the present application can be adjusted according to the actual usage scenario, and when i is increased by 1 each time, the variation step of the frequency dividing ratio of the frequency divider circuit in the present application is as follows
The fluctuation of the output clock signal is minimum; if the requirement for the accuracy of the output clock signal is relatively low, the degree of i successive increments can be increased appropriately, for example, i is increased by 2 each time, and then the change step of the frequency dividing ratio of the frequency divider circuit in the present application is as follows
。
In summary, the frequency divider circuit provided in the present application changes the variation step diameter of the frequency division ratio from 1 to 1 on the basis of dividing the initial clock signal by any fractional frequency division ratio
Therefore, the jitter of the output signal is reduced, and the stability of the output signal is improved.
On the basis of the above-described embodiment:
as a preferred embodiment, the phase control unit 003 includes a flip-flop 031, a reset unit 032, and a flip-flop control unit;
The input end of the reset unit 032 is the control end of the phase control unit 003, the input end of the flip-flop control unit is the input end of the phase control unit 003, and the positive output end of the flip-flop 031 is the output end of the phase control unit 003;
the output end of the reset unit 032 is connected with the control end of the flip-flop control unit, the output end of the flip-flop control unit is connected with the input end of the flip-flop 031, and the clock signal input end of the flip-flop 031 is connected with the input end of the integer frequency divider 002;
the clock signal input end of the flip-flop 031 is used for inputting a clock signal, and the flip-flop 031 is used for outputting a level corresponding to the input end of the flip-flop 031 when the clock signal is at a rising edge and outputting a low level when the clock signal is at a falling edge;
the reset unit 032 is configured to control the flip-flop control unit to work once in one period of the output clock signal, and the flip-flop control unit is configured to control the level of the input terminal of the flip-flop 031 so that the flip-flop 031 outputs i pulses.
In this embodiment, the phase control unit 003 includes a flip-flop 031, a reset unit 032 and a flip-flop control unit for generating i times pulses in each cycle of the output clock signal.
Specifically, first, the reset unit 032 controls the flip-flop control unit to operate once in a period of the output clock signal, an input end of the flip-flop control unit serves as an input end of the phase control unit 003 for inputting the parameter i, and the level of the input end of the flip-flop 031 is controlled so that the flip-flop 031 outputs i pulses in a period of the output clock signal, when the magnitude of i changes, the number of times that the flip-flop 031 outputs pulses also changes, so that the phase shift unit 001 outputs the phase-delayed shift clock signal, thereby achieving the purpose of fractional frequency division.
In addition, the flip-flop 031 in this application is different from a general D flip-flop, and generally the D flip-flop is configured to output a level corresponding to an input terminal of the flip-flop 031 when a rising edge of a clock signal comes, and hold a value of an output terminal at a previous sampling time at other times; the flip-flop 031 of the present invention is configured to output a level corresponding to an input terminal of the flip-flop 031 when a rising edge of a clock signal arrives, and output a low level when a falling edge of the clock signal arrives and keep the output terminal of the flip-flop 031 until a next rising edge of the clock signal arrives. The specific structure of the flip-flop 031 in this application is not particularly limited as long as the above-described functions can be achieved.
As a preferred embodiment, the trigger control unit includes a thermometer code converter 331 and
a trigger control subunit 332, wherein the trigger control subunit 332 includes a dual-way selector and a first D trigger;
the input of the thermometer code converter 331 is the input of the trigger control unit,
the control terminal of the individual flip-flop control subunit 332 is the control terminal of the flip-flop control unit,
a first input terminal of the flip-flop control subunit 332 and
the output terminals of the trigger control subunits 332 are sequentially connected in series, one end of the series circuit is grounded, the other end of the series circuit is connected with the input terminal of the trigger 031, and the thermometer code converter 331 
An output terminal and
the second input ends of the trigger control subunits 332 are connected in a one-to-one correspondence;
the first input end of the two-way selector is the first input end of the trigger control subunit 332, the second input end of the two-way selector is the second input end of the trigger control subunit 332, the control end of the two-way selector is the control end of the trigger control subunit 332, the output end of the two-way selector is connected with the input end of the first D trigger, the in-phase output end of the first D trigger is the output end of the trigger control subunit 332, and the clock signal input end of the first D trigger is connected with the input end of the integer frequency divider 002;
the thermometer code converter 331 is used for outputting a thermometer code corresponding to i, the number of bits of the thermometer code is
The two-way selector is used for outputting the value of the first input end of the two-way selector when the reset unit 032 outputs the first level, and outputting the value of the second input end of the two-way selector when the reset unit 032 outputs the second level.
Referring to fig. 2 (a) and fig. 2 (b), fig. 2 (a) is a partial circuit diagram of a frequency divider circuit according to the present invention, and fig. 2 (b) is another partial circuit diagram of a frequency divider circuit according to the present invention. In this embodiment, the input terminal of the thermometer code converter 331 is the input terminal of the trigger control unit, i.e. the input terminal of the phase control unit 003, and the parameter i is input through the input terminal of the thermometer code converter 331, and the output of the thermometer code converter is shared 
The output of the bit, thermometer code converter 331 is from the 0 th bit to the 0 th bit
The number of the continuous bits of 1 is equal to the decimal number corresponding to the input parameter iFor example, input i =3, and the output of thermometer code converter 331 is 111.
Of thermometer-coded converters 331
An output terminal and
the second input ends of the two-way selectors are connected in a one-to-one correspondence manner, the control ends of the two-way selectors are connected with the output end of the reset unit 032, the two-way selectors output the values of the first input ends of the two-way selectors when the reset unit 032 outputs a first level, and the two-way selectors output the values of the second input ends of the two-way selectors when the reset unit 032 outputs a second level. When the reset unit 032 outputs the second level, the value of the input end of the first D flip-flop in the flip-flop control subunit 332 is the value of the second input end of the dual-way selector, that is, the value of the corresponding bit in the output of the thermometer code converter, when the clock signal input by the clock signal input end of the first D flip-flop, that is, the next rising edge of the frequency-divided clock signal output by the phase shift unit 001 arrives,
the value of the output of the first D flip-flop is the value output by the thermometer code converter 331. When the rising edge of the frequency-divided clock signal comes, the output of the reset unit 032 changes to the first level, the value of the input end of the first D flip-flop in the flip-flop control sub-unit 332 is the value of the first input end of the dual-way selector, each first D flip-flop constitutes a shift register, when the rising edge of the frequency-divided clock signal comes, the output end of the flip-flop 031 sequentially outputs the value of the output end of each first D flip-flop, and when the falling edge of the frequency-divided clock signal comes, the value of the output end of the flip-flop 031 changes to 0.
In summary, it can be seen that in each cycle of the output signal of reset unit 032, flip-flop 031 outputs a number of pulses equal to the number of 1's in the output of thermometer code converter 331, i.e., i.
As a preferred embodiment, the reset unit 032 comprises a second D flip-flop and an and gate;
the non-inverting input end of the second D flip-flop is the input end of the resetting unit 032, and the output end of the and gate is the output end of the resetting unit 032;
the inverted output end of the second D flip-flop is connected to the first input end of the and gate, and the clock signal input end of the second D flip-flop is connected to the input end of the integer frequency divider 002 and the second input end of the and gate, respectively.
Referring to fig. 2 (a) and fig. 2 (b), fig. 2 (a) is a partial circuit diagram of a frequency divider circuit according to the present invention, and fig. 2 (b) is another partial circuit diagram of a frequency divider circuit according to the present invention. In this embodiment, the reset unit 032 includes a second D flip-flop and an and gate, and the reset unit 032 outputs a reset signal in each cycle of the output clock signal output by the integer frequency divider 002.
Specifically, a clock signal input end of the second D flip-flop inputs a frequency-divided clock signal, a non-inverting input end of the second D flip-flop inputs an output clock signal output by integer frequency division, an inverting output end of the second D flip-flop outputs an inverted signal of a signal obtained by delaying the output clock signal output by the integer frequency divider 002 by T, the signal and the frequency-divided clock signal pass through an and gate and then output a high-level signal having a pulse width of T and a period of Tbk, where T is the period of the initial clock signal and Tbk is the period of the output clock signal output by the integer frequency divider 002.
When the reset unit 032 includes the second D flip-flop and the and gate, the dual selector outputs the value of the first input terminal of the dual selector when the reset unit 032 outputs the low level, and the dual selector outputs the value of the second input terminal of the dual selector when the reset unit 032 outputs the high level.
As a preferred embodiment, the phase shift unit 001 includes a phase generator 011, a multiplexer 012 and a phase shift control module 013, wherein the phase shift control module 013 includes k third D flip-flops;
the input terminal of the phase generator 011 is the input terminal of the phase shift unit 001, and the phase generator 011
The output terminals are connected to the input terminals of the multiplexers 012 in a one-to-one correspondence manner, the output terminal of the multiplexer 012 is the output terminal of the phase shift unit 001, the control terminal of the multiplexer 012 is connected to the output terminal of the phase shift control module 013, and the input terminal of the phase shift control module 013 is the control terminal of the phase shift unit 001;
The clock signal input ends of k third D flip-flops are sequentially connected in series with the in-phase output ends of the k third D flip-flops, the clock signal input end of the first third D flip-flop is the input end of the phase shift control module 013, the in-phase output end of the kth third D flip-flop is the output end of the phase shift control module 013, and the in-phase input end of the third D flip-flop is connected with the reverse output end of the third D flip-flop.
Referring to fig. 2 (a) and fig. 2 (b), fig. 2 (a) is a partial circuit diagram of a frequency divider circuit according to the present invention, and fig. 2 (b) is another partial circuit diagram of a frequency divider circuit according to the present invention. In the present embodiment, the phase generator 011 is configured to generate based on an initial clock signal
An offset clock signal, and
the frequency of each offset clock signal is the same as that of the initial clock signal, and the phase difference between two adjacent offset clock signals is
(ii) a Of multiplexers 012
With input terminals and phase generator 011
The output terminals are connected in a one-to-one correspondence, the output of the multiplexer 012 is controlled by the phase shift control module 013, the phase shift control module 013 generates the phase shift control signal based on the number of pulses output by the phase control unit 003, and the number of pulses output by the phase control unit 003 is i, so that the phase shift unit 001 can control the multiplexer 012 to output the i-th shift clock signal.
Further, the phase generator 011 may be formed of a gill bit cell or a delay locked loop, which is not particularly limited in this application.
As a preferred embodiment, the flip-flop 031 includes a first tri-state inverter 041, a second tri-state inverter 042, a third tri-state inverter 043, a first inverter 051, a second inverter 052, a third inverter 053, a fourth inverter 054, a fifth inverter 055, and a nand gate 006;
the input end of the first tri-state inverter 041 is the input end of the flip-flop 031, the input end of the first inverter 051 is the clock signal input end of the flip-flop 031, and the output end of the fourth inverter 054 is the positive output end of the flip-flop 031;
the clock signal input end of the first tri-state inverter 041, the clock signal input end of the second tri-state inverter 042 and the clock signal input end of the third tri-state inverter 043 are all connected with the input end of the first inverter 051, and the inverted clock signal input end of the first tri-state inverter 041, the inverted clock signal input end of the second tri-state inverter 042 and the inverted clock signal input end of the third tri-state inverter 043 are all connected with the output end of the first inverter 051;
the output end of the first tristate inverter 041 is connected with the output end of the second tristate inverter 042 and the input end of the second inverter 052 respectively, the input end of the second tristate inverter 042 and the output end of the second inverter 052 are connected, the connected common end is connected with the input end of the third tristate inverter 043, the output end of the third tristate inverter 043 is connected with the input end of the third inverter 053, the input end of the fourth inverter 054 and the output end of the NAND gate 006 respectively, the output end of the third inverter 055 is connected with the input end of the fifth inverter 055, the connected common end is connected with the first input end of the NAND gate, and the second input end of the NAND gate 006 is connected with the input end of the first inverter.
Referring to fig. 3, fig. 3 is a circuit diagram of a flip-flop according to the present invention.
The common D flip-flop is a two-stage latch structure formed by a tri-state inverter and an inverter, and the flip-flop 031 in this application replaces the tri-state inverter in the second stage latch of the common D flip-flop with a nand gate. When the rising edge of the clock signal of the flip-flop 031 in this application comes, the flip-flop 031 is in accordance with the principle of a normal D flip-flop, the output of the flip-flop 031 is to sample and hold the input terminal of the flip-flop 031, when the falling of the clock signal of the flip-flop 031 in this application comes, the nand gate outputs a high level, and the output of the fifth inverter 055 is in a high impedance state, then the output of the flip-flop 031 is in a low level.
The invention also provides a frequency synthesizer which comprises the frequency divider circuit.
For the related introduction of the frequency synthesizer provided by the present invention, please refer to the embodiment of the frequency divider circuit, which is not described herein again.
It should be noted that, in the present specification, relational terms such as first and second, and the like are used only for distinguishing one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (6)
1. A frequency divider circuit is characterized by comprising a phase offset unit, an integer frequency divider and a phase control unit;
the phase shift unit is used for generating based on an initial clock signal
An offset clock signal and outputs the ith offset clock signal, wherein i is a parameter input by the input end of the phase control unit,
the frequency of each offset clock signal is the same as that of the initial clock signal, and the phase difference between two adjacent offset clock signals is
I is a positive integer, k is a positive integer not less than 2;
the integer frequency divider is used for generating an output clock signal with the frequency being 1/M of the frequency of the input clock signal based on the input clock signal of the integer frequency divider, wherein M is a positive integer;
The phase control unit is used for generating i times of pulses in one period of the output clock signal;
the input end of the phase deviation unit is used for inputting an initial clock signal, the output end of the phase deviation unit is connected with the input end of the integer frequency divider, the output end of the integer frequency divider is the output end of the frequency divider circuit and is connected with the control end of the phase control unit, and the output end of the phase control unit is connected with the control end of the phase deviation unit;
the phase control unit comprises a trigger, a reset unit and a trigger control unit;
the input end of the reset unit is the control end of the phase control unit, the input end of the trigger control unit is the input end of the phase control unit, and the positive output end of the trigger is the output end of the phase control unit;
the output end of the reset unit is connected with the control end of the trigger control unit, the output end of the trigger control unit is connected with the input end of the trigger, and the clock signal input end of the trigger is connected with the input end of the integer frequency divider;
the clock signal input end of the trigger is used for inputting a clock signal, the trigger is used for outputting the level corresponding to the input end of the trigger when the clock signal is at a rising edge, and outputting the low level when the clock signal is at a falling edge;
The reset unit is used for controlling the trigger control unit to work once in one period of the output clock signal, and the trigger control unit is used for controlling the level of the input end of the trigger so that the trigger can output i-time pulses.
2. The frequency divider circuit of claim 1, wherein the trigger control unit comprises a thermometer code converter and
each trigger control subunit comprises a two-way selector and a first D trigger;
the input end of the thermometer code converter is the input end of the trigger control unit,
the control end of each trigger control subunit is the control end of the trigger control unit,
a first input terminal of the trigger control subunit and
the output ends of the trigger control subunits are sequentially connected in series, one end of the circuit after the series connection is grounded, the other end of the circuit after the series connection is connected with the input end of the trigger, and the thermometer code converter
An output terminal and
the second input ends of the trigger control subunits are correspondingly connected one by one;
the first input end of the two-way selector is the first input end of the trigger control subunit, the second input end of the two-way selector is the second input end of the trigger control subunit, the control end of the two-way selector is the control end of the trigger control subunit, the output end of the two-way selector is connected with the input end of the first D trigger, the in-phase output end of the first D trigger is the output end of the trigger control subunit, and the clock signal input end of the first D trigger is connected with the input end of the integer frequency divider;
The thermometer code converter is used for outputting i corresponding thermometer codes, andthermometer coded number of bits
And the two-way selector is used for outputting the value of the first input end of the two-way selector when the reset unit outputs the first level and outputting the value of the second input end of the two-way selector when the reset unit outputs the second level.
3. The frequency divider circuit of claim 2, wherein the reset unit comprises a second D flip-flop and an and gate;
the non-inverting input end of the second D trigger is the input end of the reset unit, and the output end of the AND gate is the output end of the reset unit;
and the inverted output end of the second D trigger is connected with the first input end of the AND gate, and the clock signal input end of the second D trigger is respectively connected with the input end of the integer frequency divider and the second input end of the AND gate.
4. The frequency divider circuit of claim 3, wherein the phase offset unit comprises a phase generator, a multiplexer, and a phase offset control module, the phase offset control module comprising k third D flip-flops;
the phase generator is used for generating based on the initial clock signal 
-said offset clock signal;
the phase deviation control module is used for generating a phase deviation control signal based on the number of times of the pulse output by the phase control unit;
the multiplexer is used for outputting an offset clock signal corresponding to the phase offset control signal;
the input terminal of the phase generator is the input terminal of the phase shift unit
The output ends of the multi-path selector are connected with the input end of the multi-path selector in a one-to-one correspondence manner, the output end of the multi-path selector is the output end of the phase deviation unit, the control end of the multi-path selector is connected with the output end of the phase deviation control module, and the input end of the phase deviation control module is the control end of the phase deviation unit;
the clock signal input ends of the k third D triggers are sequentially connected with the in-phase output ends of the k third D triggers in series, the clock signal input end of the first third D trigger is the input end of the phase deviation control module, the in-phase output end of the k third D trigger is the output end of the phase deviation control module, and the in-phase input end of the third D trigger is connected with the reverse phase output end of the third D trigger.
5. The frequency divider circuit of claim 4, wherein the flip-flop comprises a first tri-state inverter, a second tri-state inverter, a third tri-state inverter, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, and a NAND gate;
the input end of the first tri-state inverter is the input end of the trigger, the input end of the first inverter is the clock signal input end of the trigger, and the output end of the fourth inverter is the positive output end of the trigger;
the clock signal input end of the first tri-state inverter, the clock signal input end of the second tri-state inverter and the clock signal input end of the third tri-state inverter are all connected with the input end of the first inverter, and the inverted clock signal input end of the first tri-state inverter, the inverted clock signal input end of the second tri-state inverter and the inverted clock signal input end of the third tri-state inverter are all connected with the output end of the first inverter;
the output end of the first tri-state inverter is connected with the output end of the second tri-state inverter and the input end of the second inverter respectively, the input end of the second tri-state inverter and the output end of the second inverter are connected, the public end of the connection is connected with the input end of the third tri-state inverter, the output end of the third tri-state inverter is connected with the input end of the third inverter, the input end of the fourth inverter and the output end of the NAND gate respectively, the output end of the third inverter is connected with the input end of the fifth inverter, the public end of the connection is connected with the first input end of the NAND gate, and the second input end of the NAND gate is connected with the input end of the first inverter.
6. A frequency synthesiser comprising a frequency divider circuit as claimed in any one of claims 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210139588.3A CN114204937B (en) | 2022-02-16 | 2022-02-16 | Frequency divider circuit and frequency synthesizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210139588.3A CN114204937B (en) | 2022-02-16 | 2022-02-16 | Frequency divider circuit and frequency synthesizer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114204937A CN114204937A (en) | 2022-03-18 |
| CN114204937B true CN114204937B (en) | 2022-06-14 |
Family
ID=80658993
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210139588.3A Active CN114204937B (en) | 2022-02-16 | 2022-02-16 | Frequency divider circuit and frequency synthesizer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114204937B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003188719A (en) * | 2001-12-18 | 2003-07-04 | Seiko Epson Corp | Frequency divider circuit |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2666184A1 (en) * | 1990-08-24 | 1992-02-28 | Alcatel Radiotelephone | CLOCK WITH DIVISION OF FRACTIONAL FREQUENCY AND SERVING THIS CLOCK. |
| DE10125155C1 (en) * | 2001-05-22 | 2002-11-28 | Infineon Technologies Ag | Programmable fractional frequency divider has different phase offset signals switched through to output of phase selection device in programmed sequence |
| CN1996762A (en) * | 2005-12-26 | 2007-07-11 | 中兴通讯股份有限公司 | A number frequency divider |
| CN101378259A (en) * | 2007-08-31 | 2009-03-04 | 锐迪科微电子（上海）有限公司 | Phase selection programmable frequency divider |
| KR100975040B1 (en) * | 2008-09-02 | 2010-08-11 | 고려대학교 산학협력단 | Programmable frequency divider and Method of frequency dividing |
| CN104363015A (en) * | 2014-10-08 | 2015-02-18 | 四川和芯微电子股份有限公司 | Fractional frequency divider circuit |
| CN111510139A (en) * | 2020-04-27 | 2020-08-07 | 中科威发半导体（苏州）有限公司 | Frequency divider, control method of frequency divider, phase-locked loop, and semiconductor device |
-
2022
- 2022-02-16 CN CN202210139588.3A patent/CN114204937B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003188719A (en) * | 2001-12-18 | 2003-07-04 | Seiko Epson Corp | Frequency divider circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114204937A (en) | 2022-03-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3169794B2 (en) | Delay clock generation circuit | |
| US7224199B1 (en) | Circuit and method for digital delay and circuits incorporating the same | |
| KR101165491B1 (en) | Multiple reference clock synthesizer | |
| JP4780144B2 (en) | Frequency divider circuit | |
| JPH0897715A (en) | Digital pll circuit | |
| KR0159213B1 (en) | Variable delay circuit | |
| US6031401A (en) | Clock waveform synthesizer | |
| CN114629476A (en) | High resolution pulse width modulation signal generating circuit | |
| CN111416619B (en) | Time delay measuring circuit, time delay measuring method, electronic equipment and chip | |
| US7358782B2 (en) | Frequency divider and associated methods | |
| US7180339B2 (en) | Synthesizer and method for generating an output signal that has a desired period | |
| CN110289856B (en) | Dynamic phase shift and decimal frequency division system based on PLL circuit | |
| CN114204937B (en) | Frequency divider circuit and frequency synthesizer | |
| US10749531B1 (en) | Multi-modulus frequency divider circuit | |
| US10742220B1 (en) | Method and apparatus for operating programmable clock divider using reset paths | |
| CN114967411B (en) | Multi-stage time-to-digital converter with automatic reset mechanism | |
| CN108039885B (en) | High-speed frequency division method and high-speed frequency divider with duty ratio adjusting function | |
| US7436725B2 (en) | Data generator having stable duration from trigger arrival to data output start | |
| US7733152B2 (en) | Control signal generating circuit enabling value of period of a generated clock signal to be set as the period of a reference signal multiplied or divided by an arbitrary real number | |
| CN207896958U (en) | A kind of high-speed frequency divider with duty cycle adjustment function | |
| CN207896957U (en) | A kind of high-speed frequency divider | |
| CN111490776A (en) | Counter duty ratio adjustable synchronous frequency divider | |
| TW201014187A (en) | All digital fast-lock self-calibrated multiphase delay-locked loop | |
| CN114095018B (en) | Decimal frequency dividing circuit | |
| CN108111163B (en) | High-speed frequency divider |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |