FR2666184A1 - CLOCK WITH DIVISION OF FRACTIONAL FREQUENCY AND SERVING THIS CLOCK. - Google Patents

Abstract

A fractional frequency division clock comprising a division circuit (2) which generates a clock signal (Ck) from a timing signal (R), the frequencies of these two signals being in a division ratio (Q ) which is the sum of an integer part and a fractional part (F), a pulse absorber (1) receiving said rhythm signal and transmitting it to said division circuit (2) by removing a pulse of at least this signal on command, and accumulation means (3) for controlling said pulse absorber (1) each time the product of the number of pulses of said clock signal (Ck) counted from an instant original and said fractional part changes unit. Application in particular to the field of telecommunications systems.

Description

-t Fractional Frequency Division Clock and Slave Control

  The present invention relates to a fractional frequency division clock and means for controlling this clock on a synchronization signal. Most of the electronic circuits are now designed to operate with a clock signal of a specific frequency produced by an oscillator. When an equipment includes circuits intended to operate with different clock signals, a first solution is to provide it with oscillators in number equal to that of the clock signals This solution is obviously not economical. It is often used, when the frequency of a first of these signals, is not a multiple of that of a second of these signals to a fractional frequency division clock Such a clock, when made entirely in digital technology, produces a signal whose average frequency over a recurrence period is the frequency of the signal it receives divided by a

division report.

  It is thus known to use a programmable counter receiving a timing signal and provided to periodically deliver, according to the recurrence period, a first and a second successive series of pulses, the repetition frequencies of these two series being sub-multiples of the frequency of the timing signal Such a device, in addition to the programmable counter, requires two additional counters to determine the number of pulses of each series and control means. It therefore occupies, in the case of an embodiment in integrated form, a relatively large substrate surface, which is an obstacle to the miniaturization of the equipment in which it is implanted. In addition, the phase shift between its output signal and a signal whose frequency is exactly in the division ratio of that of the timing signal is widely variable and can have a high amplitude. A first object of the present invention is the realization of a fractional frequency division clock having a reduced size thanks to the use of simpler elementary circuits and whose output signal has a limited phase shift with the desired frequency. This phase shift, in a preferred embodiment, is

  less than one period of the rhythm signal.

  In certain fields of application, in particular in the reception equipment of telecommunication systems, it is necessary to slave the output signal of this clock on a signal

synchronization.

  The present invention therefore also relates to servo-control means specially adapted for this type of division clock.

fractional frequency.

  Although it should not be seen as a limitation of the invention, it will advantageously be used in the context of the European digital cellular radiocommunication system. A mobile terminal of this system indeed comprises a coding and decoding device. speech which can be realized by means of a standard component operating with 8 kHz and 2048 kHz clock signals. The terminal furthermore comprises an internal clock producing a 13 MHz clock signal and generates a clock signal. 50 Hz synchronization signal on which the coding and decoding member must be synchronized The invention thus makes it possible, from the timing signal, to produce the signals

  synchronized clock on the synchronization signal.

  The fractional frequency division clock according to the invention comprises a division circuit which produces a clock signal from a timing signal, the frequencies of these two signals being in a division ratio which is the sum of an integer part and a fractional part, and is characterized in that it comprises a pulse absorber receiving the timing signal and transmitting it to the dividing circuit by suppressing at least one pulse of this signal on command, and accumulating means for controlling the pulse absorber each time the product of the number of clock signal pulses counted from an instant of origin and said

  fractional part changes unit.

  In addition, in the fractional frequency division clock, the division ratio is the sum of the product of a first division factor and the fractional part and the product of a second division factor and the complement. at one of the fractional part, the accumulation means comprise an accumulation register producing a first operand which takes the value of an addition signal in response to the clock signal and an addition circuit producing this signal. addition as the sum modulo the denominator of the fractional part of the first operand and a second operand comprising at least the numerator of the fractional part and producing a retaining signal, said pulse absorber being designed to absorb a number of pulses equal to the difference of said two dividing factors in response to the hold signal. Furthermore, the fractional frequency division clock being designed to be slaved to a synchronization signal, it comprises a servo module receiving this synchronization signal and said clock signal and producing a correction signal, the second operand being the sum of the numerator and the

correction signal.

  Thus, when the frequency of said clock signal is a multiple of that of the synchronization signal, the servo module comprises means for producing a count value corresponding to the number of pulses of said holographic signal that appeared during a period of time. fixed duration measurement, means for producing a correction value proportional to the difference of a second and a first count value and inversely proportional to the time separating the medium from the second and the first corresponding measurement periods, the correction signal, usually zero, being assigned the correction value during a correction period

  expressed as a number of periods of the clock signal.

  Moreover, in the fractional frequency division clock, the measurement period being a multiple of the period of the synchronization signal, the corresponding first and second measurement periods being consecutive, the servocontrol module comprises a counter receiving the signal d clock and producing a phase signal, the capacitance of this counter being a sub-multiple of the ratio of the frequencies of the clock and synchronization signals, comprises a summing circuit producing the second count value as the sum of values taken by the phase signal at the timing of the synchronization signal, a timer register producing the first count value as the second count value with a delay of one measurement period, a subtraction circuit producing a difference signal as the difference of said second and first count values, and a correction module producing the value of

  correction in proportion to the phase difference signal.

  Advantageously in the fractional frequency division clock, an elementary output of the counter is used to

  produce an auxiliary clock signal.

  In an alternative embodiment, the fractional frequency division clock further comprises a compensation circuit which now produces the correction value as the sum of the values of the output signal of the correction module during the measurement period.

  previous period and the current measurement period.

  In addition, in the fractional frequency division clock, the compensation circuit includes a limiting saturation adder

  said correction value to a determined maximum value.

  In an advantageous embodiment, the fractional frequency division clock comprises a limiting circuit affecting the correction value correction signal during the first appearance of a determined state of a counter elementary output following the beginning. of a period of the synchronization signal, the

  correction signal being zero during the remainder of the period.

  On the other hand, the fractional frequency division clock comprises a synchronization register producing as a measurement signal the phase signal in response to a trigger signal from a trigger circuit whose output takes the value of the said signal. synchronization on command of the clock signal, the signal of

  measurement being addressed to the summing circuit.

  According to an additional characteristic, the fractional frequency division clock comprises a control circuit producing a control signal whose period is equal to the measuring period, this control signal causing the resetting of the summing circuit, the transfer from the input to the output of the timer register and the

  modification of the output signal of the compensation circuit.

  Advantageously, the fractional frequency division clock receives an initialization signal intended to initialize the compensation circuit. In addition, the fractional frequency division clock includes an initialization circuit imposing on the counter, a starting value

  in response to the initialization signal.

  In a particular case of the frequency division clock

  fractional the whole part of the division report is zero.

  It is further possible to provide in the fractional frequency division clock that the difference of the two division factors is equal to unity, the pulse absorber suppressing a single

pulse on command.

  The different objects and features of the present invention

  will appear more precisely as part of the description

  embodiments given by way of non-limiting example with reference to the appended figures which represent: FIG. 1, a block diagram of a fractional frequency division clock according to the invention,

  Figure 2, the diagram of a servo module of this clock.

  Fractional frequency division clocks receive a timing signal and produce a clock signal and are provided so that the frequencies of these signals are in a division ratio Q. This ratio can always be broken down as the sum of the product of a first division factor A and a fractional part F and the product of a second division factor B and the complement to one of this fractional part, where the division factors are integers and the fractional part is an integer number between zero and one

Q = A F + B (1-F)

  The different numbers can be further chosen such that the difference of the two dividing factors is equal to unity

A = B + 1

  Moreover, the fractional part can be represented in the form -6 of a fraction including a numerator N and a denominator D

F = N / D

  The invention described below applies regardless of the value

of these different numbers.

  By way of example, in order to clarify the disclosure, the invention will be presented in connection with a concrete case of application concerning the cellular radiocommunication digital system In this case a mobile terminal is provided with an internal oscillator which produces the clock signal at a frequency of 13 M Hz From this signal, the clock signal used in particular for speech processing circuits at a frequency of 2.048 M Hz must be generated. The division ratio is therefore:

Q = 6.34765625

Q = 6 + 89/256

= 6 (256 89) + 7 (89)

256,256

  By repeating the previous notations

A = 7 B = 6 F = 89

N = 89 D = 256

  The fractional frequency division clock of the invention shown in FIG. 1 comprises a pulse absorber 1 which receives the timing signal R and the output of which is connected to the input of a dividing circuit 2 which produces the clock signal Ck It also comprises accumulation means 3 receiving this clock signal and controlling the pulse absorber by a retaining signal C, these means being provided to limit the phase shift of the signal

  clock as it will appear later.

  Pulse absorber 1 transmits directly to its output the timing signal R, except when it receives the retaining signal C In

  the latter case it suppresses a pulse of the rhythm signal.

  The division circuit 2 produces the clock signal Ck whose frequency is a submultiple of that of the signal applied to its input. This submultiple is equal to the second division factor B, 6 in the present case. for example, and when it divides by an even number, it will advantageously be a ring counter also known as the "Johnson" counter. A counter of this type is produced by the series setting of flip-flops. , the first of them receiving the output signal of the latter which is the clock signal Ck The submultiple is here double the number of flip-flops. The accumulation means 3 are designed to trigger the pulse absorber 1 each time the product of the fractional part F and a pulse number of the clock signal counted from an instant of origin changes unit, that is to say, when its integer part increases by one unit. This instant of origin is fixed arbitrarily, it constitutes only a reference of time.

  be, for example, the time of commissioning of the clock.

  These accumulation means 3 in a particular embodiment which should not be considered as a limitation of the invention

  comprises an addition circuit 31 and an accumulation register 32.

  The accumulation register 32 produces a first operand which has the value that had an addition signal S during the appearance of the

  last pulse of the clock signal Ck.

  The addition circuit 32 produces this addition signal S as the sum of the first operand and a second operand modulo the denominator D of the fractional part F. The second operand in this first part of the invention takes the value of N numerator N of this fractional part F This circuit is further provided to deliver the retaining signal C to the pulse absorber 1,

  when this sum is greater than the denominator.

  Thus, whenever the product of the numerator and the number of pulses of the clock signal becomes greater than a multiple of the denominator to which it was previously lower, a pulse of the clock signal is suppressed, which amounts to dividing by the first division factor A.

  In the numerical example considered, the denominator is equal to 256.

  The addition circuit can therefore consist of a simple adder

  providing an 8-bit output signal and a hold signal.

  The invention applies if the division ratio is reduced to the fractional part, that is, if the first A and second B division factors are respectively 1 and 0. In this case the dividing circuit 2 is reduced to a simple link, the signal

  clock Ck being the output signal of the pulse absorber 1.

  It also applies if these dividing factors differ by more than one unit. It is then sufficient to provide the impulse absorber 1 so that it absorbs a number of pulses equal to the difference of these two factors. is within the reach of those skilled in the art

will not be more detailed.

  According to an additional characteristic of the invention, the fractional frequency division clock is designed to be servocontrolled by a servo module on a synchronization signal whose

  frequency is a sub-multiple of that of the clock signal.

  This servo module is designed to record the number of pulses of the clock signal Ck during a fixed value measurement period. It produces a first count value during a first measurement period, then a second count value during a first measurement period. second measurement period It then calculates a correction value which is proportional to the difference of these two count values and inversely proportional to the time separating the media from the two corresponding measurement periods Finally, it produces a correction signal which takes this value of correction during a correction period and which is zero the rest of the time This correction signal is added to the numerator N of the fractional part F for

  forming the second operand 2 of the addition circuit 31.

  This servo module 4 appears in an embodiment given solely for information purposes in FIG.

  bodies that will now be detailed.

  A counter 40 receives the clock signal Ck and produces a phase signal P which corresponds to the number of pulses that have appeared since its reset. The capacity of this counter is a sub-multiple of the frequency ratio of the clock signal Ck and a synchronization signal T. A trigger circuit 41 produces a trigger signal D which takes the value that had the synchronization signal T when the last pulse of the clock signal Ck appears. for example, a flip-flop known as flip-flop D. A synchronization register 42 produces a measurement signal Pe which has the value that the phase signal P had during the appearance of the last pulse of the signal A control circuit 43 produces a periodic control signal L whose period is worth the measurement period. Advantageously, this measurement period will be a multiple of the period of the synchronization signal. A summing circuit 44 delivers the second count value P 2 which is the sum of the values taken by the measurement signal Pe during each pulse of the synchronization signal T This circuit is reset by the control signal L It will appear more clearly now why the output signal of this circuit is the second

count value.

  A delay register 45 produces the first count value P1 as the second count value delayed by a measurement period, that is to say by a control signal period L Thus the adopted denomination is justified since given moment, the output signal of this register has the value that had the output signal of the

  summing circuit 44 during the previous measurement period.

  A subtraction circuit 46 produces a phase difference signal E

  as the difference of the two count values: P 2 Pl.

  A correction module 47 produces an output signal whose value is that of the phase difference signal E divided by the ratio between the measurement period and the period of the synchronization signal T and multiplied by a constant that is denominated commonly coefficient

servo stiffness.

  A compensation circuit 48 produces a correction value m which is the sum of the values of the output signal of the correction module 47 during the preceding measurement period and during the current period. This circuit is intended to limit this correction value to a maximum value It will include, for example, a saturation adder which produces the sum of the two values or this maximum value if this sum is greater than it. This circuit is also intended to be initialized by means of an initialization signal I. A circuit The correction signal M produces the correction signal M which has the correction value m during a correction period and which is zero the rest of the time. This correction period may be of any value and will be determined by those skilled in the art. This correction signal M is added with an adder not represented in the figure to the numerator N of the fractional part F

  to give the second operand 02.

  It is finally provided, as an accessory, that the counter 40 is initialized to a starting value IT by means of an initialization circuit 50 controlled by the initialization signal I on appearance of the synchronization signal T. In a variant of the clock, the counter 40 is furthermore provided for delivering an auxiliary clock signal H on the output of one of these counting cells. This auxiliary clock signal is in synchronism with the clock signal and , just like this, it is slaved on the synchronization signal T. This variant finds an advantageous application in the case of the previously mentioned mobile terminal Indeed some components for speech processing operate with a signal at 2.048 MHz and a signal at 8 k Hz which is the frequency of speech sampling In addition these signals must be slaved on the synchronization signal at 50 Hz produced in the terminal corresponding to the

rhythm of communication frames.

  In this case, the capacity of the counter 40 will be chosen equal to 256, the most significant bit corresponding to the auxiliary clock signal H to

a frequency of 8 kHz.

  It appears that the count values P 1, P 2, in this case, are not equal to the number of pulses of the clock signal C k produced during the corresponding measurement periods, since the counter 40 has completed several cycles (160 in this case) during a period of the synchronization signal These count values, on the other hand, correspond to these numbers of pulses since they are congruent (modulo 256 in this case) Given the small frequency difference that there is a between the clock signal when it is slave and 11 - when it is not, the capacity of the counter is sufficient If this was not the case it is always possible to increase the capacity of this counter in order to widen the possible range of correction, its capacity being limited to the ratio of the frequencies of the clock signal and the synchronization signal. An advantageous solution is to realize the limiting circuit 49 so that the correction period is the period of the auxiliary clock signal H The correction signal is affected by the correction value during this period and is zero during the remainder of the synchronization signal period T This operation is repeated

  periodically to the rhythm of the synchronization signal, for example.

  In this case, if the servocontrol must make it possible to obtain a relative frequency difference between the auxiliary holographic signal and the synchronization signal of less than 5 parts per million, the value of

  correction can take one of the values -2, -1, 0, 1 or 2.

  In fact, during a period of the synchronization signal for which the correction value is equal to 2, during a period of the auxiliary clock signal, the division ratio is equal to Qc = 6 + 91/256, while during the other 159 periods, it is worth Qo = 6 + 89/256 The frequency difference is therefore Qc Qo * 7.68 10-6 Qo The second operand 02 which is the sum of the correction value

  and the numerator will be an integer between 87 and 91.

  The adder which produces this second operand can be reduced to a simple combinatorial circuit which produces the 4 low-order bits of this operand, its 3 most significant bits being invariable. Indeed, the decimal values that this operator can take express themselves. as follows in binary numbering

87 = 101 0111

88 = 101 1000

89 = 101 1001

= 101 1010

91 = 101 1011

  Moreover, it will be noted that the retaining signal C of the addition circuit 33 is periodic Its period corresponds to 256 pulses of the clock signal Ck It follows that the auxiliary clock signal which has the same period has the same value. particularity that all its pulses have the same phase shift because they are separated by the same number of periods of the timing signal R Thus, when the auxiliary clock signal is used as a sampling signal, it does not introduce

  of parasitic modulation on the signal that is samples.

  Another advantage of the invention lies in the fact that the temporal division of the divisions by the first A and by the second B division factor is as uniform as possible. In the numerical example chosen (A = 7, B = 6), the maximum phase difference between the clock signal Ck and the timing signal also called phase jitter,

  is worth a period of the rhythm signal is 76.9 ns.

  The embodiment of the servo-control module 4 that has been described has a very complete structure that provides the advertised performance. The invention also applies if certain members are deleted. Indeed, the tripping circuit 41 is not strictly necessary, it only makes it possible to synchronize the synchronization register 42 on the clock signal Ck. It can be suppressed by directly controlling this register with the synchronization signal T instead of triggering signal D. It is also not necessary to record the count values Pl, P 2 over several periods of the synchronization signal T, although this improves the accuracy of the servocontrol In this case, the control circuit 43 is unnecessary, as is the summing circuit 44 The second counting value P 2 is equal to the measuring signal Pe which is applied directly to the input of the delay register 45 in place of the output signal of the summing circuit This synchronization register is controlled by the synchronization signal T instead of the control signal L, which is also the case for the

compensation circuit 48.

  In addition, this compensation circuit can also be eliminated, the output of the correction module 47 being directly connected to the input

of the limiting circuit 49.

13-

Claims (12)

  1 / Fractional frequency division clock comprising a division circuit (2) which produces a clock signal (Ck) from a timing signal (R), the frequencies of these two signals being in a division ratio (Q) which is the sum of an integer part and a fractional part (F), characterized in that it comprises a pulse absorber (1) receiving said timing signal and transmitting it to said division circuit ( 2) suppressing at least one pulse of this command signal, and accumulation means (3) for controlling said pulse absorber (1) each time the product of the number of pulses of said clock signal ( Ck) counted from a moment of origin and said fractional part changes unit. 2 / fractional frequency division clock according to claim 1 characterized in that, said division ratio (Q) being the sum of the product of a first division factor (A) and said fractional part (F) and from the product of a second division factor (B) and the complement to one of said fractional part, said accumulation means (3) comprises an accumulation register (32) producing a first operand (01) which takes the value an addition signal (S) in response to said clock signal (Ck) and an adding circuit (33) producing said addition signal as the sum modulo the denominator (D) of said fractional part of said first operand (01) and a second operand (02) comprising at least the numerator (N) of said fractional part (F) and producing a retaining signal (C), said pulse absorber (1) being provided to absorb a number of pulses equal to the difference of said ow   division factors in response to said hold signal (C).   3 / fractional frequency division clock according to claim 2, characterized in that, being provided to be slaved to a synchronization signal (T), it comprises a servo module (4) receiving this synchronization signal and said signal clock (Ck) and producing a correction signal (M), said second operand (02)   being the sum of said numerator (N) and said correction signal.   4 / fractional frequency division clock according to claim 14 - 3, characterized in that, the frequency of said clock signal (Ck) being a multiple of that of said synchronization signal (T), said servo module (4 ) comprises means for generating a count value corresponding to the number of pulses of said holographic signal (Ck) occurring during a fixed duration measurement period, means for producing a correction value (m) proportional to the difference in time a second (P 2) and a first (P 1) count value and inversely proportional to the time separating the medium from the second and the first corresponding measurement periods, said correction signal (M) usually zero, being assigned said correction value (m) during a correction period expressed as a number   periods of said clock signal (Ck).   Fractional frequency division clock according to claim 4, characterized in that said measurement period being a multiple of the period of said synchronization signal (T), said first and second corresponding measurement periods being consecutive, said servo module (4) comprises a counter (40) receiving said clock signal (Ck) and producing a phase signal (P), the capacity of said counter being a submultiple of the frequency ratio of said clock signals (Ck) and of synchronization (T), comprises a summation circuit (44) producing said second count value (P 2) as the sum of the values taken by said phase signal (P) at the rate of said synchronization signal (T), a timing register (45) producing said first count value (P 1) as said second count value with a delay of said measurement period, a subtraction circuit (46) producing an output signal phase art (E) as the difference of said second and first count values, and a correction module (47) producing said correction value   (m) in proportion to said phase difference signal (Pe).   6 / fractional frequency division clock according to claim, characterized in that an elementary output of said counter (40) is   used to produce an auxiliary clock signal (H).   7 / fractional frequency division clock according to claim 6, characterized in that it further comprises a compensation circuit (48) now producing said correction value (m) - as the sum of the values of the output signal of said correction module (47) during the previous measurement period and the period current measurement.   8 / fractional frequency division clock according to claim 7, characterized in that said compensation circuit (48) comprises a saturation adder limiting said correction value (m) to a maximum value determined.   9 / Fractional frequency division clock according to any one of   Claims 5 to 8, characterized in that it comprises a circuit   limiting device (41) affecting said correction signal (M) of said correction value (m) during the first occurrence of a determined state of an elementary output of said counter (40) following the beginning of a period of said signal synchronization (T), said signal of   correction being zero during the rest of the said period.   10 / Fractional frequency division clock according to any one of   Claims 5 to 9, characterized in that it comprises a   synchronization register (42) producing as said measurement signal (Pe) said phase signal (P) in response to a trigger signal (D) from a trigger circuit (41) whose output takes the value of said signal of synchronization (T) on command of said clock signal (Ck), said measurement signal being addressed to said summing circuit (44).   11 / fractional frequency division clock according to claim, characterized in that it comprises a control circuit (43) producing a control signal (L) whose period is equal to said measurement period, the control signal causing the delivery at zero of said summing circuit (44), transferring the input to the output of said delay register (45) and changing the output signal   said compensation circuit (48).   12 / Fractional frequency division clock according to any one of   Claims 5 to 11, characterized in that it receives a signal   initialization circuit (I) provided for initialising said circuit of compensation (48).   13 / fractional frequency division clock according to claim 12, characterized in that it comprises an initialization circuit (50) 16 - imposing on said counter (40) a starting value in response to said initialization signal (I).   14 / Fractional frequency division clock according to any one of   Claims 1 to 13, characterized in that the entire part   said division ratio (Q) is zero.   Fractional frequency division clock according to one of Claims 2 to 13, characterized in that the difference between the two   division factors (A, B) is equal to unity, said absorber   pulses (1) suppressing a single command pulse.