CN110289856B

CN110289856B - Dynamic phase shift and decimal frequency division system based on PLL circuit

Info

Publication number: CN110289856B
Application number: CN201910590758.8A
Authority: CN
Inventors: 苏志刚; 王海力; 陈子贤; 马明
Original assignee: Jingwei Qili Beijing Technology Co ltd
Current assignee: Jingwei Qili Beijing Technology Co ltd
Priority date: 2019-07-02
Filing date: 2019-07-02
Publication date: 2023-01-24
Anticipated expiration: 2039-07-02
Also published as: CN110289856A

Abstract

The invention discloses a dynamic phase shift and decimal frequency division system based on a PLL circuit, which comprises: voltage-controlled oscillator, phase shift and decimal frequency dividing circuit and output frequency divider. Selecting an nth first clock signal from the M first clock signals as a second clock signal according to the phase selection signal; receiving an external control signal, and carrying out dynamic phase shift or decimal frequency division on the nth first clock signal; performing addition operation on the first integer frequency division signal according to an external control signal to obtain a second integer frequency division signal; and performing integer frequency division on the second clock signal according to the second integer frequency division signal to obtain a third clock signal. Determining the precision of phase shift and fractional frequency division according to the number of the first clock signals; the design complexity and the layout area of the circuit are effectively reduced.

Description

Dynamic phase shift and decimal frequency division system based on PLL circuit

Technical Field

The invention relates to the field of signal delay, in particular to a dynamic phase shift and decimal frequency division system based on a PLL circuit.

Background

Currently, a phase-locked loop (PLL) is widely used in an integrated circuit for processing a clock signal. In many cases, the PLL transmit clock requires a strict phase requirement to complete the sampling operation and minimize the bit error rate, in addition to the need for accurate frequency. With a phase-selective PLL architecture using a ring-shaped voltage-controlled oscillator, ringvco can generate typically 6-16 output clocks of different phases, which are fed to an output frequency divider and the output phase is selected by a phase selection signal phase sel, while the output frequency is controlled by an integer divider signal div sel. In practical circuits, the delays of the clock path and the data path are difficult to match very well, so that the dynamic phase shift function is very important, which makes it very convenient for a user to fine-tune the phase of the output clock to find the most suitable sampling position. In other cases where a PLL is required to perform fractional frequency division, sigma-delta circuits are often used to perform this function. However, the frequency dividing ratio is not required to be very accurate many times, and then the continued use of the sigma-delta circuit increases the design complexity and the layout area.

Disclosure of Invention

The invention aims to solve the defects in the prior art.

In order to achieve the purpose, the invention discloses a dynamic phase shifting and fractional frequency division system based on a PLL circuit.

The system comprises: the device comprises a voltage controlled oscillator VCO, a phase shift and fractional frequency division circuit and an output frequency divider DIV. Wherein the content of the first and second substances,

and the voltage-controlled oscillator VCO is used for sending the M first clock signals to a receiving end of the phase-shifting and fractional frequency division circuit.

The phase shift and fractional frequency division circuit is used for selecting the nth first clock signal from the M first clock signals as a second clock signal ck _ sel according to a phase selection signal phase _ sel; and also for receiving control signals, comprising: the phase shift circuit control signal and the frequency division circuit control signal frac carry out dynamic phase shift or decimal frequency division on the nth first clock signal; and is further configured to add the first integer divided signal div _ sel _1 according to the frac to obtain a second integer divided signal div _ sel _2.

And the output frequency divider DIV is used for performing integer frequency division on ck _ sel according to DIV _ sel _2 to obtain a third clock signal.

Wherein M, n is a positive integer, M is not less than n.

In one embodiment, the phase shift and fractional division circuit is further configured to receive an external fractional division reset signal int _ done to complete fractional division.

In one embodiment, a phase shift and fractional division circuit comprises: the circuit comprises a state machine circuit, a dynamic phase shift control circuit, a decimal frequency division control circuit, a first data selector, a second data selector, a third data selector and a fourth data selector.

Further, the state machine circuit is configured to process the phase selection signal phase _ sel according to the state machine direction signal dir and the state machine clock signal ck to obtain a first selection control signal sel _ ck and a second selection control signal sel _ next; wherein, the first and the second end of the pipe are connected with each other,

sel _ ck is a control code of M bits, the nth bit in the control code of M bits is an enable bit, and the control code is used for controlling the first data selector to select the nth first clock signal from the M first clock signals as ck _ sel;

sel _ next is a control code of M bits, and the n ± 1 th bit of the control code of M bits is an enable bit for controlling the second data selector to select the first clock signal adjacent to the nth first clock signal as the fourth clock signal ck _ next.

Further, the fractional division control circuit is configured to obtain a fractional division enable signal frac _ en according to the frequency division circuit control signal frac. The frac _ en judging state machine circuit receives the clock signal and the direction signal output by the dynamic phase shift control circuit to carry out dynamic phase shift, or receives the clock signal and the direction signal output by the decimal frequency division control circuit to carry out decimal frequency division.

Further, the fractional frequency division control circuit is further configured to obtain a fractional frequency division direction signal dir _ frac and a fractional frequency division clock signal ck _ frac according to the frequency division circuit control signal frac; when communicating with the state machine circuit, dir _ frac is used as a direction signal of the state machine circuit, and ck _ frac is used as a clock signal of the state machine circuit.

Further, the dynamic phase shift control circuit is used for obtaining a phase shift direction signal dir _ ps and a phase shift clock signal ck _ ps according to the phase shift circuit control signal; when the state machine circuit is communicated, dir _ ps is used as a direction signal of the state machine circuit, and ck _ ps is used as a clock signal of the state machine circuit.

The invention has the advantages that: determining the precision of phase shift and decimal frequency division according to the number of the phases of the VCO output clock; when the circuit design with low frequency dividing ratio is carried out, the design complexity and the layout area of the circuit are effectively reduced.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a block diagram of a dynamic phase shifting and fractional frequency division system based on a PLL circuit;

FIG. 2 is a schematic diagram of a phase shifting and fractional frequency division circuit according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a state machine circuit according to an embodiment of the invention;

FIG. 4 is a schematic diagram of a dynamic phase shift control circuit according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a fractional-N control circuit according to an embodiment of the present invention;

FIG. 6 is a timing diagram of the input of the low potential control signal according to the embodiment of the present invention;

FIG. 7 is a timing diagram illustrating a left shift phase according to an embodiment of the present invention;

FIG. 8 is a timing diagram illustrating a phase shift to the right according to an embodiment of the present invention;

FIG. 9 is a timing diagram of frequency division by 3.25 according to an embodiment of the present invention;

fig. 10 is a timing diagram of frequency division by 3.5 according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Fig. 1 is a block diagram of a dynamic phase shifting and fractional frequency division system based on a PLL circuit, as shown in fig. 1. The system comprises: the system comprises a voltage controlled oscillator VCO, a phase shift and fractional frequency division circuit and an output frequency divider DIV; wherein the content of the first and second substances,

The phase shift and decimal frequency division circuit is used for selecting the nth first clock signal as a second clock signal ck _ sel according to a phase selection signal phase _ sel; and also for receiving control signals, comprising: a phase shift circuit control signal and a frequency division circuit control signal frac for dynamically shifting the phase or dividing the fractional frequency of the nth first clock signal; the frequency divider circuit is further configured to perform addition operation on the first integer frequency-divided signal div _ sel _1 according to the frequency-dividing circuit control signal frac to obtain a second integer frequency-divided signal div _ sel _2;

the output frequency divider DIV is used for carrying out integer frequency division on ck _ sel according to DIV _ sel _2 to obtain a third clock signal;

wherein M, n is a positive integer, M is not less than n.

In one embodiment, as shown in FIG. 2. The phase shift and fractional frequency division circuit includes: the device comprises a state machine circuit, a dynamic phase shift control circuit, a decimal frequency division control circuit, a first data selector, a second data selector, a third data selector and a fourth data selector; wherein, the first and the second end of the pipe are connected with each other,

the state machine circuit is used for processing phase _ sel according to the state machine direction signal dir and the state machine clock signal ck to obtain a first selection control signal sel _ ck and a second selection control signal sel _ next; the first data selector is used for selecting an n-th first clock signal from the M first clock signals as ck _ sel; sel _ next is a control code of M bits, of which n ± 1 bits are enable bits for controlling the second data selector to select the first clock signal adjacent to the nth first clock signal as the fourth clock signal ck _ next.

And the fractional division control circuit is used for obtaining a fractional division enable signal frac _ en according to frac. The frac _ en judging state machine circuit receives the clock signal and the direction signal output by the dynamic phase shift control circuit to carry out dynamic phase shift, or receives the clock signal and the direction signal output by the decimal frequency division control circuit to carry out decimal frequency division.

The decimal frequency division control circuit is also used for obtaining a decimal frequency division direction signal dir _ frac and a decimal frequency division clock signal ck _ frac according to the frac; when communicating with the state machine circuit, dir _ frac is used as a direction signal of the state machine circuit, and ck _ frac is used as a clock signal of the state machine circuit.

The dynamic phase-shifting control circuit is used for obtaining a phase-shifting direction signal dir _ ps and a phase-shifting clock signal ck _ ps according to the phase-shifting circuit control signal; when the state machine circuit is communicated, dir _ ps is used as a direction signal of the state machine circuit, and ck _ ps is used as a clock signal of the state machine circuit.

The specific processing of signals by each circuit is described in detail below by circuit design in specific embodiments.

Example one

To implement the corresponding functions of the state machine circuit, it is shown in fig. 3. The state machine circuit includes: the decoder, M state machine data selectors and M state machine D triggers. Wherein the content of the first and second substances,

the decoder 301 decodes phase _ sel of the L-bit binary code into the control code at the SET end of the M D flip-flops. Wherein M =2 ^L M, L is a positive integer.

When the control code of the n-th D flip-flop SET end is 1, the D flip-flop is SET, so that the output of the Q end is 1.

And controlling M data selectors to select Q end signals of the (n + 1) th or (n-1) th D trigger to be output by dir, and outputting the output signals as D end signals of the nth D trigger.

ck is used as the signal input at the CP end of the D flip-flop, and when the clock signal goes through a rising edge (or a falling edge), the signal input at the D end is used as the signal output at the Q end.

The dir is provided by a decimal frequency division control circuit or a dynamic phase shift control circuit. ck is provided by a fractional division control circuit or a dynamic phase shift control circuit.

In one embodiment, when L =3 and M =8, the decoder 301 decodes 1 binary code with 3 bits into 8 control codes, which are sequentially inputted to the SET terminal of the D flip-flop 311 to the D flip-flop 318 for setting the D flip-flop. As shown in table 3-1.

TABLE 3-1,3 bit phase selection signals and their corresponding control codes

Signals of a D terminal and a Q terminal of each D flip-flop in an initial state are both 0, and when a binary code is 101, 8 control codes are 00000100 in sequence, a SET terminal signal of the D flip-flop 316 is 1, so that an output terminal Q of the D flip-flop 316 is SET to be 1. The output Q of the remaining 7D flip-flops is still 0. The first control signal sel _ ck 7:0, specifically 00000100, is obtained.

And when dir is 0, controlling the nth data selector to output a Q end signal of the (n-1) th D trigger, wherein the Q end signal is used as a D end signal of the nth D trigger. sel _ ck [7:0] is 00000100 and the second control signal sel _ next [7:0] is 00000010.

And when dir is 1, controlling the nth data selector to output a Q end signal of the (n + 1) th D trigger, wherein the Q end signal is used as a D end signal of the nth D trigger. sel _ ck [7:0] is 00000100 and sel _ next [7:0] is 00001000.

To realize the corresponding function of the dynamic phase shift control circuit, it is shown in fig. 4. The dynamic phase shift control circuit includes: a plurality of phase shifting D flip-flops. Wherein the content of the first and second substances,

the phase shift circuit control signal as the external control signal specifically includes: a phase shift clock control signal psck, a phase shift enable control signal psen, and a phase shift direction control signal psdir.

The D flip-flop 401 generates a transition signal a according to the inverted psck at the CP end and the psen input at the D end.

The D flip-flop 402 generates dir _ ps according to the transition signal a input from the CP terminal and the psdir input from the D terminal. Wherein, the first and the second end of the pipe are connected with each other,

when psdir is 0, dir _ ps is always 0.

When psdir is 1, at the rising edge of the transition signal a (i.e., the falling edge of psck), the D flip-flop 402 outputs the psdir at the D terminal as a Q terminal signal. If the initial signal at the Q terminal is 0, dir _ ps changes from 0 to 1 at the rising edge of the transition signal a.

D flip-flop 403 and D flip-flop 404 generate ck _ ps from psck, transition signal a, and ck _ next. By introducing ck _ next, the correlation relationship between ck _ ps and ck _ next is established, and the ck _ sel output by the first data selector is prevented from generating burrs.

To realize the corresponding function of the fractional division control circuit, as shown in fig. 5. The fractional frequency division control circuit includes: a fractional division enable signal circuit 510, a fractional division direction signal circuit 520, a fractional division clock signal circuit 530, and an integer division signal processing circuit 540. Wherein the content of the first and second substances,

fractional division enable signal circuit 510 processes frac through the gate circuit to obtain frac _ en.

When frac is a 1 3-bit binary code, it is processed through 1 or gate circuit, and the input of the or gate is each 1 bit of the binary signal, resulting in frac _ en. Frac _ en is 0,frac _ en to control the third and fourth data selectors to output the clock signal and the direction signal of the dynamic phase shift control circuit only when frac is 000, that is, the frac is low potential; when the frac is 001 to 111, that is, the frac is high potential, the frac _ en is 1, and the frac _ en controls the third data selector and the fourth data selector to output the clock signal and the direction signal of the fractional division control circuit.

The fractional-n directional signal circuit 520 processes frac through the gate circuit to obtain dir _ frac.

When the frac is a 1 bit 3 binary signal, the lower 2 bits of the frac are processed by nor gate 521 and the result and the most significant bit of the frac are processed by nor gate 522 resulting in the dir _ frac. The relationship between the 3-bit frac and its corresponding dir _ frac is shown in Table 5-1.

TABLE 5-1,3 bit divide circuit control signal and its corresponding fractional divide direction signal

As can be seen from Table 5-1, when frac is not 0 and the most significant bit is 0, dir _ frac is 1; when frac is 0, or the most significant bit is 1, dir _ frac is 0.

fractional-N clock signal circuit 530 includes a count subcircuit 531, a total subcircuit 532, a compare subcircuit 533, and a task subcircuit 534. Wherein the content of the first and second substances,

and the counting sub-circuit 531 is used for processing ck _ sel and int _ done and counting the number of phase shifts performed in 1 integer-divided clock period.

And a total number sub-circuit 532 for calculating the number of phase shifts to be performed in 1 integer divided clock cycle according to frac. Specifically, the value of frac (frac is a binary code) is the number of phase shifts that need to be performed in 1 integer clock cycle of the third clock signal.

For a 3-bit frac, when the frac is 001, the value is 1, and 1 phase shift needs to be performed in 1 clock cycle of integer frequency division of the third clock signal; when the frac is 010, the numerical value is 2, and 2 phase shifts are required to be performed in 1 integer frequency division clock period of the third clock signal; when the frac is 011, the value is 3, and 3 phase shifts are required in 1 integer frequency division clock period of the third clock signal; when the frac is 100, the value is 4, and 4 phase shifts are required to be performed in 1 clock cycle of integer frequency division of the third clock signal; when the frac is 101, the value is 5, and 3 phase shifts are required to be performed in 1 integer frequency division clock period of the third clock signal; when the frac is 110, the value is 6, and 2 phase shifts are required to be performed in 1 integer frequency division clock period of the third clock signal; when frac is 111 and the value is 7, then 1 phase shift is required for 1 integer divided clock cycle of the third clock signal.

The comparing sub-circuit 533 is configured to determine whether the number of phase shifts required to be performed is completed within 1 clock cycle of integer frequency division.

Task sub-circuit 534 is used to process the internal signal of fractional divided clock signal circuit 530 in conjunction with ck _ next and dir _ frac to generate ck _ frac.

In one embodiment, when frac is 001, ck _ sel output by the first data selector is indirectly controlled to carry out right shift phase for 1 time through dir _ frac and ck _ frac, and fractional division of 0.125 is completed; when frac is 010, ck _ sel is right-shifted for 2 times to complete fractional frequency division of 0.25; when frac is 011, ck _ sel is right-shifted for 3 times to complete fractional frequency division of 0.375; when frac is 100, ck _ sel is left-shifted for 4 times to complete fractional frequency division of 0.5; when frac is 101, ck _ sel is left-shifted for 3 times to complete fractional frequency division of 0.625; when frac is 110, ck _ sel is left-shifted for 2 times to complete fractional division of 0.75; when frac is 111, ck _ sel is left shifted 1 time, completing a fractional division of 0.875.

On the basis of completing the fractional frequency division, the ck _ sel is subjected to integer frequency division through an output frequency divider DIV, and a third clock signal is output to obtain

And

a divided clock signal. The resulting third clock signal is related to ck _ sel as shown in table 5-3.

TABLE 5-2 relationship of third clock signal to second clock signal

Wherein T is one clock cycle of the first clock signal, T _i I =1.2.3 … n.n +1 is the i-th clock cycle of the first clock signal. It should be noted that the clock period of the first clock signal is always unchanged.

As can be seen from Table 5-2, when the process was carried out

And

the integer digital value of 1 clock cycle of the third clock signal is equal to the number of clock cycles of ck _ sel in 1 clock cycle of the third clock signal; when proceeding with

And

the number of clock cycles of ck _ sel in 1 clock cycle constituting the third clock signal is equal to the integer bit value of 1 clock cycle of the third clock signal plus one. Further, when fractional division is not performed, the integer bit value of 1 clock cycle of the third clock signal is equal to the number of clock cycles of ck _ sel in 1 clock cycle constituting the third clock signal.

The integer digital value of 1 clock cycle of the third clock signal is determined by the second integer frequency-divided signal div _ sel _2.

Therefore, div _ sel _1 needs to be processed by the integer division signal processing circuit 540, resulting in div _ sel _2. The output divider DIV divides ck _ sel by an integer based on DIV _ sel _2, resulting in a third clock signal.

When frac is a 1-bit 3-bit binary signal, the addition circuit (i.e., integer division signal processing circuit 540) processes the signal div _ sel _1 based on the most significant bit of frac.

When the highest bit of frac is 0, proceed

And

the addition circuit outputs the value n of div _ sel _1 as div _ sel _2 when dividing the frequency; when the highest bit of frac is 1, proceed

And

the addition circuit adds one to the value n of div _ sel _1 to obtain and output div _ sel _2, which has a value of n +1.

The dynamic phase shift or fractional frequency division of the first clock signal can be realized by combining the three specific circuits and 4 data selectors.

In the scenario where the VCO outputs 8 first clock signals. Wherein each first clock signal differs from the phase-adjacent first clock signal by 1/8 phase, i.e., 45 °.

When dynamic phase shifting and fractional division are not performed, the timing diagram is shown in fig. 6.

ph [7:0] represents the first clock signal of phase 1, with its rising edge corresponding to the number 0; it should be understood that ph 7:0 is the first clock signal of 8 phases, but for simplicity of the drawing, the clock waveforms from phase 2 to phase 8 are not shown in detail and are represented by numbers 1 to 7. Specifically, the number 1 corresponds to the rising edge position of the first clock signal of the 2 nd phase, the number 2 corresponds to the rising edge position of the first clock signal of the 3 rd phase, and so on.

The state machine circuit decodes the phase selection signal phase [2:0], phase [2:0] is 2, and the decoded control code is 00000100 in sequence. The D flip-flop 313 is set according to the control code, and the obtained first selection control signal sel _ ck [7:0] is 00000100.

According to sel _ ck 7:0, the first data selector outputs the clock signal whose rising edge corresponds to the digit 2 in the first clock signal as ck _ sel.

And controlling a phase shift circuit control signal of the dynamic phase shift control circuit to be at a low potential so that dir _ ps and ck _ ps are 0.

The frac of the fractional division control circuit is controlled to low potential so that dir _ frac and ck _ frac are 0.

Since the most significant bit of frac is 0, the value of div _ sel _1, 3, is output as div _ sel _2, and the value of div _ sel _2 is 3. The output divider DIV divides ck _ sel by 4 based on DIV _ sel _2, resulting in the third clock signal CLKout.

When dynamic phase shifting of the left shift phase is performed, the timing diagram is shown in fig. 7.

frac is low, i.e. frac has a value of 0. Frac _ en is 0, frac _encontrols the third data selector and the fourth data selector to output the clock signal and the direction signal of the dynamic phase shift control circuit, and the state machine circuit receives the clock signal and the direction signal of the dynamic phase shift control circuit to perform dynamic phase shift.

The state machine circuit decodes a phase selection signal phase [2:0], phase [2:0] is 2, and the decoded control codes are 00000100 in sequence. The D flip-flop 313 is set according to the control code, and the obtained first selection control signal sel _ ck [7:0] is 00000100.

The dynamic phase shift control circuit receives an external phase shift circuit control signal and comprises: a phase shift clock control signal psck, a phase shift enable control signal psen, and a phase shift direction control signal psdir. Wherein the content of the first and second substances,

psdir is 0, making dir _ ps continuously 0;

when psen is 1, the D flip-flop 401, the D flip-flop 403, and the D flip-flop 404 process the psec and ck _ next at the CP end to obtain ck _ ps.

Since dir _ ps is 0, dir _pscontrols the nth data selector in the state machine, and outputs the Q end signal of the (n-1) th D trigger, and then the Q end signal is used as the D end signal of the nth D trigger. At this time, sel _ ck [7:0] is 00000100, and the second selection control signal sel _ next [7:0] is 00000010.

According to sel _ next [7:0], the second data selector outputs the clock signal whose rising edge corresponds to the digit 1 in the first clock signal as ck _ next.

When the signal ck _ ps is a rising edge, the state machine circuit takes the D-end signal of the nth D flip-flop as the signal output by the Q-end of the D flip-flop. In this process, sel _ ck [7:0] changes from 00000100 to 00000010; sel _ next [7:0] changes from 00000010 to 00000001.

Thereby, ck _ sel of the first data selection output is changed, and the ck _ sel completes a phase shift of 45 ° to the left.

Since the most significant bit of frac is 0, the value of div _ sel _1, 3, is output as div _ sel _2, with the value of div _ sel _2 being 3. The output divider DIV divides ck _ sel by 4 based on DIV _ sel _2, resulting in the third clock signal CLKout. Compared to CLKout without dynamic phase shifting and fractional frequency division, is shifted left by 45 deg. phase.

When performing dynamic phase shifting of the right phase shift, the timing diagram is shown in fig. 8.

frac is low, i.e. the value of frac is 0. Frac _ en is 0, frac _encontrols the third data selector and the fourth data selector to output the clock signal and the direction signal of the dynamic phase shift control circuit, and the state machine circuit receives the clock signal and the direction signal of the dynamic phase shift control circuit to perform dynamic phase shift.

The state machine circuit decodes a phase selection signal phase [2:0], phase [2:0] is 2, and the decoded control codes are 00000100 in sequence. The D flip-flop 316 is set according to the control code, and the first selection control signal sel _ ck [7:0] is 00000100.

psdir is 1, when psen is 1 and the psck is at the falling edge, the D trigger 402 outputs psdir at the D end through the Q end, so that dir _ ps is changed from 0 to 1;

Since dir _ ps is initially 0, dir _pscontrols the nth data selector in the state machine, and outputs the Q end signal of the (n-1) th D trigger, which is further used as the D end signal of the nth D trigger. At this time, sel _ ck [7:0] is 00000100, and the second selection control signal sel _ next [7:0] is 00000010. According to sel _ next [7:0], the second data selector outputs the clock signal of which the rising edge corresponds to the digit 1 in the first clock signal as ck _ next.

When dir _ ps is changed from 0 to 1, dir _ ps controls the nth data selector in the state machine to output the Q end signal of the (n + 1) th D trigger, and then the Q end signal is used as the D end signal of the nth D trigger. At this time, sel _ ck [7:0] is 00000100, and sel _ next [7:0] changes from 00000010 to 00001000. The output of the second data selector is changed from the clock signal whose rising edge corresponds to the number 1 in the first clock signal to the clock signal whose rising edge corresponds to the number 3 in the first clock signal as ck _ next.

When the signal ck _ ps is a rising edge, the state machine circuit takes the D-end signal of the nth D flip-flop as the signal output by the Q-end of the D flip-flop. In this process, sel _ ck [7:0] changes from 00000100 to 00001000; sel _ next [7:0] changes from 00001000 to 00010000.

Thereby, ck _ sel of the first data selection output is changed, and the ck _ sel completes a phase shifted to the right by 45 °.

Since the most significant bit of frac is 0, the value 3 of div _ sel _1 is output as div _ sel _2, and the value of div _ sel _2 is 3. The output divider DIV divides ck _ sel by 4 based on DIV _ sel _2, resulting in the third clock signal CLKout. The phase is shifted to the right by 45 deg. compared to CLKout without dynamic phase shifting and fractional division.

When a fractional division of 3.25 is performed, the timing diagram is shown in fig. 9.

By dividing by 3.25, i.e.

When dividing frequency, combine the above-mentioned related description of the fractional division control circuit. It can be obtained that frac should be 2, i.e. the binary code is 010; the value of div _ sel _1 should be 2.

When frac is 010, frac _ en is 1, frac _ en controls the third data selector and the fourth data selector to output the clock signal and the direction signal of the fractional division control circuit, so that the state machine circuit receives the clock signal and the direction signal of the fractional division control circuit and performs fractional division.

The state machine circuit decodes the phase selection signal phase [2:0], phase [2:0] is 0, and the decoded control code is 00000001 in sequence. The D flip-flop 311 is set according to the control code, and the obtained first selection control signal sel _ ck [7:0] is 00000001.

According to sel _ ck 7:0, the first data selector outputs the clock signal whose rising edge corresponds to digital 0 in the first clock signal as ck _ sel.

When frac is 010, the highest bit is 0, and dir \ u frac is 1. And controlling an nth data selector in the state machine by dir _ frac, outputting a Q end signal of an n +1 th D trigger, and further taking the Q end signal as a D end signal of the nth D trigger. At this time, sel _ ck [7:0] is 00000001, and the second selection control signal sel _ next [7:0] is 00000010.

fractional-N clock signal circuit 530 includes a count subcircuit 531, a total subcircuit 532, a compare subcircuit 533, and a task subcircuit 534. Under the control of int _ done outside, the counting sub-circuit 531 resets 1 time for every 3 clock cycles of ck _ sel; a total number of sub-circuits 532, which are calculated to obtain that 2 times of phase shift is required in each 3 clock cycles according to the fact that frac is 010; the comparison sub-circuit 533 determines whether the phase shift is completed for 2 times in each 3 clock cycles; the task sub-circuit 534 processes the internal signal of the fractional divided clock signal circuit 530 in conjunction with ck _ next and dir _ frac to generate ck _ frac.

And the state machine circuit takes the D end signal of the nth D trigger as the signal output by the Q end of the D trigger at the 1 st rising edge of ck _ frac. In this process, sel _ ck [7:0] changes from 00000001 to 00000010; sel _ next [7:0] also changes from 00000010 to 00000100.

In each 3 clock cycles of ck _ sel, ck _ frac experiences 2 rising edges, sel _ ck [7:0] changes from 00000001 to 00000010 and from 00000010 to 00000100.

Thereby, ck _ sel of the first data selection output is changed to the right by a phase of 45 ° 2 times. ck _ sel completes a fractional division of 0.25.

Since the most significant bit of frac is 0, the value 2 of div _ sel _1 is output as div _ sel _2, and the value of div _ sel _2 is 2. The output divider DIV divides ck _ sel by 3 based on DIV _ sel _2, resulting in the third clock signal CLKout. The third clock signal CLKOut includes 1 clock cycle in comparison with CLKOut without dynamic phase shift and fractional frequency division

Namely that

The division by 3.25 is completed. Wherein T is 1 clock cycle of the first clock signal.

When 3.5 decimal divisions are performed, the timing diagram is shown in fig. 10.

By dividing by 3.5, i.e.

When dividing frequency, combine the above-mentioned related description of the fractional division control circuit. It can be obtained that frac should be 4, i.e. the binary code is 100; the value of div _ sel _1 should be 2.

When frac is 100, frac _ en is 1, frac _encontrols the third data selector and the fourth data selector to output the clock signal and the direction signal of the fractional division control circuit, so that the state machine circuit receives the clock signal and the direction signal output by the fractional division control circuit to perform fractional division.

The state machine circuit decodes the phase selection signal phase [2:0], phase [2:0] is 0, and the decoded control code is 00000001 in sequence. The D flip-flop 311 is set according to the control code, and the first selection control signal sel _ ck [7:0] is obtained to be 00000001.

When frac is 100, the highest bit is 1,dir _fracis 0. And controlling an nth data selector in the state machine by dir _ frac, and outputting a Q end signal of an n-1 th D trigger to be used as a D end signal of the nth D trigger. At this time, sel _ ck [7:0] is 00000001, and the second selection control signal sel _ next [7:0] is 10000000.

According to sel _ next [7:0], the second data selector outputs the clock signal of digit 7 corresponding to the rising edge in the first clock signal as ck _ next.

fractional-N clock signal circuit 530 includes a count subcircuit 531, a total subcircuit 532, a compare subcircuit 533, and a task subcircuit 534. Under the control of int _ done outside, the counting sub-circuit 531 resets ck _ sel for 1 time every 4 clock cycles; a total number of sub-circuits 532, which calculates that 4 times of phase shift is required in every 4 clock cycles according to the fact that frac is 100; the comparison sub-circuit 533 determines whether the phase shift is completed for 4 times every 4 clock cycles; the task sub-circuit 534 processes the internal signal of the fractional divided clock signal circuit 530 in conjunction with ck _ next and dir _ frac to generate ck _ frac.

And the state machine circuit takes the D end signal of the nth D trigger as the signal output by the Q end of the D trigger at the 1 st rising edge of ck _ frac. In this process, sel _ ck [7:0] changes from 00000001 to 10000000; sel _ next [7:0] also changes from 10000000 to 01000000.

In each 4 clock cycles of ck _ sel, ck _ frac experiences 4 rising edges, sel _ ck [7:0] changes from 00000001 to 10000000, then from 10000000 to 01000000, then from 01000000 to 00100000, and then from 00100000 to 00010000.

Thereby, ck _ sel of the first data selection output is changed to be shifted by 45 ° phase 4 times to the left. ck _ sel completes a fractional division of 0.5.

Since the most significant bit of frac is 1, and the value 2 of div _ sel _1 is added by 1 and output as div _ sel _2, the value of div _ sel _2 is 3. The output divider DIV divides ck _ sel by 4 based on DIV _ sel _2, resulting in the third clock signal CLKout. The third clock signal CLKOUT includes CLKOUT 1 clock cycle, which is comparable to CLKOUT without dynamic phase shifting and fractional frequency division

Namely, it is

The division by 3.5 is completed. Wherein T is 1 clock cycle of the first clock signal.

The invention provides a dynamic phase shifting and fractional frequency dividing system based on a PLL circuit, which determines the precision of phase shifting and fractional frequency dividing according to the number of phases of a VCO output clock; the design complexity and the layout area of the circuit are effectively reduced.

The above embodiments are provided to further explain the objects, technical solutions and advantages of the present invention in detail, it should be understood that the above embodiments are merely exemplary embodiments of the present invention and are not intended to limit the scope of the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A dynamic phase shift and fractional frequency division system based on a PLL circuit comprises: the VCO is characterized by also comprising a phase shift and decimal frequency division circuit; wherein the content of the first and second substances,

the VCO is used for sending the M first clock signals to a receiving end of the phase-shifting and fractional frequency division circuit;

the phase shifting and fractional frequency dividing circuit is used for selecting the nth first clock signal from the M first clock signals as a second clock signal ck _ sel according to a phase selection signal phase _ sel; and also for receiving control signals, comprising: the phase shift circuit control signal and the frequency division circuit control signal frac carry out dynamic phase shift or decimal frequency division on the nth first clock signal; the integer divider is further configured to add the first integer divided signal div _ sel _1 according to the frac to obtain a second integer divided signal div _ sel _2; the phase shift and fractional frequency division circuit comprises a state machine circuit and a first data selector, wherein the state machine circuit is used for processing a phase selection signal phase _ sel according to a state machine direction signal dir and a state machine clock signal ck to obtain a first selection control signal sel _ ck, the sel _ ck is an M-bit control code, an nth bit in the M-bit control code is an enable bit, and the first data selector is used for controlling the first data selector to select the nth first clock signal from the M first clock signals as the ck _ sel;

the output frequency divider DIV is used for carrying out integer frequency division on the ck _ sel according to the DIV _ sel _2 to obtain a third clock signal;

wherein M, n is a positive integer, M is not less than n.

2. The system of claim 1, wherein the phase shifting and fractional division circuit is further configured to receive an external fractional division reset signal int _ done to perform fractional division.

3. The system of claim 1, wherein the phase shifting and fractional division circuit comprises: the circuit comprises a state machine circuit, a dynamic phase shift control circuit, a decimal frequency division control circuit, a first data selector, a second data selector, a third data selector and a fourth data selector.

4. The system of claim 3, wherein the state machine circuit is further configured to process the phase select signal phase _ sel according to the state machine direction signal dir and the state machine clock signal ck to obtain a second select control signal sel _ next; wherein the content of the first and second substances,

the sel _ next is a control code of M bits, and the n ± 1 th bit in the control code of M bits is an enable bit for controlling the second data selector to select the first clock signal adjacent to the nth first clock signal as the fourth clock signal ck _ next.

5. The system of claim 3, wherein the fractional division control circuit is configured to obtain a fractional division enable signal frac _ en according to the dividing circuit control signal frac, and determine whether the state machine circuit receives the clock signal and the direction signal output by the dynamic phase shift control circuit for dynamic phase shifting or receives the clock signal and the direction signal output by the fractional division control circuit for fractional division by the frac _ en.

6. The system of claim 3, wherein the fractional division control circuit is further configured to obtain a fractional division direction signal dir _ frac and a fractional division clock signal ck _ frac according to a division circuit control signal frac; when the direct-current switching circuit is communicated with the state machine circuit, the dir _ frac is used as a direction signal of the state machine circuit, and the ck _ frac is used as a clock signal of the state machine circuit.

7. The system of claim 3, wherein the dynamic phase shift control circuit is configured to obtain the phase shift direction signal dir _ ps and the phase shift clock signal ck _ ps according to the phase shift circuit control signal; when the state machine circuit is communicated, the dir _ ps is used as a direction signal of the state machine circuit, and the ck _ ps is used as a clock signal of the state machine circuit.