CN114629476A - High resolution pulse width modulation signal generating circuit - Google Patents
High resolution pulse width modulation signal generating circuit Download PDFInfo
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Abstract
The invention provides a high resolution pulse width modulation signal generating circuit, comprising: the control module generates rising and falling edge delay quantity; the PWM counting module generates a PWM signal; the delay module is used for carrying out delay operation on the PWM signal based on the rising edge delay amount and the falling edge delay amount; an output selection module outputting an output signal of the PWM counting module or the delay module based on the output selection signal; and the calibration module counts the frequency division signal of the ring oscillation signal of the delay module based on the counting clock and realizes the calibration of the delay amount according to the relation between the ring oscillation signal and the counting clock. The invention improves the resolution ratio of the PWM signal under the condition of not changing the counting clock; by the multiple relation between the counting clock and the delay chain, the delay module is used as the lower extension of the PWM counting module, so that the control is convenient, and the precision of the PWM signal is improved; and the MUX is used as the minimum delay unit and the delay selection logic of the delay chain, so that the inherent delay is reduced, and the error of the delay chain is favorably reduced.
Description
Technical Field
The invention relates to the field of integrated circuit design, in particular to a high-resolution pulse width modulation signal generating circuit.
Background
In switching power supplies, lighting, solar inverters, wireless chargers, and motor control, digitized PWM is used to control switching power elements to regulate a target voltage. With the development of SiC and GaN semiconductor technologies, the switching frequency of the switching power device is higher and higher, which puts demands on the control system to generate high-resolution PWM signals.
Generally, for a Pulse Width Modulation (PWM) signal with a given switching frequency fswpwm, the number of resolution bits n is determined by the clock frequency fck of the counter, which is calculated as n ═ log2(fck/fswpwm). Suppose that a PWM signal having a count clock frequency of 100MHz and a switching frequency of 1MHz has a resolution log2(100/1) ═ 6.6, meaning that the PWM signal has a resolution of 6.6 bits. In many applications, the resolution of the PWM signal needs to be more than 10 bits, and the clock frequency fck needs to be fswpwm 2101024 MHz. The clock frequency fck cannot be increased at will due to the limitation of the process, for example, under the condition of realizing 13-bit PWM precision under the carrier frequency of 1MHz, the counting clock of the digital PWM needs to reach the frequency above 8GHz, the resolution is 122ps, and this index is difficult to realize under the general integrated circuit process, so the limitation of the process capability on the clock frequency of the counter and the high resolution requirement of the PWM form a contradiction.
How to further improve the accuracy of the PWM signal and reduce the error has become one of the problems to be solved by those skilled in the art.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, it is an object of the present invention to provide a high resolution PWM signal generating circuit for solving the problem of the prior art that the accuracy of the PWM signal is limited by the clock frequency.
To achieve the above and other related objects, the present invention provides a high resolution pwm signal generating circuit, comprising:
the device comprises a control module, a PWM counting module, a delay module, an output selection module and a calibration module;
the control module receives a control signal and is used for generating a rising edge delay amount, a falling edge delay amount, an output selection signal and a calibration control signal;
the PWM counting module receives a counting clock and generates a PWM signal based on the counting clock;
the delay module is connected with the output ends of the control module and the PWM counting module and is used for delaying the PWM signal based on the rising edge delay amount and the falling edge delay amount;
the output selection module is connected with the output ends of the control module, the PWM counting module and the delay module and outputs the output signal of the PWM counting module or the delay module based on the output selection signal;
the calibration module is connected with the output end of the control module, receives the counting clock, counts the frequency division signal of the ring oscillation signal of the delay module based on the counting clock, and calibrates the delay amount based on the multiple relation of the ring oscillation signal and the counting clock, wherein the high level width of the ring oscillation signal is the rising edge delay amount in the delay module, and the low level width is the preset width.
Optionally, the control module includes a delay amount selection register, and the rising edge delay amount and the falling edge delay amount are output based on the delay amount selection register.
Optionally, the PWM counting module includes a counting unit and a comparing unit; the counting unit receives the counting clock, counts the counting clock and outputs a counting value; the comparison unit is connected with the output end of the counting unit, compares the counting value with a preset value, and turns over the level to obtain the PWM signal when the counting value reaches the preset value.
More optionally, the PWM count module further receives a phase adjustment control signal, where the phase adjustment control signal is connected to the comparison unit, and adjusts the phase of the PWM signal by changing the preset value, so as to implement a pulse frequency modulation function.
Optionally, the delay module includes a rising edge delay unit and a falling edge delay unit;
the rising edge delay unit is connected with the output ends of the PWM counting module and the control module and delays the rising edge of the PWM signal based on the rising edge delay amount; the falling edge delay unit is connected with the rising edge delay unit and the output end of the control module, and carries out falling edge delay on the PWM signal after the rising edge delay based on the falling edge delay amount;
or the falling edge delay unit is connected with the output ends of the PWM counting module and the control module, and carries out falling edge delay on the PWM signal based on the falling edge delay amount; the rising edge delay unit is connected with the falling edge delay unit and the output end of the control module, and carries out rising edge delay on the PWM signal after the falling edge delay based on the rising edge delay amount.
More optionally, the rising edge delay unit and the falling edge delay unit each include a delay decoder, a delay chain formed by m sequentially cascaded delay blocks, and an and or logic unit;
the delay decoder decodes the delay amount to obtain a delay amount selection signal and a delay block effective signal;
the delay chain receives the PWM signal, each delay block in the delay chain receives the delay amount selection signal and the delay block effective signal, and the PWM signal is delayed based on the delay amount selection signal and the delay block effective signal;
the input end of the AND logic unit is connected with the output end of the delay chain and the PWM signal, and the output signal of the delay chain and the PWM signal are subjected to AND operation to obtain a delay signal of the PWM signal;
wherein m is a natural number of 1 or more.
Optionally, the delay block includes first to n +1 th data selectors connected in series, a first input end of the later-stage data selector is connected to an output end of the earlier-stage data selector, a second input end of each data selector is connected to the PWM signal, a first input end and a second input end of the first data selector are connected to the PWM signal, a control end of the first data selector to the nth data selector is connected to the corresponding delay amount selection signal, a control end of the n +1 th data selector is connected to the corresponding delay block effective signal, where n is a natural number greater than or equal to 1.
More optionally, the data selector is an alternative selector.
More optionally, the calibration module includes a ring oscillation signal generating unit and a calibration operation unit, the ring oscillation signal generating unit generates at least two ring oscillation signals with different frequencies, the high level width of each ring oscillation signal selects different delay amounts of the delay module, and the low level width of each ring oscillation signal is a preset width; and the calibration operation unit divides the frequency of the ring oscillation signal and counts the frequency division signal of the ring oscillation signal based on the counting clock to obtain the multiple relation between the ring oscillation signal and the counting clock.
Optionally, the ring oscillation signal generating unit includes a delay selecting subunit, a preset delay subunit, an edge detecting subunit, and an RS flip-flop;
the delay selection subunit is connected with the output end of the RS trigger, the delay selection subunit and the rising edge delay unit have the same structure, and different delay amounts are selected based on the calibration control signal to delay the output signal of the RS trigger;
the preset delay subunit is connected with the output end of the RS trigger and delays the output signal of the RS trigger based on a preset delay amount;
the edge detection subunit is connected with the output end of the preset delay unit and used for carrying out edge detection on the output signal of the preset delay subunit;
and the reset end of the RS trigger is connected with the output end of the delay selection subunit, and the set end of the RS trigger is connected with the output end of the edge detection subunit to generate the ring oscillation signal.
As described above, the high resolution pwm signal generating circuit according to the present invention has the following advantageous effects:
1. the high-resolution pulse width modulation signal generating circuit improves the resolution of the pulse width modulation signal under the condition of not changing a counting clock, and can be used for adjusting the period and the duty ratio of a PWM signal.
2. The high-resolution pulse width modulation signal generating circuit measures the multiple relation between the counting clock and the delay chain through the calibration circuit, can conveniently use the delay module as the lower extension of the PWM counting module, is convenient for software control, and improves the precision of high-resolution PWM.
3. The high-resolution pulse width modulation signal generating circuit uses the basic unit device MUX as the minimum delay unit of the delay chain and also serves as delay selection logic, so that the inherent delay from the input of the delay module to the output of the delay module is reduced, and the error of the delay chain is favorably reduced.
Drawings
Fig. 1 is a schematic diagram of a high resolution pwm signal generating circuit according to the present invention.
Fig. 2 is a schematic structural diagram of the PWM counting module according to the present invention.
FIG. 3 is a schematic diagram of a rising edge delay unit according to the present invention.
Fig. 4 is a schematic diagram of the delay block of the present invention.
Fig. 5 is a schematic structural diagram of a calibration module according to the present invention.
Description of the element reference numerals
1 high resolution pulse width modulation signal generating circuit
11 control module
12 PWM counting module
121 counting unit
122 comparison unit
13 delay module
13a rising edge delay unit
13b falling edge delay unit
131 delay decoder
132 delay block
1321 data selector
1322 buffer stage
133 AND OR logic cell
134 buffer
14 output selection module
15 calibration module
151 ring oscillation signal generating unit
1511 delay selection subunit
1512 preset delay subunit
1513 edge detector subunit
1514 RS flip-flop
152 calibration arithmetic unit
Detailed Description
The following embodiments of the present invention are provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1-5. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
As shown in fig. 1, the present invention provides a high resolution pwm signal generating circuit 1, where the high resolution pwm signal generating circuit 1 includes:
the device comprises a control module 11, a PWM counting module 12, a delay module 13, an output selection module 14 and a calibration module 15.
As shown in FIG. 1, the control module 11 receives control signals for generating a rising edge delay up [7:0], a falling edge delay down [7:0], an output select signal ctl1, and a calibration control signal ctl 2.
Specifically, the control module 11 includes, but is not limited to, a delay amount selection register, an output control unit, and a calibration control unit (not shown), and any control signal for controlling operations of the modules in the high resolution pwm signal generating circuit 1 may be generated by the control module 11. The selection of the rising edge delay amount up [7:0] and the falling edge delay amount down [7:0] is realized by changing the delay amount selection register, and based on the characteristics of the register, when the edge of the PWM signal changes, the output value of the delay amount selection register cannot be changed immediately, so that the generation of competition of the output of the PWM signal with high resolution can be avoided.
Specifically, in this embodiment, the control module 11 further receives the counting clock ck as a working clock, and in actual use, the source of the working clock of the control module 11 may be set as needed, which is not limited in this embodiment.
It should be noted that, as an example, the rising edge delay amount up [7:0] and the falling edge delay amount down [7:0] are 8-bit bus signals. In practical use, the number of bits of the rising edge delay amount and the falling edge delay amount can be set according to needs, and is not limited to this embodiment.
As shown in fig. 1, the PWM count module 12 receives the count clock ck and generates a PWM signal based on the count clock ck.
Specifically, as shown in fig. 2, in the present embodiment, the PWM counting module 12 includes a counting unit 121 and a comparing unit 122. The counting unit 121 receives the count clock ck, counts the count clock ck, and outputs a count value. The comparing unit 122 is connected to the output end of the counting unit 121, compares the count value with a preset value (comparison threshold), and turns over the level to obtain the PWM signal when the count value reaches the preset value.
It should be noted that any circuit structure capable of generating a PWM waveform is applicable to the present invention, and is not limited to this embodiment.
As another implementation of the present invention, the PWM count module 11 further receives a phase adjustment control signal ctl3, for example, the phase adjustment control signal ctl3 is provided by the control module 11; the phase adjustment control signal ctl3 is connected to the comparison unit 122, and the preset value is changed to adjust the phase of the PWM signal, so as to implement a Pulse Frequency Modulation (PFM) function.
As shown in fig. 1, the delay module 13 is connected to the output ends of the control module 11 and the PWM count module 12, and delays the PWM signal based on the rising edge delay amount up [7:0] and the falling edge delay amount down [7:0 ].
Specifically, as shown in fig. 1, the delay module 13 includes a rising edge delay unit 13a and a falling edge delay unit 13 b. In this embodiment, the rising edge delay unit 13a is connected to the output ends of the PWM count module 12 and the control module 11, and delays the rising edge of the PWM signal based on the rising edge delay amount up [7:0 ]; the falling edge delay unit 13b is connected to the rising edge delay unit 13a and the output end of the control module 11, and performs falling edge delay on the PWM signal after the rising edge delay based on the falling edge delay amount down [7:0 ]. In this embodiment, the rising edge delay unit 13a and the falling edge delay unit 13b have the same structure, and each includes a delay decoder 131, a delay chain formed by m sequentially cascaded delay blocks 132, and an and or logic unit 133. In this embodiment, taking the rising edge delay unit 13a as an example, the falling edge delay unit 13b and the rising edge delay unit 13a only differ in receiving different delay amounts (the rising edge delay unit receives the rising edge delay amount, and the falling edge delay unit receives the falling edge delay amount), and the delayed objects are different (the rising edge delay unit delays the rising edge, and the falling edge delay unit delays the falling edge), which are not repeated herein.
More specifically, as shown in FIG. 3, the delay decoder 131 decodes the rising edge delay amount up [7:0] into a rising edge delay amount selection signal sel [255:0] and a delay block valid signal nohit [7:0 ]. In this embodiment, the delay decoder 131 is an 8-input 256-output decoder, decodes an 8-bit rising edge delay amount into a 256-bit rising edge delay amount selection signal, and outputs an 8-bit delay block valid signal, while only one-bit rising edge delay amount selection signal is valid at the same time.
More specifically, as shown in fig. 3, the delay chain includes m sequentially cascaded delay blocks 132, where m is a natural number greater than or equal to 1, and m is set to 8 in this embodiment; the delay chain receives the PWM signal, delays a rising edge of the PWM signal based on the rising edge delay amount selection signal sel [255:0] and the delay block valid signal nohit [7:0 ]. The input end of the first-stage delay block is connected with the PWM signal, the input end of the second-stage delay block is connected with the output end of the first-stage delay block, the input end of the third-stage delay block is connected with the output end … … of the second-stage delay block, and so on, and the input end of the eighth-stage delay block is connected with the output end of the seventh-stage delay block; the first stage delay block receives the last eight bits of the rising edge delay amount selection signal (sel [255:224]) and the last bit of the delay block valid signal (nohit [7]), and the second to eighth stage delay blocks receive the eight bits of the rising edge delay amount selection signal and the one bit of the delay block valid signal, respectively, to obtain the corresponding rising edge delay. Further, taking an eighth-stage delay block as an example, as shown in fig. 4, the delay block 132 includes first to n +1 th data selectors 1321 sequentially cascaded, where n is a natural number greater than or equal to 1; a first input end of a later-stage data selector is connected with an output end of a preceding-stage data selector, a second input end of each data selector is connected with the PWM signal, a first input end and a second input end of the first data selector are connected with the PWM signal, control ends of the first data selector to the nth data selector are respectively connected with a corresponding one-bit signal in the delay amount selection signal, and a control end of the n +1 th data selector is connected with a corresponding one-bit signal in the delay block effective signal; as an example, n is set to 32, and the data selector employs a one-out-of-two selector (MUX). When the delay block effective signal (nohit [0]) in the delay block 132 is at low level, the corresponding delay block is selected to add delay, when the delay block effective signal (nohit [0]) in the delay block 132 is at high level, the PWM signal which is not selected by the corresponding delay block is directly output by the last-stage alternative selector; the corresponding one of the two selectors is selected to add a delay when the delay amount selection signal (sel [0], sel [1] … sel [30] or sel [31]) is low, and the corresponding one of the two selectors is not selected to directly output the PWM signal when the delay amount selection signal (sel [0], sel [1] … sel [30] or sel [31]) is high. As another implementation manner of the present invention, the delay block 132 further includes a buffer stage 1322 connected to the input terminal of the first data selector, and the PWM signal passes through the buffer stage 1322 and then is input to each data selector, wherein the buffer stage 1322 and the (last) th +1 th data selector (the last stage) are inherent delays, i.e., there are delays as long as the PWM signal passes through the delay chain, regardless of the delay amount.
More specifically, as shown in fig. 3, the input terminal of the and/or logic unit 133 is connected to the output terminal of the delay chain and the PWM signal, and performs an and operation on the output signal of the delay chain and the PWM signal to obtain a delay signal of the PWM signal. In this embodiment, the and/or logic unit 133 includes an and gate and a not gate connected to an output end of the and gate, and in practical use, any circuit structure capable of implementing and/or logic is applicable to the present invention, which is not limited to this embodiment.
As another implementation manner of the present invention, the rising edge delay unit 13a further includes a buffer 134 connected to the input terminal of the first stage delay block, and the PWM signal is output to the delay block 132 and the and or logic unit 133 through the buffer 134. The buffer 134 and the and or logic unit 133 are inherent delays.
It should be noted that, in order to reduce the error between each section of delay, the lengths of the metal lines at the input ends of the data selectors are equal (or approximately equal, allowing process errors) and the lengths of the metal lines at the output ends of the data selectors are equal (or approximately equal, allowing process errors). Compared with the prior art, the alternative selector of the basic unit for delaying has small circuit scale and short inherent delay brought by the selection circuit, and is favorable for fine control of the PWM signal.
It should be noted that, in practical use, the PWM signal may be delayed by a falling edge first, and then delayed by a rising edge. The falling edge delay unit is connected with the output ends of the PWM counting module and the control module, and carries out falling edge delay on the PWM signal based on the falling edge delay amount; the rising edge delay unit is connected with the falling edge delay unit and the output end of the control module, and carries out rising edge delay on the PWM signal after the falling edge delay based on the rising edge delay amount; the present embodiment is not limited thereto.
As shown in fig. 1, the output selection module 14 is connected to the output ends of the control module 11, the PWM count module 12 and the delay module 13, and outputs the output signal of the PWM count module 11 or the delay module 12 based on the output selection signal ctl1 to obtain the output signal PWM' of the high resolution PWM signal generating circuit 1.
Specifically, when the rising edge and/or the falling edge of the PWM signal needs to be delayed, the output selection module 14 outputs the output signal of the delay module 12; when there is no need to delay the rising edge and/or the falling edge of the PWM signal, the output selection module 14 outputs the output signal of the PWM count module 11.
As shown in fig. 1, the calibration module 15 is connected to the output end of the control module 11, receives the count clock ck, counts the frequency-divided signal of the ring oscillator signal calclk of the delay module 13 based on the count clock ck, and calibrates the delay amount based on a multiple relationship between the ring oscillator signal calclk and the count clock ck, where a high level width of the ring oscillator signal calclk is a rising edge delay amount in the delay module, and a low level width is a preset width.
Specifically, in the present embodiment, the calibration module 15 includes a ring signal generating unit 151 and a calibration calculating unit 152; the ring oscillation signal generating unit 151 generates at least two ring oscillation signals with different frequencies, the high level width of each ring oscillation signal selects different delay amounts of the delay module 13, and the low level width of each ring oscillation signal is a preset value; the calibration operation unit 152 divides the frequency of the ring oscillator signal calclk, counts the frequency-divided signal of the ring oscillator signal calclk based on the count clock ck, calculates the multiple relation Fcal between the ring oscillator signal calclk and the count clock ck through hardware, namely, a calibration amount, outputs a calibration completion flag comp, and adjusts the rising edge delay amount or the falling edge delay amount based on the calibration amount Fcal to realize high-resolution output.
More specifically, the ring signal generating unit 151 includes a delay selecting subunit 1511, a preset delay subunit 1512, an edge detecting subunit 1513, and an RS flip-flop 1514. The delay selection subunit 1511 is connected to the output end of the RS flip-flop 1514, the delay selection subunit 1511 has the same structure as the rising edge delay unit 13a, and selects different delay amounts based on the calibration control signal ctl2 to delay the output signal of the RS flip-flop 1514. As an example, in this embodiment, the delay amount of the delay selection subunit 1511 is set to 256 stages and 128 stages respectively, that is, all MUXs or half MUXs in the rising edge delay unit 13a are selected to be added into the delay chain, and in actual use, the delay amount of the delay selection subunit 1511 may be set as required, which is not limited to 256 stages and 128 stages of this embodiment. The preset delay subunit 1512 is connected to an output end of the RS flip-flop 1514, and delays an output signal of the RS flip-flop 1514 based on a preset delay amount. The preset delay amount is set based on the process conditions, and is not described in detail herein. The edge detection subunit 1513 is connected to the output end of the preset delay subunit 1512, and performs edge detection on the output signal of the preset delay subunit 1512. The reset terminal RST of the RS flip-flop 1514 is connected to the output terminal of the delay selection subunit 1511, and the SET terminal SET is connected to the output terminal of the edge detection subunit 1513, so as to generate the ring oscillation signal calclk.
More specifically, the calibration module 15 calibrates the ring oscillator signal calclk by using the count clock ck, measures a multiple relationship between the count clock ck and the ring oscillator signal calclk (Fcal X, where X is a delay amount of 1 stage, and Fcal is a calibration amount) with the count clock ck as a reference, and compensates the output signal of the high-resolution PWM signal generating circuit 1 based on the relationship between the count clock ck and the ring oscillator signal calclk to generate the high-resolution PWM signal. The calibration and operation of the invention are realized by hardware, and the conversion by using a CPU is not needed, thereby reducing the load of the CPU. In the calibration module 15, the high level width of the ring oscillator signal calclk is determined by the delay amount selected by the delay selection subunit 1511, and the low level width is determined by the delay amount of the preset delay subunit 1512. As an example, first selecting 256-stage delay, the 512 frequency division (the frequency division value can be set according to needs, but is not limited to this embodiment) of the ring oscillator signal calclk measured by the calibration operation unit 152 can be divided into 256 CNT count clocks ck; and then, selecting 128 sections of delays, 512 frequency division of the ring oscillation signal calclk detected by the calibration operation unit 152 can be divided into 128 CNTs of the count clock ck.
Assuming that the delay per segment is X and the inherent delay is DLY, the following equation is obtained:
(256X+DLY)*512＝Tck*CNT256 (1)
(128X+DLY)*512＝Tck*CNT128 (2)
wherein Tck is the period of the counting clock ck, and from these two equations, it can be calculated how many X each ck is equal to, and the calibration quantity Fcal satisfies:
Fcal＝Tck/x＝512*128/(CNT256-CNT128)。
in summary, the present invention provides a high resolution PWM signal generating circuit, which includes a control module, a PWM counting module, a delay module, an output selecting module, and a calibration module; the control module receives a control signal and is used for generating a rising edge delay amount, a falling edge delay amount, an output selection signal and a calibration control signal; the PWM counting module receives a counting clock and generates a PWM signal based on the counting clock; the delay module is connected with the output ends of the control module and the PWM counting module and is used for delaying the PWM signal based on the rising edge delay amount and the falling edge delay amount; the output selection module is connected with the output ends of the control module, the PWM counting module and the delay module and outputs the output signal of the PWM counting module or the delay module based on the output selection signal; the calibration module is connected with the output end of the control module, receives the counting clock, counts the frequency division signal of the ring oscillation signal of the delay module based on the counting clock, and calibrates the delay amount based on the multiple relation of the ring oscillation signal and the counting clock, wherein the high level width of the ring oscillation signal is the rising edge delay amount in the delay module, and the low level width is the preset width. The high-resolution pulse width modulation signal generating circuit improves the resolution of the pulse width modulation signal under the condition of not changing a counting clock, and can be used for adjusting the period and the duty ratio of a PWM signal. The high-resolution pulse width modulation signal generating circuit measures the multiple relation between the counting clock and the delay chain through the calibration circuit, can conveniently use the delay module as the lower extension of the PWM counting module, is convenient for software control, and improves the precision of high-resolution PWM. The high-resolution pulse width modulation signal generating circuit uses the basic unit device MUX as the minimum delay unit of the delay chain and also serves as delay selection logic, so that the inherent delay from the input of the delay module to the output of the delay module is reduced, and the error of the delay chain is favorably reduced. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A high resolution pwm signal generating circuit, comprising at least:
the device comprises a control module, a PWM counting module, a delay module, an output selection module and a calibration module;
the control module receives a control signal and is used for generating a rising edge delay amount, a falling edge delay amount, an output selection signal and a calibration control signal;
the PWM counting module receives a counting clock and generates a PWM signal based on the counting clock;
the delay module is connected with the output ends of the control module and the PWM counting module and is used for delaying the PWM signal based on the rising edge delay amount and the falling edge delay amount;
the output selection module is connected with the output ends of the control module, the PWM counting module and the delay module and outputs the output signal of the PWM counting module or the delay module based on the output selection signal;
the calibration module is connected with the output end of the control module, receives the counting clock, counts the frequency division signal of the ring oscillation signal of the delay module based on the counting clock, and calibrates the delay amount based on the multiple relation of the ring oscillation signal and the counting clock, wherein the high level width of the ring oscillation signal is the rising edge delay amount in the delay module, and the low level width is the preset width.
2. The high resolution pwm signal generation circuit according to claim 1, wherein: the control module includes a delay amount selection register that outputs the rising edge delay amount and the falling edge delay amount based on the delay amount selection register.
3. The high resolution pwm signal generating circuit according to claim 1, wherein: the PWM counting module comprises a counting unit and a comparing unit; the counting unit receives the counting clock, counts the counting clock and outputs a counting value; the comparison unit is connected with the output end of the counting unit, compares the counting value with a preset value, and turns over the level to obtain the PWM signal when the counting value reaches the preset value.
4. The high resolution pulse width modulated signal generating circuit of claim 3, wherein: the PWM counting module also receives a phase adjustment control signal, the phase adjustment control signal is connected with the comparison unit, the phase of the PWM signal is adjusted by changing the preset value, and the pulse frequency modulation function is further realized.
5. The high resolution pwm signal generating circuit according to claim 1, wherein: the delay module comprises a rising edge delay unit and a falling edge delay unit;
the rising edge delay unit is connected with the output ends of the PWM counting module and the control module and delays the rising edge of the PWM signal based on the rising edge delay amount; the falling edge delay unit is connected with the rising edge delay unit and the output end of the control module, and carries out falling edge delay on the PWM signal after the rising edge delay based on the falling edge delay amount;
or the falling edge delay unit is connected with the output ends of the PWM counting module and the control module, and carries out falling edge delay on the PWM signal based on the falling edge delay amount; the rising edge delay unit is connected with the falling edge delay unit and the output end of the control module, and carries out rising edge delay on the PWM signal after the falling edge delay based on the rising edge delay amount.
6. The high resolution pulse width modulated signal generating circuit of claim 5, wherein: the rising edge delay unit and the falling edge delay unit respectively comprise a delay decoder, a delay chain formed by m sequentially cascaded delay blocks and an AND logic unit;
the delay decoder decodes the delay amount to obtain a delay amount selection signal and a delay block effective signal;
the delay chain receives the PWM signal, each delay block in the delay chain receives the delay amount selection signal and the delay block effective signal, and the PWM signal is delayed based on the delay amount selection signal and the delay block effective signal;
the input end of the AND logic unit is connected with the output end of the delay chain and the PWM signal, and the output signal of the delay chain and the PWM signal are subjected to AND operation to obtain a delay signal of the PWM signal;
wherein m is a natural number of 1 or more.
7. The high resolution pulse width modulated signal generating circuit of claim 6, wherein: the delay block comprises first to n +1 th data selectors which are sequentially cascaded, a first input end of a back-stage data selector is connected with an output end of a front-stage data selector, a second input end of each data selector is connected with the PWM signal, a first input end and a second input end of the first data selector are connected with the PWM signal, the first data selector is connected with a control end of the n-th data selector and is respectively connected with a corresponding delay amount selection signal, a control end of the n +1 th data selector is connected with a corresponding delay block effective signal, and n is a natural number greater than or equal to 1.
8. The high resolution pwm signal generating circuit according to claim 7, wherein: the data selector is an alternative selector.
9. The high resolution PWM signal generating circuit according to any one of claims 5 to 8, wherein: the calibration module comprises a ring oscillation signal generation unit and a calibration operation unit, wherein the ring oscillation signal generation unit generates at least two ring oscillation signals with different frequencies, the high level width of each ring oscillation signal selects different delay amounts of the delay module respectively, and the low level width of each ring oscillation signal is a preset width; and the calibration operation unit divides the frequency of the ring oscillation signal and counts the frequency division signal of the ring oscillation signal based on the counting clock to obtain the multiple relation between the ring oscillation signal and the counting clock.
10. The high resolution pwm signal generating circuit according to claim 9, wherein: the ring oscillation signal generating unit comprises a delay selection subunit, a preset delay subunit, an edge detection subunit and an RS trigger;
the delay selection subunit is connected with the output end of the RS trigger, the delay selection subunit and the rising edge delay unit have the same structure, and different delay amounts are selected based on the calibration control signal to delay the output signal of the RS trigger;
the preset delay subunit is connected with the output end of the RS trigger and delays the output signal of the RS trigger based on a preset delay amount;
the edge detection subunit is connected with the output end of the preset delay unit and used for carrying out edge detection on the output signal of the preset delay subunit;
and the reset end of the RS trigger is connected with the output end of the delay selection subunit, and the set end of the RS trigger is connected with the output end of the edge detection subunit to generate the ring oscillation signal.
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| CN202011443393.5A CN114629476A (en) | 2020-12-08 | 2020-12-08 | High resolution pulse width modulation signal generating circuit |
| PCT/CN2021/116216 WO2022121389A1 (en) | 2020-12-08 | 2021-09-02 | High-resolution pulse width modulation signal generation circuit |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115913189A (en) * | 2022-10-27 | 2023-04-04 | 湖南毂梁微电子有限公司 | Digital pulse width modulation circuit and modulation method |
| CN116015253A (en) * | 2022-12-13 | 2023-04-25 | 上海极海盈芯科技有限公司 | Self-correcting delay circuit, micro-processing chip and motor control system |
| CN116707496A (en) * | 2023-08-01 | 2023-09-05 | 青岛本原微电子有限公司 | High-resolution pulse signal processing circuit |
| CN117040263A (en) * | 2023-08-03 | 2023-11-10 | 北京伽略电子股份有限公司 | Soft start circuit |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115580275B (en) * | 2022-12-08 | 2023-08-01 | 国仪量子(合肥)技术有限公司 | High-precision pulse signal generating device, FPGA chip and signal processing equipment |
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| US7459951B2 (en) * | 2006-02-22 | 2008-12-02 | Exar Corporation | Self-calibrating digital pulse-width modulator (DPWM) |
| CN102035514B (en) * | 2010-11-11 | 2012-11-28 | 东南大学 | Control method for digital pulse width modulation (DPWM) circuit |
| CN102386916A (en) * | 2011-09-21 | 2012-03-21 | 复旦大学 | Digital pulse width modulator circuit capable of reducing power consumption and chip area |
| US8994426B2 (en) * | 2012-08-31 | 2015-03-31 | Analog Devices, Inc. | Method and systems for high-precision pulse-width modulation |
| CN106612111B (en) * | 2016-12-30 | 2020-05-08 | 深圳市志奋领科技有限公司 | High-precision delay clock calibration system and method |
| CN111884631A (en) * | 2020-04-30 | 2020-11-03 | 电子科技大学 | Digital pulse width modulation module adopting hybrid structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115913189A (en) * | 2022-10-27 | 2023-04-04 | 湖南毂梁微电子有限公司 | Digital pulse width modulation circuit and modulation method |
| CN115913189B (en) * | 2022-10-27 | 2023-10-27 | 湖南毂梁微电子有限公司 | Digital pulse width modulation circuit and modulation method |
| CN116015253A (en) * | 2022-12-13 | 2023-04-25 | 上海极海盈芯科技有限公司 | Self-correcting delay circuit, micro-processing chip and motor control system |
| CN116015253B (en) * | 2022-12-13 | 2024-04-09 | 上海极海盈芯科技有限公司 | Self-correcting delay circuit, micro-processing chip and motor control system |
| CN116707496A (en) * | 2023-08-01 | 2023-09-05 | 青岛本原微电子有限公司 | High-resolution pulse signal processing circuit |
| CN116707496B (en) * | 2023-08-01 | 2023-10-13 | 青岛本原微电子有限公司 | High-resolution pulse signal processing circuit |
| CN117040263A (en) * | 2023-08-03 | 2023-11-10 | 北京伽略电子股份有限公司 | Soft start circuit |
| CN117040263B (en) * | 2023-08-03 | 2024-04-12 | 北京伽略电子股份有限公司 | Soft start circuit |
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