CN115913189B

CN115913189B - Digital pulse width modulation circuit and modulation method

Info

Publication number: CN115913189B
Application number: CN202211325881.5A
Authority: CN
Inventors: 陈虎; 邓梁; 彭石
Original assignee: Hunan Guliang Microelectronics Co ltd
Current assignee: Hunan Guliang Microelectronics Co ltd
Priority date: 2022-10-27
Filing date: 2022-10-27
Publication date: 2023-10-27
Anticipated expiration: 2042-10-27
Also published as: CN115913189A

Abstract

The application relates to a digital pulse width modulation circuit and a modulation method. The basic circuit is used for generating a pre-stage pulse width modulation output signal, the transient response circuit is used for carrying out transient modulation on the pre-stage pulse width modulation output signal, the delay response circuit is used for carrying out delay modulation on the pre-stage pulse width modulation output signal, the normal state response circuit is used for carrying out normal state modulation on the pre-stage pulse width modulation output signal, and the signal output end of the post-selection switch circuit is used for selecting and outputting the modulated pulse signal. According to the scheme, multidimensional efficient response can be made to the external event, digital pulse signals with different time characteristics can be flexibly modulated, and the event response efficiency is greatly improved.

Description

Digital pulse width modulation circuit and modulation method

Technical Field

The application belongs to the technical field of pulse width modulation, and relates to a digital pulse width modulation circuit and a modulation method.

Background

Digital pulse width modulation (Digital Pulse Width Modulation, DPWM) is widely used in many control fields of measurement, communication, power control and conversion, such as instrumentation, robot servos, motor drives, frequency converters, switching power supplies, photovoltaic inversion, and the like. In general, a PWM pulse in a control system has a certain period and duty ratio, which are used for controlling the on-off of each switching device in a circuit, and the period and duty ratio of the PWM pulse do not change at will after setting. However, the control system (e.g., pipeline, etc.) also needs to respond to external events to effect start-up, braking, acceleration, and deceleration, etc. In the process of implementing the present application, the inventor finds that the conventional digital pulse width modulation technology has the technical problem of low event response efficiency.

Disclosure of Invention

In view of the above-mentioned problems of the conventional methods, the present invention proposes a digital pulse width modulation circuit and a digital pulse width modulation method, which can make a multidimensional efficient response to an external event and flexibly modulate digital pulse signals with different time characteristics.

In order to achieve the above object, the embodiment of the present invention adopts the following technical scheme:

in one aspect, a digital pulse width modulation circuit is provided, including a base circuit, a transient response circuit, a delay response circuit, a normal response circuit, and a post-selection switch circuit;

the signal output end of the basic circuit is respectively connected with the signal input ends of the transient response circuit and the delay response circuit, the quantization control output end of the basic circuit is respectively connected with the secondary quantization control input end of the delay response circuit and the selection control input end of the post-selection switch circuit, the signal input end of the normal response circuit is used for receiving an external event input signal, and the signal output end of the normal response circuit is respectively connected with the control input ends of the basic circuit and the delay response circuit;

the signal input end of the transient response circuit is used for receiving an external event input signal, the quantization control input end of the transient response circuit is connected with the quantization control output end of the basic circuit, the signal input ends of the post-selection switch circuit are respectively connected with the signal output ends of the delay response circuit and the transient response circuit, and the signal output end of the post-selection switch circuit is used for selecting and outputting a modulated pulse signal;

The basic circuit is used for generating a pre-stage pulse width modulation output signal, the transient response circuit is used for carrying out transient modulation on the pre-stage pulse width modulation output signal, the delay response circuit is used for carrying out delay modulation on the pre-stage pulse width modulation output signal, and the normal response circuit is used for carrying out normal modulation on the pre-stage pulse width modulation output signal.

In another aspect, a digital pulse width modulation method is provided, including the steps of:

initializing a circuit for performing pre-stage pulse width modulation; initializing a reset time counter, and setting values of a time period register, a first comparison register, a second comparison register and a quantization control register;

the time counter counts upwards from 0, and self-increases by 1 every system clock period;

when the count value of the time counter is equal to the value of the time period register, counting downwards from the value of the time period register, and reducing 1 per system clock period; when the count value of the time counter is equal to 0, starting to count upwards from 0, and sequentially cycling; wherein, the direction signal is valid in the process of the up counting of the time counter, and is invalid in the process of the down counting;

comparing the value of the time counter with the value of 0, the value of the time period register, the value of the first comparison register and the value of the second comparison register respectively in real time, judging whether the values are equal, and generating corresponding control signals if the values are equal;

Outputting a pre-stage pulse width modulation output signal according to a first quantization rule when a corresponding control signal is valid or a control signal output by a normal state response circuit is valid according to the value of the quantization control register;

performing post-stage modulation on the pre-stage pulse width modulation output signal according to the value of the quantization control register, and outputting a pulse signal after post-stage pulse width modulation; the latter modulation includes transient modulation, delay modulation, or normal modulation.

One of the above technical solutions has the following advantages and beneficial effects:

according to the digital pulse width modulation circuit and the modulation method, through the modulation circuit architecture design of the basic circuit, the transient response circuit, the delay response circuit, the normal response circuit and the post-selection switch circuit, the reference pulse with a certain period and duty ratio is generated on the output signal of the basic circuit based on the basic circuit, and is used as the output of the front-stage pulse width modulation, and in the post-stage pulse width modulation, after the external event input signal is valid, the reference pulse is further modulated: the transient response circuit is used for carrying out transient modulation, the level output of pulse width modulation is temporarily and immediately controlled at an external event, the original level output is restored after the external event is cancelled, and the PWM state is strictly synchronous with the external event; or delay modulation based on a delay response circuit which delays after a lapse of a certain period of time (a pre-time) after an external event, and outputs a PWM level to a certain state and holds the same for a certain period of time (a post-time); or the normal state modulation is carried out based on the normal state response circuit and the basic circuit, after counting and counting the events after the external event comes, the period and the duty ratio of the PWM level output are changed at one time or periodically, so that three-dimensional response to the external event can be realized, and digital pulse signals with different time characteristics can be flexibly modulated. The method and the device can make multi-dimensional efficient response to the external event, flexibly modulate the digital pulse signals with different time characteristics, and achieve the effect of greatly improving the event response efficiency.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present application, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.

FIG. 1 is a schematic diagram of a digital pulse width modulation circuit in one embodiment;

FIG. 2 is a schematic diagram of a digital pulse width modulation circuit according to another embodiment;

FIG. 3 is a schematic diagram of the workflow of pre-pulse width modulation in one embodiment;

FIG. 4 is a schematic diagram of a delay modulation workflow in one embodiment;

FIG. 5 is a schematic diagram of a transient modulation workflow in one embodiment;

fig. 6 is a schematic diagram of normal modulation operation in one embodiment.

Detailed Description

The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It is noted that reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.

Those skilled in the art will appreciate that the embodiments described herein may be combined with other embodiments. The term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations. It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to and integrated with the other element or intervening elements may also be present. The terms "one end," "the other end," and the like are used herein for illustrative purposes only.

Embodiments of the present application will be described in detail below with reference to the attached drawings in the drawings of the embodiments of the present application.

In one embodiment, as shown in fig. 1, an embodiment of the present application provides a digital pulse width modulation circuit 100, which includes a base circuit 11, a transient response circuit 13, a delayed response circuit 15, a normal response circuit 17, and a post-select switch circuit 19. The signal output end of the basic circuit 11 is respectively connected with the signal input ends of the transient response circuit 13 and the delay response circuit 15, and the quantization control output end of the basic circuit 11 is respectively connected with the secondary quantization control input end of the delay response circuit 15 and the control input end of the post-selection switch circuit 19. The signal input end of the normal response circuit 17 is used for receiving an external event input signal, and the signal output ends of the normal response circuit 17 are respectively connected with the control input ends of the base circuit 11 and the delay response circuit 15.

The signal input terminal of the transient response circuit 13 is used for receiving an external event input signal, and the quantization control input terminal of the transient response circuit 13 is connected to the quantization control output terminal of the base circuit 11. The signal input end of the post-selection switch circuit 19 is respectively connected with the signal output ends of the delay response circuit 15 and the transient response circuit 13, and the signal output end of the post-selection switch circuit 19 is used for selecting and outputting the modulated pulse signal. The basic circuit 11 is configured to generate a pre-pulse width modulation output signal, the transient response circuit 13 is configured to transient modulate the pre-pulse width modulation output signal, the delay response circuit 15 is configured to delay-modulate the pre-pulse width modulation output signal, and the normal response circuit 17 is configured to normally modulate the pre-pulse width modulation output signal.

It will be appreciated that, as shown in fig. 1, the digital pwm circuit 100 includes a base circuit 11, a transient response circuit 13, a delay response circuit 15, a normal response circuit 17, and a post-selection switch circuit 19, and it should be noted that fig. 1 may also include an indication of an operating clock and a reset signal of a circuit, which are not shown, and those skilled in the art may choose to add these common components by themselves according to the normal operation requirement of the circuit.

Specifically, the external event input signal may be denoted as EXT_EVT, may be provided by an external device/circuit, and is indicative of an external event that requires a response by the digital pulse width modulation circuit 100. The preceding pulse width modulation is based on the basic circuit 11 generating a reference pulse with a certain period and duty cycle on its output signal. The transient response circuit 13 is a response circuit that immediately controls the PWM level output when an external event comes, and restores the original level output after the external event is canceled, while the PWM state is strictly synchronized with the external event. The delay response circuit 15 is a response circuit that outputs the PWM level to a certain state and holds the PWM level for a certain period of time (also referred to as a post-time) after a delay of one period of time (also referred to as a pre-time) has elapsed after the external event, and the delay time can be preset by software according to the delay response needs of different external events.

The normal response circuit 17 is a response circuit that counts an external event after the external event comes, and changes the period and duty ratio of the PWM level output at one time or periodically. The post-selection switch circuit 19 is a switch circuit for selectively outputting the pulse signal after final modulation. The transient response circuit 13, the delay response circuit 15 and the normal response circuit 17 can respectively realize three different post-stage pulse width modulation outputs, realize three-dimensional responses to external events, and flexibly and efficiently modulate digital pulse signals with different time characteristics. The purpose of the latter pulse width modulation is to further modulate the reference pulse output by the former pulse width modulation after the external event input signal ext_evt is valid, so as to form a pulse signal after transient modulation, delay modulation or normal modulation.

The digital pwm circuit 100 is designed by the modulation circuit architecture of the base circuit 11, the transient response circuit 13, the delay response circuit 15, the normal response circuit 17 and the post-selection switch circuit 19, and generates a reference pulse with a certain period and duty cycle on the output signal based on the base circuit 11, as the output of the preceding pulse width modulation, and in the following pulse width modulation, after the external event input signal is valid, the reference pulse is further modulated: that is, the transient response circuit 13 is used for performing transient modulation, which temporarily and immediately controls the level output of pulse width modulation at an external event, and restores the original level output after the external event is cancelled, so that the PWM state is strictly synchronous with the external event; or delay modulation based on the delay response circuit 15, which delays after a lapse of a certain period of time (a lead time) after an external event, and outputs a PWM level to a certain state and holds it for a certain period of time (a post time); or based on the normal state response circuit 17 and the basic circuit 11, after counting and counting the external event, the period and the duty ratio of the PWM level output are changed at one time or periodically, so that three-dimensional response to the external event can be realized, and digital pulse signals with different time characteristics can be flexibly modulated. The method and the device can make multi-dimensional efficient response to the external event, flexibly modulate the digital pulse signals with different time characteristics, and achieve the effect of greatly improving the event response efficiency.

In one embodiment, as shown in FIG. 2, the base circuit 11 includes a time counter TCTR, a time period register TPRD, a first compare register CMPA, a second compare register CMPB, a comparator CMP, quantization control registers EQC1-3, and an event quantizer EQ. The time counter TCTR is connected to the comparator CMP and the event quantizer EQ, respectively. The time period register TPRD, the first comparison register CMPA and the second comparison register CMPB are respectively connected to the comparator CMP. The comparator CMP is connected to the event quantizer EQ. The event quantizer EQ is connected to the normal response circuit 17, the transient response circuit 13, and the delay response circuit 15, respectively. The quantization control register EQC is connected to the event quantizer EQ, the transient response circuit 13, the delay response circuit 15, and the post-selection switch circuit 19, respectively.

The time counter TCTR is used for periodically counting and outputting a direction signal to the event quantizer EQ, and the comparator CMP is used for comparing the value of the time counter TCTR with 0, the value of the time period register TPRD, the value of the first comparison register CMPA and the value of the second comparison register CMPB, respectively, and generating a corresponding control signal when the values are equal. The quantization control register EQC is used for controlling the event quantizer EQ to output a pre-stage pulse width modulation output signal according to a first quantization rule.

It will be appreciated that the base circuit 11 may be part of a circuit for a wide variety of multi-bit (e.g., without limitation, 16-bit, 32-bit or 64-bit) PWM, the principles for implementing the pre-stage pulse width modulation function being similar. For ease of illustration and understanding, the following description will be given by taking 32 bits as an example.

The base circuit 11 comprises a time counter TCTR [31:0], a time period register TPRD [31:0], a first comparison register CMPA [31:0], a second comparison register CMPB [31:0], a comparator CMP, quantization control registers EQC1-3[31:0] and an event quantizer EQ, all of which can be directly employed as known in the art. The basic circuit 11 can efficiently complete the pre-stage pulse width modulation, and has simple circuit structure and high reliability.

Specifically, after the circuit initialization is completed, the time counter TCTR counts up from 0, and each system clock (SYSCLK) period is self-increased by 1; when the count value of the time counter TCTR is equal to the value TPRD preset by software in the time period register TPRD, the time counter TCTR starts counting downwards from the value TPRD, and each SYSCLK clock period is self-reduced by 1; when the time counter TCTR counts down to 0, the time counter TCTR starts to count up from 0; and sequentially circulating. The corresponding direction signal Dir during the up-counting of the time counter TCTR is active (e.g. may be indicated as active by a high level 1) and the corresponding direction signal Dir during the down-counting of the time counter TCTR is inactive (e.g. may be indicated as inactive by a low level 0).

The values of the first comparison register CMPA and the second comparison register CMPB can be preset by software, with values between 0 and TPRD, for comparison with the value of the time counter TCTR in the event quantizer EQ. The comparator CMP is configured to compare the value of the time counter TCTR with the value of 0, the value of the time period register TPRD, the value of the first comparison register CMPA and the value of the second comparison register CMPB, respectively, and determine whether the values are equal, and if the value of the time counter TCTR is equal to 0, the value of the time period register TPRD, the value of the first comparison register CMPA and the value of the second comparison register CMPB, respectively, generate corresponding control signals. The event quantizer EQ functions to change the output signal state of the event quantizer EQ when the corresponding control signal is active, according to the setting of the quantization control field of the quantization control register EQC.

In one embodiment, further, the respective control signals include a control signal eq_zero corresponding to 0, a control signal eq_tprd corresponding to a value of the time period register, a control signal eq_cmpa corresponding to a value of the first comparison register, a control signal eq_cmpb corresponding to a value of the second comparison register, and a control signal EVT output after processing by the normal state response circuit 17 corresponding to the external event input signal, and the preceding pulse width modulation output signal includes an output signal EQ1 and an output signal EQ2.

The first quantization rule includes:

setting the priority order of the control signals as EQ_ZERO > EQ_TPRD > EQ_CMPA > EQ_CMPB > EVT;

controlling the event quantizer output signal EQ1 by a first register EQC1 of the quantization control register; when the direction signal is valid, the first four quantization control domains of the upper position in the first register EQC1 are respectively used for sequentially associating each control signal according to the priority order, and when the direction signal is invalid, the four quantization control domains behind the first four quantization control domains are respectively used for sequentially associating each control signal according to the priority order;

controlling the event quantizer to output an output signal EQ2 by using a second register EQC2 of the quantization control register; when the direction signal is valid, the first four quantization control domains of the upper position in the second register EQC2 are respectively used for sequentially associating each control signal according to the priority order, and when the direction signal is invalid, the four quantization control domains behind the first four quantization control domains are respectively used for sequentially associating each control signal according to the priority order;

when the value of the quantization control field is 0, the output signal EQ1 or EQ2 is set to 1;

when the value of the quantization control field is 1, the output signal EQ1 or EQ2 is set to 0;

when the value of the quantization control domain is 2, the output signal EQ1 or EQ2 is kept in the original state;

Bypassing the associated control signal when the value of the quantized control field is 3; by-pass, the states of the output signals EQ1 and EQ2 are determined by the lower priority control signals and associated quantized control fields.

Specifically, when the value of the time counter TCTR is equal to 0, the generated control signal is denoted as eq_zero. When the value of the time counter TCTR is equal to the value of the time period register TPRD, the generated control signal is denoted as eq_tprd. When the value of the time counter TCTR is equal to the value of the first comparison register CMPA, the generated control signal is denoted as eq_cmpa. When the value of the time counter TCTR is equal to the value of the second comparison register CMPB, the generated control signal is denoted as eq_cmpb.

The event quantizer EQ is configured to change the states of the output signals EQ1 and EQ2 of the event quantizer EQ to 1 (active high), 0 (inactive low), maintain the original state, or ignore the control signals eq_zero, eq_prd, eq_cmpa, eq_cmpb, or the control signal EVT output from the normal response circuit 17 according to the settings of the 32-bit quantization control registers EQC1[31:0] and EQC2[31:0], when the control signals eq_zero, eq_prd, eq_cmpa, eq_cmpb, or the control signal EVT is active, as shown in the first quantization rule.

That is, the priority order of the control signals is: EQ_ZERO > EQ_TPRD > EQ_CMPA > EQ_CMPB > EVT. The first register EQC1[31:0] of the quantization control register is used for controlling the output signal EQ1, and the second register EQC2[31:0] of the quantization control register is used for controlling the output signal EQ2. When the direction signal Dir is 1 (active), the first four quantization control domains of the upper bits, namely quantization control domains EQC1[31:30], EQC1[29:28], EQC1[27:26], EQC1[25:24], and EQC1[23:22], are associated with control signals eq_zero, eq_prd, eq_cmpa, eq_cmpb, and EVT, respectively. When the direction signal Dir is 0 (inactive), the four quantization control domains following the first four quantization control domains, namely quantization control domains EQC1[21:20], EQC1[19:18], EQC1[17:16], EQC1[15:14] and EQC1[13:12], are associated with control signals eq_zero, eq_prd, eq_cmpa, eq_cmpb and EVT, respectively. The association of the fields with the control signals in the second register EQC2[31:0] of the quantization control register is similarly analogous.

By the quantization control mode, a high-efficiency pre-stage pulse width modulation effect is realized by finer and more accurate quantization control.

In one embodiment, as shown in fig. 2, the transient response circuit 13 includes a first selector 131, a second selector 132, a first logical and gate 133, and a second logical and gate 134. The signal input end of the first selector 131 is connected to the event quantizer EQ, the signal output end of the first selector 131 is connected to the first input end of the first logic and gate 133, the second input end of the first logic and gate 133 is used for receiving the external event input signal, and the output end of the first logic and gate 133 is connected to the signal input end of the post-selection switch circuit 19. The signal input end of the second selector 132 is connected to the event quantizer EQ, the signal output end of the second selector 132 is connected to the first input end of the second logic and gate 134, the second input end of the second logic and gate 134 is configured to receive an external event input signal, and the output end of the second logic and gate 134 is connected to the signal input end of the post-selection switch circuit 19. Control inputs of the first selector 131 and the second selector 132 are respectively connected to a quantization control register EQC of the base circuit 15.

It can be appreciated that by adopting the transient response circuit 13 of the above-described simple structure, the transient modulation output can be efficiently and reliably supported. Specifically, the transient response circuit 13 is composed of 2 one-out-of-three (e.g., but not limited to, one-out-of-three) selectors and 2 logical AND gates, and functions to immediately respond to the external event input signal EXT_EVT when the external event input signal EXT_EVT is active and allow its output signals RP1 and RP2 to be driven by the outputs of the selectors, and to turn off its output signals RP1 and RP2 when the external event input signal EXT_EVT is inactive. The source of the output signal RP1 may be 0, 1 or the output signal EQ1 of the event quantizer EQ, controlled by the field EQC3[9:8] of the third register EQC3 of the quantization control register; the source of the output signal RP2 may be 0, 1 or the output signal EQ2 of the event quantizer EQ, controlled by the field EQC3[11:10] of the third register EQC3 of the quantization control register.

In one embodiment, as shown in fig. 2, the delay response circuit 15 includes a pre-counter prednt, a post-counter POSCNT, and a secondary quantizer SEQ. The control input of the front counter is used to access the external event input signal ext_evt. The control input end of the back counter is connected with the control output end of the front counter. The signal input end of the secondary quantizer is respectively connected with the signal output ends of the event quantizer, the front counter and the rear counter, the signal output end of the secondary quantizer is connected with the signal input end of the rear selection switch circuit 19, and the control input end of the secondary quantizer is connected with the quantization control register.

The pre-counter is used for starting counting and setting the first output signal to be effective when the external event input signal is converted into the effective state, stopping counting when the counting reaches a pre-counting threshold value, setting the second output signal to be effective and carrying out counting zero clearing. The post counter is used for starting counting when the second output signal is effective, stopping counting when the counting reaches a post counting threshold value, setting the third output signal to be effective and carrying out counting zero clearing. The secondary quantizer is used for performing delay modulation according to a second quantization rule when the output signal of the counter is valid under the control of the quantization control register; the counter output signal comprises a first output signal, a second output signal or a third output signal.

The components used in the delay response circuit 15 may be various counters and quantizers known in the art, and the circuit structure of the delay response circuit 15 may be designed to efficiently and reliably support the implementation of delay modulation. Specifically, for example, the delay response circuit 15 may include a 32-bit pre-counter pre [31:0], a 32-bit post-counter post [31:0] and a secondary quantizer SEQ, which generally functions to respond to an external event and keep the processing result for a certain time after a certain delay when the external event input signal ext_evt makes a 0 (low level inactive) - >1 (high level active) transition.

When the external event input signal ext_evt transitions 0 (inactive low) - >1 (active high), the pre-counter pred starts counting from 0, self-incrementing by 1 every SYSCLK clock period, while the first output signal Start of the pre-counter pred is active. The counter Stop is stopped when the count of the pre-counter pre reaches its set threshold value pre, and its second output signal Stop1 is active, while the pre-counter pre is cleared.

When the second output signal Stop1 of the pre-counting process is valid, the post-counter POSCNT starts counting from 0; when the count of the post counter POSCNT reaches the set threshold value POSVAL, the count is stopped, the third output signal Stop2 is valid, and the post counter POSCNT is cleared. The function of the secondary quantizer SEQ is to change the state of the delayed response output signal RP3 of the secondary quantizer SEQ to be 1 (high level), 0 (low level), maintain the original state or ignore the control signal when the output control signals Start, stop1 or Stop2 of the front counting and rear counting processes are valid according to the setting of the third register EQC3[31:0] of the 32-bit quantization control register, and change the state of the delayed response output signal RP4 of the secondary quantizer SEQ to be 1 (high level), 0 (low level), maintain the original state or ignore the control signal.

In one embodiment, further, the delay modulated output signals include a delay responsive output signal RP3 and a delay responsive output signal RP4. The second quantization rule includes:

setting the priority order of the output signals of the counter as the first output signal Start > the second output signal Stop1> the third output signal Stop2;

controlling the secondary quantizer to output the delayed response output signal RP3 or the delayed response output signal RP4 by using a third register EQC3 of the quantization control register; the first three quantization control domains of the upper order in the third register EQC3 are respectively used to sequentially associate the output signals of the counters according to the priority order, the adjacent three quantization control domains after the first three quantization control domains are respectively used to sequentially associate the control signals according to the priority order, the first three quantization control domains correspond to the delayed response output signals RP3, and the adjacent three quantization control domains correspond to the delayed response output signals RP4;

setting the delayed response output signal RP3 or RP4 to 1 when the value of the quantization control field is 0;

setting the delayed response output signal RP3 or RP4 to 0 when the value of the quantization control field is 1;

when the value of the quantization control field is 2, the delayed response output signal RP3 or RP4 is kept in the original state;

Bypassing the associated control signal when the value of the quantized control field is 3; by-pass, the state of the delayed response output signals RP3 and RP4 is determined by the lower priority counter output signals and associated quantization control fields.

Specifically, the priority order of the control signals is: start > Stop1> Stop2. The third register EQC3[31:26] of the quantization control register is used for controlling the delayed response output signal RP3, and the third register EQC3[23:18] is used for controlling the delayed response output signal RP4. The first three quantization control fields EQC3[31:30], EQC3[29:28] and EQC3[27:26] in the upper bits of the third register EQC3 are respectively associated with counter output signals Start, stop1 and Stop2; the next three quantization control fields, EQC3[23:22], EQC3[21:20], and EQC3[19:18], after the first three quantization control fields, are associated with counter output signals Start, stop1, and Stop2, respectively.

The quantization control field has a value of 0, 1, 2, or 3, which indicates that the delayed response output signal RP3 or RP4 is set to 1, 0, left in the original state, or bypassed (i.e., ignored) when the corresponding counter output signal is active, respectively. By-pass, the state of the delayed response output signals RP3 and RP4 is determined by the lower priority counter output signals and their associated quantization control domains. By the above secondary quantization control, delay modulation can be realized with high accuracy and high efficiency.

In one embodiment, as shown in fig. 2, the normal response circuit 17 includes an event counter EXTCNT, an input terminal of the event counter EXTCNT is used for receiving an external event input signal, and a signal output terminal of the event counter EXTCNT is connected to the event quantizer EQ of the base circuit 11.

It will be appreciated that the normal response circuit 17 may comprise a 16-bit event counter EXTCNT [15:0], with the same thing being true for higher bit number circuits. The normal response is completed by the event counter EXTCNT together with the above described basic circuit 11. The initial value of the event counter EXTCNT may be set to 0; the count of the event counter EXTCNT is self-incremented by 1 whenever a 0 (low level) - >1 (high level) transition occurs in the external event input signal ext_evt; when the count of the event counter EXTCNT reaches its set threshold EVTVAL, the control signal EVT output to the base circuit 11 is valid, while the event counter EXTCNT is cleared. The base circuit 11 decides to set the outputs EQ1 and EQ2 of the event quantizer EQ to 1, 0, to maintain the original state or to bypass the control signal (ignore the control signal) according to the first quantization rule described above.

If the external event input signal ext_evt is a periodic signal, the event counter EXTCNT may output a periodic control signal EVT, which may be used to modulate the period and duty cycle of the pulses in the base circuit 11. The external event input signal EXT_EVT can be efficiently and accurately modulated and output in a normal state based on the event counter EXTCNT, and the circuit is simple in structure and high in reliability.

It should be noted that, in the above embodiments, the set threshold values may be preset by software or set in real time according to the modulation requirements in practical applications.

In one embodiment, as shown in fig. 2, the post-selection switch circuit 19 includes a first selection switch M1 and a second selection switch M2. The first input end of the first selection switch M1 is connected to the first signal output end of the transient response circuit 13, the second input end of the first selection switch M1 is connected to the first signal output end of the delay response circuit 15, and the output end of the first selection switch M1 is used for selecting the first output signal of the transient response circuit 13 or the first output signal of the delay response circuit 15 to be output as a modulated pulse signal.

The first input end of the second selection switch M2 is connected to the second signal output end of the transient response circuit 13, the second input end of the second selection switch M2 is connected to the second signal output end of the delay response circuit 15, and the output end of the second selection switch M2 is used for selecting the second output signal of the transient response circuit 13 or the second output signal of the delay response circuit 15 to output as a modulated pulse signal. The control input ends of the first selection switch M1 and the second selection switch M2 are respectively connected with a quantization control register.

Specifically, in the post-selection switch circuit 19, the first selection switch M1 is controlled by the quantization control field EQC3[0] of the quantization control register, and functions to generate the modulated output pulse signal PWMA from the first output signal RP1 of the transient response circuit 13 and the first output signal RP3 of the delay response circuit 15. The second selection switch M2 is controlled by the quantization control field EQC3[1] of the quantization control register, and functions to generate the modulated output pulse signal PWMB from the second output signal RP2 of the transient response circuit 13 and the second output signal RP4 of the delay response circuit 15.

By using the post-selection switch circuit 19 with the above structure, efficient pulse signal selection output can be realized, and meanwhile, the circuit complexity is further reduced.

In one embodiment, there is also provided a digital pulse width modulation method comprising the steps of:

outputting a pre-stage pulse width modulation output signal according to a first quantization rule when a corresponding control signal is valid or a control signal output by the normal state response circuit 17 is valid according to a value of the quantization control register;

It will be appreciated that the circuit structure in the embodiments of the method may be understood by referring to the corresponding circuit structure in the embodiments of the digital pwm circuit 100, and the detailed description will not be repeated here and hereinafter. The working process of the digital pulse width modulation method can be divided into two stages: preceding pulse width modulation and succeeding pulse width modulation. The effect of the preceding pulse width modulation is to generate a reference pulse with a certain period and duty cycle on the output signals EQ1 and EQ2 of the event quantizer based on the base circuit 11; the purpose of the latter pulse width modulation is to further modulate the aforementioned reference pulse after the external event input signal ext_evt is valid, to form a transient, delay-modulated or normally-modulated pulse signal, respectively, according to the response needs to the external event.

Specifically, as shown in fig. 3, the operation of the preceding pulse width modulation includes 4 steps: initialization, counting, comparison and quantization. Step 1, initializing a circuit: resetting a time counter TCTR; the time period register TPRD, the first comparison register CMPA, the second comparison register CMPB, and the quantization control register EQC1-2 are set.

Step 2, counting: after the initialization is finished, the time counter TCTR starts to count upwards from 0, and each system clock period is increased by 1; when the count value of the time counter TCTR is equal to the value of the time period register TPRD, counting downwards from the value of the time period register TPRD, and reducing 1 per system clock period; when the count value of the time counter TCTR is equal to 0, the time counter TCTR starts counting up from 0, and then loops. The direction signal Dir during the up-counting of the time counter TCTR is 1 (active high) and the direction signal Dir during the down-counting is 0 (inactive low).

Step 3, comparison: the value of the time counter TCTR is respectively compared with the values of 0, TPRD, CMPA and CMPB in real time to judge whether the values are equal, and if the values are equal, corresponding control signals EQ_ZERO, EQ_TPRD, EQ_CMPA or EQ_CMPB are generated.

And 4, quantifying: depending on the settings of the first and second registers EQC1 and EQC2 in the quantization control register, when the control signal eq_zero, eq_prd, eq_cmpa, or eq_cmpb output in step 3 is valid, or the control signal EVT output from the normal response circuit 17 is valid, the states of the output signals EQ1 and EQ2 are changed to 1 (high level), 0 (low level), the original state is maintained, or the control signal is ignored.

The above-mentioned digital pulse width modulation method is to generate a reference pulse having a certain period and duty ratio on its output signal based on the base circuit 11 as an output of the preceding pulse width modulation, and in the following pulse width modulation, the reference pulse is further modulated after the external event input signal is valid: that is, the transient response circuit 13 is used for performing transient modulation, which temporarily and immediately controls the level output of pulse width modulation at an external event, and restores the original level output after the external event is cancelled, so that the PWM state is strictly synchronous with the external event; or delay modulation based on the delay response circuit 15, which delays after a lapse of a certain period of time (a lead time) after an external event, and outputs a PWM level to a certain state and holds it for a certain period of time (a post time); or based on the normal state response circuit 17 and the basic circuit 11, after counting and counting the external event, the period and the duty ratio of the PWM level output are changed at one time or periodically, so that three-dimensional response to the external event can be realized, and digital pulse signals with different time characteristics can be flexibly modulated. The method and the device can make multi-dimensional efficient response to the external event, flexibly modulate the digital pulse signals with different time characteristics, and achieve the effect of greatly improving the event response efficiency.

In one embodiment, the respective control signals include a control signal eq_zero corresponding to 0, a control signal eq_tprd corresponding to a value of the time period register, a control signal eq_cmpa corresponding to a value of the first comparison register, a control signal eq_cmpb corresponding to a value of the second comparison register, and a control signal EVT output after processing by the normal response circuit 17 corresponding to the external event input signal, and the preceding pulse width modulation output signal includes an output signal EQ1 and an output signal EQ2. The first quantization rule includes:

In one embodiment, the process of delay modulation includes:

initializing the delay response circuit 15; initializing comprises setting a threshold value of a front counter and a threshold value of a rear counter, setting a third register EQC3 of a quantization control register, and resetting the front counter and the rear counter;

performing front-end counting; the pre-counting comprises the steps that after an external event input signal is converted into a valid state, the pre-counter starts counting from 0 and the first output signal Start is valid, when the value of the pre-counter reaches a threshold value, the counting is stopped and cleared, and the second output signal Stop1 is valid;

performing post counting; the post counting comprises that after the second output signal Stop1 is effective, the post counter starts counting from 0, and stops counting and clears when the value of the post counter reaches a threshold value, and meanwhile the third output signal Stop2 is effective;

Performing secondary quantization processing according to a second quantization rule; the second quantization rule includes:

setting the priority order of the output signals of the counter as Start > Stop1> Stop2;

bypassing the associated control signal when the value of the quantized control field is 3; by-pass, the state of the delayed response output signals RP3 and RP4 is determined by the lower priority counter output signal and associated quantization control domain;

The selection switch M1 in the post-selection switch circuit 19 is controlled to select the delayed-response output signal RP3 to generate the delayed-modulated pulse signal by using the fields EQC3[0] and EQC3[1] in the third register EQC3 of the quantization control register, respectively, and the selection switch M2 is controlled to select the delayed-response output signal RP4 to generate the modulated pulse signal.

Specifically, the delay modulation is based on the delay response circuit 15 processing the pre-stage pwm output signals EQ1 and EQ2 after a certain delay when the external event input signal ext_evt is converted to 0 (low level) - >1 (high level), and holding the processing result for a certain time. As shown in fig. 4, the workflow includes 5 steps: initialization, pre-counting, post-counting, secondary quantization and post-gating.

Step 1, initializing: the pre-count threshold PREVAL and the post-count threshold POSVAL are set, the quantization control register fields EQC3[31:26], EQC3[23:18], EQC3[1], EQC3[0] are set, and the pre-counter PRECNT and the post-counter POSCNT are cleared.

Step 2, pre-counting: after the external event input signal ext_evt is converted by 0 (low level) - >1 (high level), the pre-counter prednt starts counting from 0, and the output signal Start is valid; when the presnt value reaches the threshold presal, the count is stopped and cleared, while the output signal Stop1 is active.

Step 3, post counting: after the output signal Stop1 of the front counting in the step 2 is valid, the post counter POSCNT starts counting from 0; when the count reaches the threshold value POSVAL, the count is stopped and cleared, and the output signal Stop2 is valid.

Step 4, secondary quantization: according to the settings of register fields EQC3[31:26] and EQC3[23:18], when the output signal Start, stop1 or Stop2 of the step 2 front count, step 3 back count is active, the state of the output signals RP3 and RP4 is changed to 1 (high level), 0 (low level) is kept in the original state or the control signal is ignored. The specific quantization rule is as shown in the aforementioned second quantization rule.

In one embodiment, the process of transient modulation includes:

initializing a quantization control register; initialization includes setting quantization control register fields EQC3[9:8], EQC3[11:10], EQC3[0] and EQC3[1];

during the period when the external event input signal is active, the level of the transient response output signal RP1 is controlled to be driven by 0, 1 or the output signal EQ1 according to the domains EQC3[9:8] and EQC3[11:10], and the level of the transient response output signal RP2 is controlled to be driven by 0, 1 or the output signal EQ 2;

the fields EQC3[0] and EQC3[1] are used to control the selection switch M1 in the post-selection switch circuit 19 to select the transient response output signal RP1 to generate the transient modulated pulse signal and the selection switch M2 to select the transient response output signal RP2 to generate the transient modulated pulse signal.

Specifically, the pre-stage pwm output signals EQ1 and EQ2 are immediately processed when the external event input signal ext_evt is active, and the processing is stopped immediately after the external event input signal ext_evt is deactivated, based on the transient response circuit 13. As shown in fig. 5, the workflow includes 3 steps: initialization, level control and post gating.

Step 1, initializing: the quantization control register fields EQC3[9:8], EQC3[11:10], EQC3[0] and EQC3[1] are set.

Step 2, level control: during the period when the external event input signal EXT_EVT is active, the domains EQC3[9:8], EQC3[11:10] control the level of the output signal RP1 to be driven by 0, 1 or the output signal EQ1, and the level of the output signal RP2 to be driven by 0, 1 or the output signal EQ2, respectively.

Step 3, post-stage gating: the fields EQC3[0] and EQC3[1] control the selection switches M1, M2 in the post-selection switch circuit 19, respectively, and select RP1 to generate the modulated output pulse signal PWMA and RP2 to generate the modulated output pulse signal PWMB, respectively.

In one embodiment, the normal modulation process includes:

initializing an event threshold value and resetting an event counter;

each time when an external event input signal is converted into an effective event counter is automatically increased by 1, the event counter is cleared when the count reaches an event threshold value, and meanwhile, an output signal EVT is set to be effective and the quantization operation in the prior-stage pulse width modulation is triggered;

When the output signal EVT is active, the preceding stage pwm output signal is output according to the first quantization rule according to the settings of the quantization control registers EQC1 and EQC 2.

Specifically, based on the normal response circuit 17 and the base circuit 11, when the external event input signal ext_evt is converted into 0 (low level) - >1 (high level), the number of events is counted and then the quantization of step 4 in the preceding pulse width modulation process is triggered, and the period and duty ratio of the output pulse signals EQ1 and EQ2 are changed once or periodically. As shown in fig. 6, the workflow includes several steps: initializing, counting events and quantifying.

Step 1, initializing: an event threshold EVTVAL is set and an event counter EVTCNT is cleared.

Step 2, event statistics: the counter EXTCNT is incremented by 1 whenever the external event input signal ext_evt transitions 0 (low level) - >1 (high level), and is cleared when the counter EXTCNT count reaches the threshold EVTVAL, while the output signal EVT is valid, triggering step 4 quantization in the preceding pulse width modulation.

And 3, quantifying: when the control signal EVT is active, the states of the output signals EQ1 and EQ2 are changed according to the settings of the quantization control registers EQC1 and EQC2, the quantization rule of which is the same as the step 4 quantization in the preceding pulse width modulation.

It should be noted that the description of the features in the embodiments of the method may be the same as the description of the corresponding embodiments of the digital pwm circuit 100.

It should be understood that, although the steps in the flowcharts of fig. 3 to 6 are sequentially shown as indicated by arrows, these steps are not necessarily sequentially performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Furthermore, at least a portion of the steps of fig. 3-6 may include multiple sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, nor does the order in which the sub-steps or stages are performed necessarily occur sequentially, but may be performed alternately or alternately with at least a portion of the sub-steps or stages of other steps or other steps.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description. The foregoing examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it is possible for those skilled in the art to make several variations and modifications without departing from the spirit of the present application, which fall within the protection scope of the present application. The scope of the application is therefore intended to be covered by the appended claims.

Claims

1. The digital pulse width modulation circuit is characterized by comprising a basic circuit, a transient response circuit, a delay response circuit, a normal response circuit and a post-selection switch circuit;

the signal input end of the transient response circuit is used for receiving the external event input signal, the quantization control input end of the transient response circuit is connected with the quantization control output end of the basic circuit, the signal input ends of the post-selection switch circuit are respectively connected with the signal output ends of the delay response circuit and the transient response circuit, and the signal output end of the post-selection switch circuit is used for selecting and outputting the modulated pulse signal;

The basic circuit is used for generating a pre-stage pulse width modulation output signal, the transient response circuit is used for carrying out transient modulation on the pre-stage pulse width modulation output signal, the delay response circuit is used for carrying out delay modulation on the pre-stage pulse width modulation output signal, and the normal response circuit is used for carrying out normal modulation on the pre-stage pulse width modulation output signal;

the basic circuit comprises a time counter, a time period register, a first comparison register, a second comparison register, a comparator, a quantization control register and an event quantizer;

the time counter is respectively connected with the comparator and the event quantizer, the time period register, the first comparison register and the second comparison register are respectively connected with the comparator, the comparator is connected with the event quantizer, the event quantizer is respectively connected with the normal state response circuit, the transient state response circuit and the delay response circuit, and the quantization control register is respectively connected with the event quantizer, the delay response circuit, the transient state response circuit and the post-selection switch circuit;

the time counter is used for periodically counting and outputting a direction signal to the event quantizer, and the comparator is used for comparing the value of the time counter with 0, the value of the time period register, the value of the first comparison register and the value of the second comparison register respectively and generating corresponding control signals when the values are equal;

The quantization control register is used for controlling the event quantizer to output the pre-stage pulse width modulation output signal according to a first quantization rule.

2. The digital pulse width modulation circuit of claim 1, wherein the respective control signals comprise a control signal eq_zero corresponding to 0, a control signal eq_tprd corresponding to the value of the time period register, a control signal eq_cmpa corresponding to the value of the first comparison register, a control signal eq_cmpb corresponding to the value of the second comparison register, and a control signal EVT corresponding to the external event input signal that is output after processing by the normal response circuit, the pre-stage pulse width modulation output signal comprising an output signal EQ1 and an output signal EQ2;

the first quantization rule includes:

controlling the event quantizer to output the output signal EQ1 by using a first register EQC1 of the quantization control register; when the direction signal is valid, the first four quantization control domains at the upper position in the first register EQC1 are respectively used to sequentially associate each control signal according to the priority order, and when the direction signal is invalid, the four quantization control domains after the first four quantization control domains are respectively used to sequentially associate each control signal according to the priority order;

Controlling the event quantizer to output the output signal EQ2 by using a second register EQC2 of the quantization control register; when the direction signal is valid, the first four quantization control domains of the high order in the second register EQC2 are respectively used to sequentially associate each control signal according to the priority order, and when the direction signal is invalid, the four quantization control domains after the first four quantization control domains are respectively used to sequentially associate each control signal according to the priority order;

setting the output signal EQ1 or EQ2 to 1 when the value of the quantization control field is 0;

setting the output signal EQ1 or EQ2 to 0 when the value of the quantization control field is 1;

when the value of the quantization control domain is 2, the output signal EQ1 or EQ2 is kept in an original state;

3. The digital pulse width modulation circuit of claim 1 or 2, wherein the transient response circuit comprises a first selector, a second selector, a first logical and gate, and a second logical and gate;

The signal input end of the first selector is connected with the event quantizer, the signal output end of the first selector is connected with the first input end of the first logic AND gate, the second input end of the first logic AND gate is used for receiving the external event input signal, and the output end of the first logic AND gate is connected with the signal input end of the post-selection switch circuit;

the signal input end of the second selector is connected with the event quantizer, the signal output end of the second selector is connected with the first input end of the second logic AND gate, the second input end of the second logic AND gate is used for receiving the external event input signal, and the output end of the second logic AND gate is connected with the signal input end of the post-selection switch circuit;

and the control input ends of the first selector and the second selector are respectively connected with the quantization control register.

4. The digital pulse width modulation circuit of claim 1 or 2, wherein the delay response circuit comprises a pre-counter, a post-counter, and a secondary quantizer;

the control input end of the front-end counter is used for accessing the external event input signal, the control input end of the rear-end counter is connected with the control output end of the front-end counter, the signal input ends of the secondary quantizer are respectively connected with the event quantizer, the front-end counter and the signal output end of the rear-end counter, the signal output end of the secondary quantizer is connected with the signal input end of the rear-end selection switch circuit, and the control input end of the secondary quantizer is connected with the quantization control register;

The front counter is used for starting counting and setting the first output signal to be effective when the external event input signal is converted into the effective signal, stopping counting when the counting reaches a front counting threshold value, setting the second output signal to be effective and carrying out counting zero clearing;

the post counter is used for starting counting when the second output signal is effective, stopping counting when the counting reaches a post counting threshold value, setting a third output signal to be effective and carrying out counting zero clearing;

the secondary quantizer is used for performing delay modulation according to a second quantization rule when the output signal of the counter is valid under the control of the quantization control register; the counter output signal comprises the first output signal, the second output signal or the third output signal.

5. The digital pulse width modulation circuit of claim 4, wherein the delay modulated output signal comprises a delay responsive output signal RP3 and a delay responsive output signal RP4;

the second quantization rule includes:

controlling the secondary quantizer to output the delayed response output signal RP3 or the delayed response output signal RP4 by using a third register EQC3 of the quantization control register; the first three quantization control domains in the upper order in the third register EQC3 are respectively configured to sequentially associate each of the counter output signals according to the priority order, and the adjacent three quantization control domains after the first three quantization control domains are respectively configured to sequentially associate each of the control signals according to the priority order, where the first three quantization control domains correspond to the delayed response output signal RP3, and the adjacent three quantization control domains correspond to the delayed response output signal RP4;

when the value of the quantization control field is 2, the delay response output signal RP3 or RP4 is kept in the original state;

bypassing the associated control signal when the value of the quantized control field is 3; by-pass, the state of the delayed response output signals RP3 and RP4 is determined by the lower priority counter output signals and associated quantization control domain.

6. The digital pulse width modulation circuit of claim 1 or 2, wherein the normalcy response circuit comprises an event counter having an input for receiving the external event input signal, the event counter having a signal output coupled to the event quantizer.

7. The digital pulse width modulation circuit of claim 1 or 2, wherein the post-select switch circuit comprises a first select switch and a second select switch;

the first input end of the first selection switch is connected with the first signal output end of the transient response circuit, the second input end of the first selection switch is connected with the first signal output end of the delay response circuit, and the output end of the first selection switch is used for selecting the first output signal of the transient response circuit or the first output signal of the delay response circuit to be output as the modulated pulse signal;

The first input end of the second selection switch is connected with the second signal output end of the transient response circuit, the second input end of the second selection switch is connected with the second signal output end of the delay response circuit, and the output end of the second selection switch is used for selecting a second output signal of the transient response circuit or a second output signal of the delay response circuit to be output as the modulated pulse signal;

and control input ends of the first selection switch and the second selection switch are respectively connected with the quantization control register.

8. A digital pulse width modulation method comprising the steps of:

initializing a circuit for performing pre-stage pulse width modulation; the initialization includes resetting a time counter, setting values of a time period register, a first comparison register, a second comparison register and a quantization control register;

9. The digital pulse width modulation method of claim 8, wherein the respective control signals comprise a control signal eq_zero corresponding to 0, a control signal eq_tprd corresponding to a value of the time period register, a control signal eq_cmpa corresponding to a value of the first comparison register, a control signal eq_cmpb corresponding to a value of the second comparison register, and a control signal EVT output after processing by a steady state response circuit corresponding to an external event input signal, the pre-stage pulse width modulation output signal comprising an output signal EQ1 and an output signal EQ2;

The first quantization rule includes:

controlling an event quantizer to output the output signal EQ1 by using a first register EQC1 of the quantization control register; when the direction signal is valid, the first four quantization control domains at the upper position in the first register EQC1 are respectively used to sequentially associate each control signal according to the priority order, and when the direction signal is invalid, the four quantization control domains after the first four quantization control domains are respectively used to sequentially associate each control signal according to the priority order;

10. The digital pulse width modulation method of claim 8, wherein the delay modulation process comprises:

initializing a delay response circuit; the initialization comprises the steps of setting a threshold value of a front counter and a threshold value of a rear counter, setting a third register EQC3 of a quantization control register, and resetting the front counter and the rear counter;

performing front-end counting; the pre-counting comprises the steps that after an external event input signal is converted into an effective state, the pre-counter starts counting from 0 and a first output signal Start is effective, when the value of the pre-counter reaches a threshold value, the counting is stopped and cleared, and a second output signal Stop1 is effective;

controlling the secondary quantizer to output a delayed response output signal RP3 or a delayed response output signal RP4 by using a third register EQC3 of the quantization control register; the first three quantization control domains in the upper order in the third register EQC3 are respectively configured to sequentially associate each of the counter output signals according to the priority order, and the adjacent three quantization control domains after the first three quantization control domains are respectively configured to sequentially associate each of the control signals according to the priority order, where the first three quantization control domains correspond to the delayed response output signal RP3, and the adjacent three quantization control domains correspond to the delayed response output signal RP4;

Bypassing the associated control signal when the value of the quantized control field is 3; bypassing, the state of the delayed response output signals RP3 and RP4 is determined by the lower priority counter output signal and associated quantization control domain;

and utilizing domains EQC3[0] and EQC3[1] in a third register EQC3 of the quantization control register to respectively control a selection switch M1 in a post selection switch circuit to select the delay response output signal RP3 to generate a pulse signal after delay modulation, and controlling a selection switch M2 to select the delay response output signal RP4 to generate a pulse signal after modulation.

11. The digital pulse width modulation method according to any one of claims 8 to 10, wherein the transient modulation process comprises:

initializing a quantization control register; the initializing includes setting quantization control register fields EQC3[9:8], EQC3[11:10], EQC3[0] and EQC3[1];

The fields EQC3[0] and EQC3[1] are utilized to respectively control a selection switch M1 in a post selection switch circuit to select the transient response output signal RP1 to generate a transient modulated pulse signal, and a selection switch M2 to select the transient response output signal RP2 to generate a transient modulated pulse signal.

12. The digital pulse width modulation method according to any one of claims 8 to 10, wherein the normal modulation process comprises:

initializing an event threshold value and resetting an event counter;

each time when an external event input signal is converted into effective, the event counter is automatically increased by 1, the event counter is cleared when the count reaches the event threshold value, and meanwhile, an output signal EVT is set to be effective and the quantization operation in the prior-stage pulse width modulation is triggered;

when the output signal EVT is valid, a preceding-stage pulse width modulated output signal is output according to the first quantization rule in accordance with the settings of the quantization control registers EQC1 and EQC 2.