CN115913189A

CN115913189A - Digital pulse width modulation circuit and modulation method

Info

Publication number: CN115913189A
Application number: CN202211325881.5A
Authority: CN
Inventors: 陈虎; 邓梁; 彭石
Original assignee: Hunan Guliang Microelectronics Co ltd
Current assignee: Hunan Guliang Microelectronics Co ltd
Priority date: 2022-10-27
Filing date: 2022-10-27
Publication date: 2023-04-04
Anticipated expiration: 2042-10-27
Also published as: CN115913189B

Abstract

The application relates to a digital pulse width modulation circuit and a modulation method. The basic circuit is used for generating a preceding-stage pulse width modulation output signal, the transient response circuit is used for carrying out transient modulation on the preceding-stage pulse width modulation output signal, the delay response circuit is used for carrying out delay modulation on the preceding-stage pulse width modulation output signal, the normal response circuit is used for carrying out normal modulation on the preceding-stage pulse width modulation output signal, and the signal output end of the post-selection switch circuit is used for selectively outputting the modulated pulse signal. According to the scheme, multi-dimensional high-efficiency response can be performed on the external event, digital pulse signals with different time characteristics can be flexibly modulated, and the event response efficiency is greatly improved.

Description

Digital pulse width modulation circuit and modulation method

Technical Field

The invention belongs to the technical field of pulse width modulation, and relates to a digital pulse width modulation circuit and a modulation method.

Background

Digital Pulse Width Modulation (DPWM) is widely used in many control fields of measurement, communication, power control and conversion, such as instrumentation, robot servos, motor drives, frequency converters, switching power supplies, and photovoltaic inversion. Generally, a PWM pulse in a control system has a certain period and duty ratio, and is used to control the on/off of each switching device in the circuit, and the period and duty ratio of the PWM pulse are not changed after being set. However, the control system (e.g., pipeline, etc.) also needs to respond to external events to perform such operations as start-up, braking, acceleration, and deceleration. In the process of implementing the present invention, the inventor finds that the traditional digital pulse width modulation technology has the technical problem of low event response efficiency.

Disclosure of Invention

In view of the problems in the conventional methods, the present invention provides a digital pulse width modulation circuit and a digital pulse width modulation method, which can make multi-dimensional efficient response to external events and flexibly modulate digital pulse signals with different time characteristics.

In order to achieve the above purpose, the embodiment of the present invention adopts the following technical solutions:

on one hand, the digital pulse width modulation circuit comprises a basic circuit, a transient response circuit, a delay response circuit, a normal response circuit and a post-selection switch circuit;

the signal output end of the basic circuit is respectively connected with the signal input ends of the transient response circuit and the delay response circuit, the quantization control output end of the basic circuit is respectively connected with the secondary quantization control input end of the delay response circuit and the selection control input end of the post selection switch circuit, the signal input end of the normal state response circuit is used for receiving an external event input signal, and the signal output end of the normal state response circuit is respectively connected with the control input ends of the basic circuit and the delay response circuit;

the signal input end of the transient response circuit is used for receiving an external event input signal, the quantization control input end of the transient response circuit is connected with the quantization control output end of the basic circuit, the signal input end of the post selection switch circuit is respectively connected with the signal output ends of the delay response circuit and the transient response circuit, and the signal output end of the post selection switch circuit is used for selectively outputting a modulated pulse signal;

the basic circuit is used for generating a preceding-stage pulse width modulation output signal, the transient response circuit is used for carrying out transient modulation on the preceding-stage pulse width modulation output signal, the delay response circuit is used for carrying out delay modulation on the preceding-stage pulse width modulation output signal, and the normal response circuit is used for carrying out normal modulation on the preceding-stage pulse width modulation output signal.

In another aspect, a digital pulse width modulation method is provided, including the steps of:

initializing a circuit for performing preceding-stage pulse width modulation; initializing a time counter including resetting, and setting values of a time period register, a first comparison register, a second comparison register and a quantization control register;

the time counter starts counting up from 0 and is automatically increased by 1 every system clock period;

when the count value of the time counter is equal to the value of the time period register, counting downwards from the value of the time period register, and subtracting 1 from each system clock period; when the count value of the time counter is equal to 0, counting up from 0, and circulating in sequence; the time counter is used for counting up and down, wherein the direction signal is effective in the process of counting up and ineffective in the process of counting down;

comparing the value of the time counter with 0, the value of the time period register, the value of the first comparison register and the value of the second comparison register respectively in real time, judging whether the values are equal, and if so, generating a corresponding control signal;

according to the value of the quantization control register, when a corresponding control signal is effective or a control signal output by the normal state response circuit is effective, outputting a preceding-stage pulse width modulation output signal according to a first quantization rule;

according to the value of the quantization control register, performing post-stage modulation on the pre-stage pulse width modulation output signal, and outputting a pulse signal after the post-stage pulse width modulation; the latter modulation includes transient modulation, delay modulation, or normal modulation.

One of the above technical solutions has the following advantages and beneficial effects:

in the digital pulse width modulation circuit and the modulation method, by the structural design of the modulation circuit of the basic circuit, the transient response circuit, the delay response circuit, the normal response circuit and the post-selection switch circuit, a reference pulse with a certain period and a certain duty ratio is generated on the output signal of the basic circuit and is used as the output of the front-stage pulse width modulation, and in the rear-stage pulse width modulation, after an external event input signal is valid, the reference pulse is further modulated: that is, the transient response circuit is used for carrying out transient modulation, the level output of pulse width modulation is immediately controlled when an external event comes, the original level output is recovered after the external event is cancelled, and the PWM state is strictly synchronous with the external event; or delay modulation is performed based on a delay response circuit, which outputs a PWM level to a certain state and maintains it for a certain time (post time) after a time (pre time) delay after an external event comes; or normal modulation is carried out based on the normal response circuit and the basic circuit, after counting and counting the events after the external event comes, the period and the duty ratio of PWM level output are changed at one time or periodically, so that response of three dimensions to the external event can be realized, and digital pulse signals with different time characteristics can be flexibly modulated. The purpose of making multi-dimensional high-efficiency response to an external event and flexibly modulating digital pulse signals with different time characteristics is achieved, and the effect of greatly improving the event response efficiency is achieved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the description of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the description below are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a schematic diagram of an embodiment of a digital PWM circuit;

FIG. 2 is a schematic diagram of a digital PWM circuit according to another embodiment;

FIG. 3 is a schematic diagram of the operation flow of the pre-stage PWM in one embodiment;

FIG. 4 is a schematic diagram of an embodiment of a delay modulation workflow;

FIG. 5 is a schematic diagram of an embodiment of transient modulation workflow;

fig. 6 is a schematic diagram of a normal modulation operation flow in one embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It should be appreciated that reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.

One skilled in the art will appreciate that the embodiments described herein may be combined with other embodiments. The term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element and be integral therewith, or intervening elements may also be present. The terms "one end," "the other end," and the like are used herein for illustrative purposes only.

The following detailed description of embodiments of the invention will be made with reference to the accompanying drawings.

In one embodiment, as shown in fig. 1, the present application provides a digital pulse width modulation circuit 100, which includes a base circuit 11, a transient response circuit 13, a delay response circuit 15, a normal response circuit 17, and a post-selection switch circuit 19. The signal output end of the basic circuit 11 is respectively connected with the signal input ends of the transient response circuit 13 and the delay response circuit 15, and the quantization control output end of the basic circuit 11 is respectively connected with the secondary quantization control input end of the delay response circuit 15 and the control input end of the post-selection switch circuit 19. The signal input end of the normal response circuit 17 is used for receiving an external event input signal, and the signal output end of the normal response circuit 17 is respectively connected with the control input ends of the basic circuit 11 and the delay response circuit 15.

The signal input terminal of the transient response circuit 13 is used for receiving an external event input signal, and the quantization control input terminal of the transient response circuit 13 is connected with the quantization control output terminal of the base circuit 11. The signal input end of the post-selection switch circuit 19 is respectively connected with the signal output ends of the delay response circuit 15 and the transient response circuit 13, and the signal output end of the post-selection switch circuit 19 is used for selectively outputting the modulated pulse signal. The basic circuit 11 is used for generating a preceding-stage pulse width modulation output signal, the transient response circuit 13 is used for performing transient modulation on the preceding-stage pulse width modulation output signal, the delay response circuit 15 is used for performing delay modulation on the preceding-stage pulse width modulation output signal, and the normal response circuit 17 is used for performing normal modulation on the preceding-stage pulse width modulation output signal.

It is understood that, as shown in fig. 1, the digital pwm circuit 100 includes a basic circuit 11, a transient response circuit 13, a delay response circuit 15, a normal response circuit 17, and a post-selection switch circuit 19, it should be noted that fig. 1 may also include schematic diagrams of an operation clock, a reset signal, and the like of the circuits not shown, and those skilled in the art may choose to add these common parts according to the normal operation needs of the circuits.

Specifically, the external event input signal may be denoted as EXT _ EVT, which may be provided by an external device/circuit, characterizing the external event to which the digital pulse width modulation circuit 100 is required to respond. The preceding stage pulse width modulation is based on the basic circuit 11 generating a reference pulse with a certain period and duty cycle on its output signal. The transient response circuit 13 is a response circuit that immediately controls the level output of the PWM when an external event comes, and restores the original level output after the external event is cancelled, during which the PWM state is strictly synchronized with the external event. The delay response circuit 15 is a response circuit that outputs the PWM level to a certain state after a delay of a certain period of time (also referred to as a lead time) elapses after the external event comes, and maintains the state for a certain period of time (also referred to as a lead time), and the delay time may be preset by software according to the delay response requirements of different external events.

The normal state response circuit 17 is a response circuit that counts and counts external events after the external events come, and changes the period and duty ratio of the PWM level output at once or periodically. The post-selection switch circuit 19 is a switch circuit for selectively outputting the finally modulated pulse signal. The transient response circuit 13, the delay response circuit 15 and the normal response circuit 17 can respectively realize three different post-stage pulse width modulation outputs, so that three-dimensional responses to external events can be made, and digital pulse signals with different time characteristics can be flexibly and efficiently modulated. The purpose of the post-stage pulse width modulation is to further modulate the reference pulse output by the pre-stage pulse width modulation after the external event input signal EXT _ EVT is asserted, thereby forming a pulse signal after transient modulation, delay modulation or normal modulation.

The digital pwm circuit 100, through the design of the modulation circuit architecture of the basic circuit 11, the transient response circuit 13, the delay response circuit 15, the normal response circuit 17, and the post-selection switch circuit 19, generates a reference pulse with a certain period and duty ratio on the output signal of the basic circuit 11, as the output of the preceding-stage pwm, and in the following-stage pwm, after the external event input signal is asserted, further modulates the reference pulse: that is, the transient response circuit 13 performs transient modulation, and immediately controls the level output of pulse width modulation when an external event comes, and restores the original level output after the external event is cancelled, and the PWM state is strictly synchronized with the external event; or delay modulation is performed based on the delay response circuit 15, which outputs the PWM level to a certain state and maintains it for a certain period of time (post-time) after a time (pre-time) delay after the external event comes; or normal modulation is performed based on the normal response circuit 17 and the basic circuit 11, and after counting and counting the events after the external event comes, the period and duty ratio of the PWM level output are changed at one time or periodically, so that response of three dimensions to the external event can be realized, and digital pulse signals with different time characteristics can be flexibly modulated. The purpose of making multidimensional high-efficiency response to an external event and flexibly modulating digital pulse signals with different time characteristics is achieved, and the effect of greatly improving the event response efficiency is achieved.

In one embodiment, as shown in FIG. 2, the base circuit 11 includes a time counter TCTR, a time period register TPRD, a first comparison register CMPA, a second comparison register CMPB, a comparator CMP, quantization control registers EQC1-3, and an event quantizer EQ. The time counter TCTR is connected to the comparator CMP and the event quantizer EQ, respectively. The time period register TPRD, the first comparison register CMPA and the second comparison register CMPB are respectively connected to the comparator CMP. The comparator CMP is connected to an event quantizer EQ. The event quantizer EQ is connected to the normal response circuit 17, the transient response circuit 13, and the delay response circuit 15, respectively. The quantization control register EQC is connected to the event quantizer EQ, the transient response circuit 13, the delay response circuit 15, and the post-selection switch circuit 19, respectively.

The time counter TCTR is used to periodically count and output a direction signal to the event quantizer EQ, and the comparator CMP is used to compare the value of the time counter TCTR with 0, the value of the time period register TPRD, the value of the first comparison register CMPA and the value of the second comparison register CMPB, respectively, and generate a corresponding control signal when the comparison results in equal values. The quantization control register EQC is used to control the event quantizer EQ to output a pre-level pwm output signal according to a first quantization rule.

It will be appreciated that the base circuit 11 may be part of a circuit oriented for various types of multi-bit (e.g., without limitation, 16-bit, 32-bit, or 64-bit) PWM, which may be used to implement a preceding stage pulse width modulation function of similar principles. For convenience of explanation and understanding, the following description will be given by taking 32 bits as an example.

The base circuit 11 includes a time counter TCTR [31 ], a time period register TPRD [ 31. Preceding stage pulse width modulation can be accomplished through above-mentioned basic circuit 11 high-efficiently, and circuit structure is brief and the reliability is high.

Specifically, after the circuit initialization is completed, the time counter TCTR starts counting up from 0, and each system clock (SYSCLK) cycle is increased by 1; when the count value of the time counter TCTR is equal to the value TPRD preset by software in the time period register TPRD, the time counter TCTR starts counting down from the value TPRD, and each SYSCLK clock period is decreased by 1; when the time counter TCTR counts down to 0, the time counter TCTR starts to count up from 0; and circulating in sequence. The corresponding direction signal Dir is active during the up-counting of the time counter TCTR (which may be indicated by a high level 1, for example), and is inactive during the down-counting of the time counter TCTR (which may be indicated by a low level 0, for example).

The values of the first comparison register CMPA and the second comparison register CMPB may be preset by software, and the values thereof range from 0 to TPRD, and are used for comparison with the value of the time counter TCTR in the event quantizer EQ. The comparator CMP is configured to compare the value of the time counter TCTR with 0, the value of the time period register TPRD, and the values of the first comparison register CMPA and the second comparison register CMPB, respectively, to determine whether the values are equal to each other, and generate corresponding control signals if the values of the time counter TCTR are equal to 0, the value of the time period register TPRD, and the values of the first comparison register CMPA and the second comparison register CMPB, respectively. The event quantizer EQ is configured to change the state of the output signal of the event quantizer EQ when the corresponding control signal is asserted according to the setting of the quantization control field of the quantization control register EQC.

In one embodiment, further, the corresponding control signals include a control signal EQ _ ZERO corresponding to 0, a control signal EQ _ TPRD corresponding to the value of the time period register, a control signal EQ _ CMPA corresponding to the value of the first comparison register, a control signal EQ _ CMPB corresponding to the value of the second comparison register, and a control signal EVT output after being processed by the steady state response circuit 17 corresponding to the external event input signal, and the preceding-stage pulse width modulation output signals include an output signal EQ1 and an output signal EQ2.

The first quantization rule includes:

setting the priority sequence of the control signals as EQ _ ZERO > EQ _ TPRD > EQ _ CMPA > EQ _ CMPB > EVT;

controlling the event quantizer to output an output signal EQ1 by utilizing a first register EQC1 of the quantization control register; when the direction signal is valid, the first four quantization control domains at the upper position in the first register EQC1 are respectively used for sequentially associating the control signals according to the priority order, and when the direction signal is invalid, the four quantization control domains behind the first four quantization control domains are respectively used for sequentially associating the control signals according to the priority order;

controlling the event quantizer to output an output signal EQ2 by using a second register EQC2 of the quantization control register; when the direction signal is valid, the first four quantization control domains at the upper position in the second register EQC2 are respectively used for sequentially associating the control signals according to the priority order, and when the direction signal is invalid, the four quantization control domains behind the first four quantization control domains are respectively used for sequentially associating the control signals according to the priority order;

when the value of the quantization control domain is 0, setting the output signal EQ1 or EQ2 as 1;

when the value of the quantization control domain is 1, setting the output signal EQ1 or EQ2 as 0;

when the value of the quantization control domain is 2, keeping the output signal EQ1 or EQ2 in the original state;

when the value of the quantization control field is 3, bypassing the associated control signal; when bypassed, the state of the output signals EQ1 and EQ2 is determined by the lower priority control signal and the associated quantization control field.

Specifically, when the value of the time counter TCTR is equal to 0, the generated control signal is denoted as EQ _ ZERO. When the value of the time counter TCTR equals the value of the time period register TPRD, the control signal generated is denoted EQ _ TPRD. When the value of the time counter TCTR equals the value of the first comparison register CMPA, the control signal generated is denoted EQ _ CMPA. When the value of the time counter TCTR equals the value of the second comparison register CMPB, the control signal generated is denoted EQ _ CMPB.

The event quantizer EQ is configured to change the states of the output signals EQ1 and EQ2 of the event quantizer EQ to 1 (active high), 0 (inactive low), maintain the original state, or ignore the control signal EVT output by the normal response circuit 17 when the control signal EQ _ ZERO, EQ _ PRD, EQ _ CMPA, EQ _ CMPB, or the control signal EVT output by the normal response circuit 17 is active according to the setting of the 32-bit quantization control registers EQC1[31 ] and EQC2[31 ].

That is, the priority order of the control signals is: EQ _ ZERO > EQ _ TPRD > EQ _ CMPA > EQ _ CMPB > EVT. The first register EQC1[31 ] of the quantization control register is used to control the output signal EQ1, and the second register EQC2[31 ] of the quantization control register is used to control the output signal EQ2. When the direction signal Dir is 1 (active), the first four higher-order quantized control domains, namely, quantized control domains EQC1[31 ], EQC1[29 ], EQC1[27 ], EQC1[25 ], and EQC1[23 [ 22], are associated with the control signals EQ _ ZERO, EQ _ PRD, EQ _ CMPA, EQ _ CMPB, and EVT, respectively. When the direction signal Dir is 0 (inactive), the four quantized control domains following the first four quantized control domains, namely quantized control domains EQC1[21 ], EQC1[19 ], EQC1[17 ], EQC1[15 ] and EQC1[13 ], are respectively associated with the control signals EQ _ ZERO, EQ _ PRD, EQ _ CMPA, EQ _ CMPB and EVT. And the correlation between the domain and the control signal in the second register EQC2[31 ] of the quantization control register is similar to the analogy of the following steps.

Through the quantization control mode, the high-efficiency preceding-stage pulse width modulation effect is realized through finer and more accurate quantization control.

In one embodiment, as shown in fig. 2, the transient response circuit 13 includes a first selector 131, a second selector 132, a first logical and gate 133, and a second logical and gate 134. A signal input end of the first selector 131 is connected to the event quantizer EQ, a signal output end of the first selector 131 is connected to a first input end of the first logical and gate 133, a second input end of the first logical and gate 133 is used for receiving an external event input signal, and an output end of the first logical and gate 133 is connected to a signal input end of the post-selection switch circuit 19. A signal input end of the second selector 132 is connected to the event quantizer EQ, a signal output end of the second selector 132 is connected to a first input end of the second logic and gate 134, a second input end of the second logic and gate 134 is used for receiving an external event input signal, and an output end of the second logic and gate 134 is connected to a signal input end of the post-selection switch circuit 19. Control input terminals of the first selector 131 and the second selector 132 are respectively connected to the quantization control register EQC of the base circuit 15.

It will be appreciated that by using the transient response circuit 13 of the above-described reduced configuration, the transient modulated output can be efficiently and reliably supported. Specifically, the transient response circuit 13 is composed of 2 multi-select-one (for example, but not limited to, three-select-one) selectors and 2 logic and gates, and functions to immediately respond to an external event and allow its output signals RP1 and RP2 to be driven by the output of the selector when the external event input signal EXT _ EVT is active, and to turn off its output signals RP1 and RP2 when the external event input signal EXT _ EVT is inactive. The source of the output signal RP1 may be 0, 1 or the output signal EQ1 of the event quantizer EQ, controlled by the domain EQC3[9 ] of the third register EQC3 of the quantization control register; the source of the output signal RP2 may be 0, 1 or the output signal EQ2 of the event quantizer EQ, controlled by the domain EQC3[ 11.

In one embodiment, as shown in fig. 2, the delay response circuit 15 includes a pre-counter PRECNT, a post-counter POSCNT, and a quadratic quantizer SEQ. The control input of the pre-counter is used to access the external event input signal EXT _ EVT. The control input end of the postposition counter is connected with the control output end of the prepositive counter. The signal input end of the secondary quantizer is respectively connected with the signal output ends of the event quantizer, the pre-counter and the post-counter, the signal output end of the secondary quantizer is connected with the signal input end of the post-selection switch circuit 19, and the control input end of the secondary quantizer is connected with the quantization control register.

The pre-counter is used for starting counting and setting the first output signal to be effective when the external event input signal is converted to be effective, stopping counting when the counting reaches a pre-counting threshold value, setting the second output signal to be effective and carrying out counting zero clearing. The rear counter is used for starting counting when the second output signal is effective, stopping counting when the counting reaches a rear counting threshold value, setting the third output signal to be effective, and performing counting zero clearing. The secondary quantizer is used for performing delay modulation according to a second quantization rule when the output signal of the counter is effective under the control of the quantization control register; the counter output signal includes a first output signal, a second output signal, or a third output signal.

The delay response circuit 15 may employ various counters and quantizers existing in the art, and the implementation of delay modulation may be efficiently and reliably supported by the circuit structure design of the delay response circuit 15. Specifically, for example, the delay response circuit 15 may include a 32-bit pre-counter PRECNT [31 ].

When the external event input signal EXT _ EVT makes a transition of 0 (inactive low) - >1 (active high), the pre-counter PRECNT starts counting from 0, increments by 1 for each SYSCLK clock cycle, and the first output signal Start of the pre-counter PRECNT is active. When the count of the pre-counter PRECNT reaches the set threshold PREVAL, the counting is stopped, the second output signal Stop1 is valid, and meanwhile, the pre-counter PRECNT is cleared.

When a second output signal Stop1 of the pre-set counting process is effective, the post-set counter POSCNT starts to count from 0; and stopping counting when the count of the post counter POSCNT reaches the set threshold POSVAL, enabling a third output signal Stop2 of the post counter POSCNT to be effective, and resetting the post counter POSCNT. The role of the secondary quantizer SEQ is to change the state of the delayed response output signal RP3 of the secondary quantizer SEQ to 1 (high level), 0 (low level), hold the original state or ignore the control signal, and change the state of the delayed response output signal RP4 of the secondary quantizer SEQ to 1 (high level), 0 (low level), hold the original state or ignore the control signal, according to the setting of the third register EQC3[ 31.

In one embodiment, further, the delay modulated output signals include a delay response output signal RP3 and a delay response output signal RP4. The second quantization rule includes:

setting the priority order of the output signals of the counter as a first output signal Start > a second output signal Stop1> a third output signal Stop2;

controlling the secondary quantizer to output a delayed response output signal RP3 or a delayed response output signal RP4 by using a third register EQC3 of the quantization control register; the first three quantization control domains of the upper bit in the third register EQC3 are respectively used for sequentially associating the output signals of the counters according to the priority order, the adjacent three quantization control domains behind the first three quantization control domains are respectively used for sequentially associating the control signals according to the priority order, the first three quantization control domains correspond to the delayed response output signal RP3, and the adjacent three quantization control domains correspond to the delayed response output signal RP4;

when the value of the quantization control field is 0, setting the delay response output signal RP3 or RP4 as 1;

when the value of the quantization control field is 1, setting the delay response output signal RP3 or RP4 to 0;

when the value of the quantization control field is 2, the delay response output signal RP3 or RP4 is kept in the original state;

when the value of the quantization control field is 3, bypassing the associated control signal; the state of the delayed response output signals RP3 and RP4 when bypassed is determined by the lower priority counter output signal and the associated quantization control field.

Specifically, the priority order of the control signals is: start > Stop1> Stop2. The third register EQC3[31 ] of the quantization control register is used to control the delayed response output signal RP3, and the third register EQC3[23 [ 18] is used to control the delayed response output signal RP4. The first three quantization control domains EQC3[31 ], EQC3[29 ], and EQC3[ 26] of the upper bits in the third register EQC3 are associated with the counter output signals Start, stop1, and Stop2, respectively; the adjacent three quantization control domains after the first three are associated with the counter output signals Start, stop1 and Stop2, respectively, EQC3[23 ], EQC3[21 ] and EQC3[19 ].

A quantized control field value of 0, 1, 2, or 3 indicates setting the delayed response output signal RP3 or RP4 to 1, 0, holding it, or bypassing the control signal (i.e., ignoring it), respectively, when the corresponding counter output signal is active. When bypassed, the state of the delayed response output signals RP3 and RP4 is determined by the lower priority counter output signal and its associated quantization control field. By the above-described quadratic quantization control, delay modulation can be realized with high accuracy and high efficiency.

In one embodiment, as shown in fig. 2, normal response circuit 17 includes an event counter EXTCNT having an input terminal for receiving an external event input signal, and a signal output terminal connected to event quantizer EQ of base circuit 11.

It will be appreciated that normal response circuit 17 may include a 16-bit event counter EXTCNT [ 15. The normal response is performed by the event counter EXTCNT together with the above-described basic circuit 11. The initial value of the event counter EXTCNT may be set to 0; the count of the event counter EXTCNT is self-incremented by 1 whenever 0 (low level) >1 (high level) transition of the external event input signal EXT _ EVT occurs; when the count of the event counter EXTCNT reaches its set threshold EVTVAL, the control signal EVT output to the base circuit 11 is asserted, while the event counter EXTCNT is cleared. The base circuit 11 determines to set the outputs EQ1 and EQ2 of the event quantizer EQ to 1, 0, to remain in the original state, or to bypass the control signal (ignore the control signal) according to the aforementioned first quantization rule.

If the external event input signal EXT _ EVT is a periodic signal, the event counter EXTCNT may output a periodic control signal EVT, which may be used to modulate the period and duty cycle of the pulses in the base circuit 11. The external event input signal EXT _ EVT can be efficiently and accurately output in a normal modulation manner based on the event counter EXTCNT, and the circuit structure is simple and the reliability is high.

It should be noted that, the threshold set in each of the above embodiments may be preset by software or set in real time according to the modulation requirement in practical application.

In one embodiment, as shown in fig. 2, the post selection switch circuit 19 includes a first selection switch M1 and a second selection switch M2. A first input terminal of the first selection switch M1 is connected to the first signal output terminal of the transient response circuit 13, a second input terminal of the first selection switch M1 is connected to the first signal output terminal of the delay response circuit 15, and an output terminal of the first selection switch M1 is used for selecting the first output signal of the transient response circuit 13 or the first output signal of the delay response circuit 15 to be output as the modulated pulse signal.

A first input terminal of the second selection switch M2 is connected to the second signal output terminal of the transient response circuit 13, a second input terminal of the second selection switch M2 is connected to the second signal output terminal of the delay response circuit 15, and an output terminal of the second selection switch M2 is used for selecting the second output signal of the transient response circuit 13 or the second output signal of the delay response circuit 15 to be output as the modulated pulse signal. The control input ends of the first selection switch M1 and the second selection switch M2 are respectively connected with the quantization control register.

Specifically, in the post-selection switch circuit 19, the first selection switch M1 is controlled by the quantization control field EQC3[0] of the quantization control register, and functions to generate the modulated output pulse signal PWMA from either the first output signal RP1 of the transient response circuit 13 or the first output signal RP3 of the delay response circuit 15. The second selection switch M2 is controlled by the quantization control field EQC3[1] of the quantization control register and functions to generate a modulated output pulse signal PWMB from either the second output signal RP2 of the transient response circuit 13 or the second output signal RP4 of the delay response circuit 15.

By using the post-selection switch circuit 19 with the above structure, high-efficiency pulse signal selection output can be realized, and the circuit complexity is further reduced.

In one embodiment, there is also provided a digital pulse width modulation method comprising the steps of:

according to the value of the quantization control register, when the corresponding control signal is valid or the control signal output by the normal state response circuit 17 is valid, outputting a preceding stage pulse width modulation output signal according to a first quantization rule;

It is to be understood that, regarding the circuit structures in the embodiments of the method, the same process can be understood with reference to the corresponding circuit structures in the embodiments of the digital pwm circuit 100, and the description thereof and the following description will not be repeated. The working process of the digital pulse width modulation method can be divided into two stages: pre-stage pulse width modulation and post-stage pulse width modulation. The function of the preceding-stage pulse width modulation is to generate a reference pulse with a certain period and duty ratio on the output signals EQ1 and EQ2 of the event quantizer based on the basic circuit 11; the purpose of the post-stage pulse width modulation is to further modulate the reference pulse after the external event input signal EXT _ EVT is asserted, to form a pulse signal after transient modulation, delay modulation or normal modulation, respectively, according to the response requirement to the external event.

Specifically, as shown in fig. 3, the working process of the preceding-stage pulse width modulation includes 4 steps: initialization, counting, comparison, and quantization. Step 1, initializing a circuit: resetting a time counter TCTR; a time period register TPRD, a first comparison register CMPA, a second comparison register CMPB and a quantization control register EQC1-2 are set.

Step 2, counting: after the initialization is finished, the time counter TCTR starts to count up from 0, and the clock period of each system is increased by 1; when the count value of the time counter TCTR is equal to the value of the time period register TPRD, counting down from the value of the time period register TPRD, and subtracting 1 from each system clock period; and counting up from 0 after the count value of the time counter TCTR is equal to 0, and sequentially circulating. The direction signal Dir is 1 (active high) during the up-counting of the time counter TCTR, and is 0 (inactive low) during the down-counting.

Step 3, comparison: and comparing the value of the time counter TCTR with the values of 0, TPRD, CMPA and CMPB respectively in real time, judging whether the values are equal, and if so, generating corresponding control signals EQ _ ZERO, EQ _ TPRD, EQ _ CMPA or EQ _ CMPB.

Step 4, quantification: according to the settings of the first and second registers EQC1 and EQC2 in the quantization control register, when the control signal EQ _ ZERO, EQ _ PRD, EQ _ CMPA or EQ _ CMPB output in step 3 is active or the control signal EVT output by the normal response circuit 17 is active, the states of the output signals EQ1 and EQ2 are changed to 1 (high level), 0 (low level), and the original states are maintained or ignored.

In the digital pulse width modulation method, the basic circuit 11 generates a reference pulse having a certain period and a certain duty ratio on the output signal thereof, and the reference pulse is further modulated after the external event input signal is enabled in the post-stage pulse width modulation as the output of the pre-stage pulse width modulation: that is, the transient response circuit 13 performs transient modulation, and immediately controls the level output of pulse width modulation when an external event comes, and restores the original level output after the external event is cancelled, and the PWM state is strictly synchronized with the external event; or delay modulation is performed based on the delay response circuit 15, which outputs the PWM level to a certain state and maintains it for a certain period of time (post-time) after a time (pre-time) delay after the external event comes; or normal modulation is performed based on the normal response circuit 17 and the basic circuit 11, and after counting and counting the events after the external event comes, the period and duty ratio of the PWM level output are changed at one time or periodically, so that response of three dimensions to the external event can be realized, and digital pulse signals with different time characteristics can be flexibly modulated. The purpose of making multidimensional high-efficiency response to an external event and flexibly modulating digital pulse signals with different time characteristics is achieved, and the effect of greatly improving the event response efficiency is achieved.

In one embodiment, the corresponding control signals include a control signal EQ _ ZERO corresponding to 0, a control signal EQ _ TPRD corresponding to the value of the time period register, a control signal EQ _ CMPA corresponding to the value of the first comparison register, a control signal EQ _ CMPB corresponding to the value of the second comparison register, and a control signal EVT processed and output by the steady state response circuit 17 corresponding to the external event input signal, and the previous stage pulse width modulation output signals include an output signal EQ1 and an output signal EQ2. The first quantization rule includes:

controlling an event quantizer to output an output signal EQ1 by utilizing a first register EQC1 of a quantization control register; when the direction signal is valid, the first four quantization control domains of the first register EQC1, which are higher than the first four quantization control domains, are respectively used for sequentially associating the control signals according to the priority order, and when the direction signal is invalid, the four quantization control domains behind the first four quantization control domains are respectively used for sequentially associating the control signals according to the priority order;

when the value of the quantization control field is 3, bypassing the associated control signal; when bypassed, the state of the output signals EQ1 and EQ2 is determined by the lower priority control signals and the associated quantization control fields.

In one embodiment, a process of delaying modulation, comprises:

initializing the delay response circuit 15; initializing the counter, wherein the initialization comprises setting a threshold value of a pre-counter and a threshold value of a post-counter, setting a third register EQC3 of a quantization control register, and clearing the pre-counter and the post-counter;

carrying out pre-counting; the pre-counting comprises that after an external event input signal is converted into effective, a pre-counter starts counting from 0 and a first output signal Start is effective, when the value of the pre-counter reaches a threshold value, counting is stopped and cleared, and a second output signal Stop1 is effective;

carrying out post counting; the post-counting comprises that after the second output signal Stop1 is effective, the post-counter starts counting from 0, when the value of the post-counter reaches a threshold value, counting is stopped and cleared, and meanwhile, the third output signal Stop2 is effective;

carrying out secondary quantization processing according to a second quantization rule; the second quantization rule includes:

setting the priority order of the output signals of the counter to be Start > Stop1> Stop2;

when the value of the quantization control domain is 0, setting the delay response output signal RP3 or RP4 as 1;

when the value of the quantization control domain is 2, the delay response output signal RP3 or RP4 is kept in the original state;

when the value of the quantization control field is 3, bypassing the associated control signal; when bypassing, the state of the delayed response output signals RP3 and RP4 is determined by the counter output signal with lower priority and the associated quantization control field;

and respectively controlling a selection switch M1 in a post selection switch circuit 19 to select a delay response output signal RP3 to generate a pulse signal after delay modulation and controlling a selection switch M2 to select a delay response output signal RP4 to generate a pulse signal after modulation by utilizing domains EQC3[0] and EQC3[1] in a third register EQC3 of the quantization control register.

Specifically, the delay modulation is based on the fact that the delay response circuit 15 processes the preceding stage pulse width modulation output signals EQ1 and EQ2 after a certain delay when the external event input signal EXT _ EVT makes a 0 (low level) >1 (high level) transition, and holds the processing result for a certain time. As shown in fig. 4, the workflow includes 5 steps: initialization, pre-counting, post-counting, secondary quantization and post-stage gating.

Step 1 initialization: setting a pre-counter threshold PREVAL and a post-counter threshold POSVAL, setting a quantization control register field EQC3[31 ], EQC3[23 ], EQC3[1], EQC3[0], and clearing a pre-counter PRECNT and a post-counter POSCNT.

Step 2, pre-counting: after the external event input signal EXT _ EVT makes a 0 (low) - >1 (high) transition, the pre-counter PRECNT starts counting from 0, and the output signal Start is active; when the PRECNT value reaches the threshold PREVAL, the counting is stopped and cleared, and the output signal Stop1 is valid.

Step 3, post counting: when the output signal Stop1 of the pre-counting in the step 2 is effective, the post-counter POSCNT starts to count from 0; and stopping counting and clearing when the counting reaches a threshold POSVAL, and enabling an output signal Stop2.

Step 4, secondary quantization: according to the settings of the register fields EQC3[31 ] and EQC3[23 ], when the output signal Start, stop1 or Stop2 of the step 2 pre-count, step 3 post-count is active, the states of the output signals RP3 and RP4 are changed to 1 (high level), 0 (low level) to remain in the original state or the control signal is ignored. The specific quantization rule is as shown in the aforementioned second quantization rule.

In one embodiment, a process of transient modulation includes:

initializing a quantization control register; initialization includes setting quantization control register fields EQC3[9 ], EQC3[11 ], EQC3[0], and EQC3[1];

during the period that the external event input signal is active, controlling the level of the transient response output signal RP1 to be driven by 0, 1 or the output signal EQ1 and controlling the level of the transient response output signal RP2 to be driven by 0, 1 or the output signal EQ2 according to domains EQC3[ 8] and EQC3[11 ], respectively;

and respectively controlling a selection switch M1 in a post selection switch circuit 19 to select a transient response output signal RP1 to generate a transient modulated pulse signal and controlling a selection switch M2 to select a transient response output signal RP2 to generate a transient modulated pulse signal by using domains EQC3[0] and EQC3[1].

Specifically, the transient response circuit 13 immediately processes the preceding-stage pulse width modulation output signals EQ1 and EQ2 when the external event input signal EXT _ EVT is active, and stops processing immediately after the external event input signal EXT _ EVT is deactivated. As shown in fig. 5, the workflow includes 3 steps: initialization, level control and post-stage gating.

Step 1 initialization: set quantization control register fields EQC3[9 ], EQC3[11 ], EQC3[0] and EQC3[1].

Step 2, level control: during the period when the external event input signal EXT _ EVT is active, the domains EQC3[9 ] and EQC3[11 ] control whether the level of the output signal RP1 is driven by 0 or 1 or the output signal EQ1, and whether the level of the output signal RP2 is driven by 0 or 1 or the output signal EQ2, respectively.

And step 3, later stage gating: the domains EQC3[0] and EQC3[1] control the selection switches M1, M2 in the post-selection switch circuit 19, respectively, selecting RP1 to generate the modulated output pulse signal PWMA, and RP2 to generate the modulated output pulse signal PWMB, respectively.

In one embodiment, the process of normal state modulation comprises:

initializing an event threshold and clearing an event counter;

the method comprises the following steps that an event counter is automatically increased by 1 every time an external event input signal is converted into an effective state, the event counter is cleared when the count reaches an event threshold value, and meanwhile, an output signal EVT is set to be effective and the quantization operation in preceding-stage pulse width modulation is triggered;

when the output signal EVT is enabled, a preceding-stage pulse width modulation output signal is output according to a first quantization rule in accordance with the settings of the quantization control registers EQC1 and EQC 2.

Specifically, based on the normal response circuit 17 and the basic circuit 11, when the external event input signal EXT _ EVT makes a 0 (low level) >1 (high level) transition, the number of events is counted and quantization in step 4 in the preceding stage pulse width modulation process is triggered, and the cycle and the duty ratio of the output pulse signals EQ1 and EQ2 are changed at one time or periodically. As shown in fig. 6, the workflow includes several steps: initialization, event statistics and quantification.

Step 1 initialization: an event threshold EVTVAL is set, and an event counter EVTCNT is cleared.

Step 2, event statistics: the counter EXTCNT is self-incremented by 1 each time a transition of 0 (low level) >1 (high level) occurs in the external event input signal EXT _ EVT, cleared when the counter EXTCNT reaches the threshold EVTVAL, and the output signal EVT is active, triggering step 4 quantization in the preceding stage pulse width modulation.

Step 3, quantification: when the control signal EVT is active, the states of the output signals EQ1 and EQ2 are changed according to the settings of the quantization control registers EQC1 and EQC2, with the same quantization rule as step 4 quantization in the preceding stage of pulse width modulation.

It should be noted that the characteristic description in the embodiments of the method may refer to the corresponding explanation in the embodiments of the digital pwm circuit 100.

It should be understood that, although the steps in the flowcharts of fig. 3 to 6 are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps of fig. 3-6 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performing the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features. The above examples only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for those skilled in the art, various changes and modifications can be made without departing from the spirit of the present application, and all of them fall within the scope of the present application. Therefore, the protection scope of the present patent should be subject to the appended claims.

Claims

1. A digital pulse width modulation circuit is characterized by comprising a basic circuit, a transient response circuit, a delay response circuit, a normal response circuit and a post selection switch circuit;

the signal output end of the basic circuit is respectively connected with the signal input ends of the transient response circuit and the delay response circuit, the quantization control output end of the basic circuit is respectively connected with the secondary quantization control input end of the delay response circuit and the selection control input end of the post selection switch circuit, the signal input end of the normal response circuit is used for receiving an external event input signal, and the signal output end of the normal response circuit is respectively connected with the control input ends of the basic circuit and the delay response circuit;

the signal input end of the transient response circuit is used for receiving the external event input signal, the quantization control input end of the transient response circuit is connected with the quantization control output end of the basic circuit, the signal input end of the post selection switch circuit is respectively connected with the signal output ends of the delay response circuit and the transient response circuit, and the signal output end of the post selection switch circuit is used for selectively outputting the modulated pulse signal;

2. The digital pulse width modulation circuit according to claim 1, wherein the base circuit comprises a time counter, a time period register, a first compare register, a second compare register, a comparator, a quantization control register, and an event quantizer;

the time counter is respectively connected with the comparator and the event quantizer, the time period register, the first comparison register and the second comparison register are respectively connected with the comparator, the comparator is connected with the event quantizer, the event quantizer is respectively connected with the normal response circuit, the transient response circuit and the delay response circuit, and the quantization control register is respectively connected with the event quantizer, the delay response circuit, the transient response circuit and the post-selection switch circuit;

the time counter is used for periodically counting and outputting a direction signal to the event quantizer, and the comparator is used for comparing the value of the time counter with 0, the value of the time period register, the value of the first comparison register and the value of the second comparison register respectively and generating corresponding control signals when the values are compared to be equal;

the quantization control register is used for controlling the event quantizer to output the preceding-stage pulse width modulation output signal according to a first quantization rule.

3. The digital pwm circuit according to claim 2, wherein the corresponding control signals include a control signal EQ _ ZERO corresponding to 0, a control signal EQ _ TPRD corresponding to the value of the time period register, a control signal EQ _ CMPA corresponding to the value of the first comparison register, a control signal EQ _ CMPB corresponding to the value of the second comparison register, and a control signal EVT corresponding to the external event input signal and output after being processed by the normal response circuit, and the previous-stage pwm output signal includes an output signal EQ1 and an output signal EQ2;

the first quantization rule includes:

setting the priority order of the control signals as EQ _ ZERO > EQ _ TPRD > EQ _ CMPA > EQ _ CMPB > EVT;

controlling the event quantizer to output the output signal EQ1 by using a first register EQC1 of the quantization control register; when the direction signal is valid, the first four quantization control fields of the first register EQC1 that are higher than the first four quantization control fields are respectively used for sequentially associating with the control signals according to the priority order, and when the direction signal is invalid, the four quantization control fields after the first four quantization control fields are respectively used for sequentially associating with the control signals according to the priority order;

controlling the event quantizer to output the output signal EQ2 by using a second register EQC2 of the quantization control register; when the direction signal is valid, the first four quantization control fields of the upper bits in the second register EQC2 are respectively used for sequentially associating each control signal according to the priority order, and when the direction signal is invalid, the four quantization control fields following the first four quantization control fields are respectively used for sequentially associating each control signal according to the priority order;

when the value of the quantization control domain is 0, setting the output signal EQ1 or EQ2 to 1;

when the value of the quantization control domain is 1, setting the output signal EQ1 or EQ2 to 0;

when the value of the quantization control domain is 2, keeping the output signal EQ1 or EQ2 in an original state;

4. The digital pulse width modulation circuit according to claim 2 or 3, wherein the transient response circuit comprises a first selector, a second selector, a first logical AND gate, and a second logical AND gate;

the signal input end of the first selector is connected with the event quantizer, the signal output end of the first selector is connected with the first input end of the first logic AND gate, the second input end of the first logic AND gate is used for receiving the external event input signal, and the output end of the first logic AND gate is connected with the signal input end of the post-selection switch circuit;

the signal input end of the second selector is connected with the event quantizer, the signal output end of the second selector is connected with the first input end of the second logic AND gate, the second input end of the second logic AND gate is used for receiving the external event input signal, and the output end of the second logic AND gate is connected with the signal input end of the post-selection switch circuit;

and the control input ends of the first selector and the second selector are respectively connected with the quantization control register.

5. The digital pulse width modulation circuit according to claim 2 or 3, wherein the delay response circuit comprises a pre-counter, a post-counter, and a quadratic quantizer;

the control input end of the pre-counter is used for accessing the external event input signal, the control input end of the post-counter is connected with the control output end of the pre-counter, the signal input end of the secondary quantizer is respectively connected with the event quantizer, the pre-counter and the signal output end of the post-counter, the signal output end of the secondary quantizer is connected with the signal input end of the post-selection switch circuit, and the control input end of the secondary quantizer is connected with the quantization control register;

the pre-counter is used for starting counting and setting a first output signal to be effective when the external event input signal is converted to be effective, stopping counting when the counting reaches a pre-counting threshold value, setting a second output signal to be effective and carrying out counting zero clearing;

the postposition counter is used for starting counting when the second output signal is effective, stopping counting when the counting reaches a postposition counting threshold, setting a third output signal to be effective and carrying out counting zero clearing;

the secondary quantizer is used for performing delay modulation according to a second quantization rule when the output signal of the counter is effective under the control of the quantization control register; the counter output signal comprises the first output signal, the second output signal, or the third output signal.

6. The digital pulse width modulation circuit of claim 5, wherein the delay modulated output signals comprise a delay response output signal RP3 and a delay response output signal RP4;

the second quantization rule includes:

controlling the secondary quantizer to output the delayed response output signal RP3 or the delayed response output signal RP4 with a third register EQC3 of the quantization control register; the first three quantization control domains of the higher order in the third register EQC3 are respectively configured to sequentially associate the counter output signals according to the priority order, the adjacent three quantization control domains after the first three quantization control domains are respectively configured to sequentially associate the control signals according to the priority order, the first three quantization control domains correspond to the delay response output signal RP3, and the adjacent three quantization control domains correspond to the delay response output signal RP4;

when the value of the quantization control field is 0, setting the delay response output signal RP3 or RP4 to 1;

when the value of the quantization control field is 2, keeping the delay response output signal RP3 or RP4 in the original state;

when the value of the quantization control field is 3, bypassing the associated control signal; the state of the delayed response output signals RP3 and RP4, when bypassed, is determined by the lower priority counter output signal and the associated quantization control field.

7. The digital pwm circuit according to claim 2 or 3, wherein the normal response circuit comprises an event counter, the event counter input terminal is configured to receive the external event input signal, and the event counter signal output terminal is connected to the event quantizer.

8. The digital pulse width modulation circuit according to claim 2 or 3, wherein the post-selection switch circuit includes a first selection switch and a second selection switch;

a first input end of the first selection switch is connected with a first signal output end of the transient response circuit, a second input end of the first selection switch is connected with a first signal output end of the delay response circuit, and an output end of the first selection switch is used for selecting a first output signal of the transient response circuit or a first output signal of the delay response circuit to be output as the modulated pulse signal;

a first input end of the second selection switch is connected with a second signal output end of the transient response circuit, a second input end of the second selection switch is connected with a second signal output end of the delay response circuit, and an output end of the second selection switch is used for selecting a second output signal of the transient response circuit or a second output signal of the delay response circuit to be output as the modulated pulse signal;

and the control input ends of the first selection switch and the second selection switch are respectively connected with the quantization control register.

9. A digital pulse width modulation method, comprising the steps of:

initializing a circuit for performing preceding-stage pulse width modulation; the initialization comprises resetting a time counter, and setting values of a time period register, a first comparison register, a second comparison register and a quantization control register;

comparing the value of the time counter with 0, the value of the time period register, the value of the first comparison register and the value of the second comparison register in real time respectively, judging whether the values are equal, and if so, generating a corresponding control signal;

according to the value of the quantization control register, when the corresponding control signal is effective or the control signal output by the normal state response circuit is effective, outputting a preceding stage pulse width modulation output signal according to a first quantization rule;

according to the value of the quantization control register, performing post-stage modulation on the pre-stage pulse width modulation output signal, and outputting a pulse signal after the post-stage pulse width modulation; the post-modulation comprises transient modulation, delay modulation or normal modulation.

10. The digital pulse width modulation method according to claim 9, wherein the corresponding control signals include a control signal EQ _ ZERO corresponding to 0, a control signal EQ _ TPRD corresponding to the value of the time period register, a control signal EQ _ CMPA corresponding to the value of the first comparison register, a control signal EQ _ CMPB corresponding to the value of the second comparison register, and a control signal EVT output after being processed by a normal state response circuit corresponding to an external event input signal, and the previous-stage pulse width modulation output signal includes an output signal EQ1 and an output signal EQ2;

the first quantization rule includes:

controlling an event quantizer to output the output signal EQ1 by utilizing a first register EQC1 of the quantization control register; when the direction signal is valid, the first four quantization control fields of the first register EQC1 at the high level are respectively used for sequentially associating each control signal according to the priority order, and when the direction signal is invalid, the four quantization control fields following the first four quantization control fields are respectively used for sequentially associating each control signal according to the priority order;

controlling the event quantizer to output the output signal EQ2 by using a second register EQC2 of the quantization control register; when the direction signal is valid, the first four quantization control fields of the upper bit in the second register EQC2 are respectively used for sequentially associating with the control signals according to the priority order, and when the direction signal is invalid, the four quantization control fields after the first four quantization control fields are respectively used for sequentially associating with the control signals according to the priority order;

11. The method according to claim 9, wherein the delaying the modulating process comprises:

initializing the delay response circuit; the initialization comprises setting a threshold value of a pre-counter and a threshold value of a post-counter, setting a third register EQC3 of a quantization control register, and clearing the pre-counter and the post-counter;

carrying out pre-counting; the pre-counting comprises that after an external event input signal is converted into valid, a pre-counter starts counting from 0 and a first output signal Start is valid, when the value of the pre-counter reaches a threshold value, counting is stopped and cleared, and a second output signal Stop1 is valid;

carrying out post counting; the post counting comprises that after the second output signal Stop1 is effective, the post counter starts counting from 0, when the value of the post counter reaches a threshold value, the counting is stopped and cleared, and meanwhile, the third output signal Stop2 is effective;

controlling the secondary quantizer to output a delayed response output signal RP3 or a delayed response output signal RP4 by using a third register EQC3 of the quantization control register; the first three quantization control domains of the higher order in the third register EQC3 are respectively configured to sequentially associate the counter output signals according to the priority order, the adjacent three quantization control domains after the first three quantization control domains are respectively configured to sequentially associate the control signals according to the priority order, the first three quantization control domains correspond to the delayed response output signal RP3, and the adjacent three quantization control domains correspond to the delayed response output signal RP4;

when the value of the quantization control domain is 2, keeping the delay response output signal RP3 or RP4 in the original state;

when the value of the quantization control field is 3, bypassing the associated control signal; when bypassed, the state of the delayed response output signals RP3 and RP4 is determined by the lower priority counter output signal and the associated quantization control field;

and respectively controlling a selection switch M1 in a post selection switch circuit to select the delay response output signal RP3 to generate a pulse signal after delay modulation and controlling a selection switch M2 to select the delay response output signal RP4 to generate a pulse signal after modulation by utilizing domains EQC3[0] and EQC3[1] in a third register EQC3 of the quantization control register.

12. The digital pulse width modulation method according to any one of claims 9 to 11, wherein the transient modulation process comprises:

initializing a quantization control register; the initialization includes setting quantization control register fields EQC3[9 ], EQC3[11 ], EQC3[0], and EQC3[1];

and respectively controlling a selection switch M1 in a post selection switch circuit to select the transient response output signal RP1 to generate a pulse signal after transient modulation and a selection switch M2 to select the transient response output signal RP2 to generate a pulse signal after transient modulation by utilizing domains EQC3[0] and EQC3[1].

13. The digital pulse width modulation method according to any one of claims 9 to 11, wherein the normal modulation process comprises:

initializing an event threshold and clearing an event counter;

the event counter is automatically increased by 1 every time when an external event input signal is converted into effective, the event counter is cleared when the count reaches the event threshold value, and meanwhile, an output signal EVT is set to be effective and the quantization operation in the preceding-stage pulse width modulation is triggered;

and when the output signal EVT is effective, outputting a previous-stage pulse width modulation output signal according to the first quantization rule according to the setting of the quantization control registers EQC1 and EQC 2.