CN114397953B - Reset filter circuit design implementation method in integrated circuit MCU design - Google Patents
Reset filter circuit design implementation method in integrated circuit MCU design Download PDFInfo
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- CN114397953B CN114397953B CN202111596112.4A CN202111596112A CN114397953B CN 114397953 B CN114397953 B CN 114397953B CN 202111596112 A CN202111596112 A CN 202111596112A CN 114397953 B CN114397953 B CN 114397953B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
Abstract
The invention relates to a method for realizing a reset filter circuit design in an integrated circuit MCU design, which is used for carrying out filter processing on an externally input reset signal through the reset filter circuit, realizing smooth release and debouncing of the externally input reset signal, avoiding burrs generated by jitter of the reset signal to the greatest extent, meeting the requirement of the circuit in the integrated circuit MCU design on the stability of the reset signal, and avoiding the situation of abnormal reset caused by insufficient jitter or reset time of the reset signal.
Description
Technical Field
The invention belongs to the field of embedded microcontrollers, and provides a reset filter circuit design implementation method in an integrated circuit MCU design.
Background
With the development of the integrated circuit field, the embedded micro-controller with high performance is widely applied in the fields of industrial control, automobile electronics and the like, and the requirements on the processing capacity of the embedded micro-controller are higher. Meanwhile, the application fields of the embedded microcontroller are mostly portable equipment, consumer electronics and field control equipment, the time sequence requirements of the embedded microcontroller are very strict, the acquisition of external input signals must be accurate and stable, and the embedded microcontroller has strong fault tolerance. Therefore, in order to meet the application requirements of the embedded microcontroller, it is necessary to try to improve the fault tolerance of the microcontroller to external input signals in the MCU design process, so as to avoid the occurrence of failure situations as much as possible.
Disclosure of Invention
The invention aims to design a reset filter circuit in the design of an integrated circuit MCU so as to improve the stability of an external input key signal-reset signal. The method for realizing the reset filter circuit design in the MCU design is utilized to carry out filter processing on the externally input reset signal, realize smooth release and debouncing of the externally input reset signal, avoid burrs generated by the jitter of the reset signal to the greatest extent, meet the requirement of a circuit in the MCU design on the stability of the reset signal and avoid the situation of abnormal reset caused by the jitter or the insufficient reset time of the reset signal.
The technical scheme adopted by the invention for achieving the purpose is as follows: a reset filter circuit in an integrated circuit MCU design, comprising: the first-stage filter circuit, the second-stage filter circuit, the reset signal debouncing circuit and the reset output circuit are connected in sequence;
the first stage filter circuit is used for realizing the detection of the low to high of an external reset input signal so as to ensure that the length of the reset low level of the external input is at least kept for more than 4 clock cycles;
the second-stage filter circuit is used for detecting the low-to-high output signal of the first-stage filter circuit so as to ensure that the length of the low level of the output signal of the first-stage filter circuit changes into the high level after lasting for 4 clock cycles;
the reset signal debouncing circuit is used for counting according to the width of the output signal of the second-stage filter circuit, and the designated width is regarded as an effective reset signal;
and the reset output circuit is used for outputting a reset signal to control the MCU to reset according to the output signal of the reset signal debouncing circuit.
The first stage filter circuit comprises a first register, a second register, a third register, a fourth register and an OR gate;
the first register, the second register, the third register and the fourth register are sequentially connected;
the input end of the first register is used for accessing an externally input reset signal rst_n;
the input ends of the first register, the second register, the third register and the fourth register are respectively connected with four input ends of the OR gate, clock input ends of the first register, the second register, the third register and the fourth register are all used for accessing the clock signal clk, and reset ends of the first register, the second register, the third register and the fourth register are all used for accessing the external reset signal rst_n;
the output end of the fourth register is connected with the fifth input end of the OR gate;
the output end of the OR gate is used as the output end of the first stage filter circuit.
The second-stage filter circuit comprises a fifth register, a sixth register, a seventh register, an eighth register and an AND gate;
the input end of the fifth register is connected with the output end of the first-stage filter circuit;
the input ends of the sixth register, the seventh register and the eighth register are respectively connected with three input ends of an AND gate, clock input ends of the fifth register, the sixth register, the seventh register and the eighth register are all used for accessing a clock signal clk, and reset ends of the fifth register, the sixth register, the seventh register and the eighth register are all used for accessing an external reset signal rst_n;
the output end of the eighth register is connected with the fourth input end of the AND gate;
the output end of the AND gate is used as the output end of the second-stage filter circuit.
The reset signal debounce circuit comprises a counter;
the counter reset end is connected with the output end of the second-stage filter circuit, the clock input end of the counter is used for accessing the clock signal clk, and the output end of the counter is connected with the reset output circuit.
The reset output circuit includes a ninth register;
the input end of the ninth register is connected with the output end of the counter, the clock input end of the ninth register is used for accessing the clock signal clk, and the output end of the ninth register is used for controlling the resetting of the MCU system.
A reset filter circuit design implementation method in an integrated circuit MCU design comprises the following steps:
the first-stage filter circuit detects the low-to-high of an external reset input signal to ensure that the length of the reset low level of the external input is at least kept for more than 4 clock cycles;
the second-stage filter circuit detects the low-to-high output signal of the first-stage filter circuit to ensure that the low-level length of the output signal of the first-stage filter circuit changes into high level after lasting for 4 clock cycles;
the reset signal debouncing circuit counts according to the width of the output signal of the second-stage filter circuit, and the specified width is reached to be regarded as an effective reset signal;
and the reset output circuit is used for outputting a reset signal to control the MCU to reset according to the output signal of the reset signal debouncing circuit.
The first stage filter circuit detects the low to high of an external reset input signal to ensure that the length of the reset low level of the external input is at least maintained for more than 4 clock cycles, and the method comprises the following steps:
the first register, the second register, the third register and the fourth register acquire a reset value 0 through a power-on reset end, the clock input ends of the first register, the second register, the third register and the fourth register are connected with a clock signal clk, the first register, the second register, the third register and the fourth register step by step, and the change condition of an external reset signal rst_n is detected;
the low-to-high detection of the external reset signal rst_n is realized by performing or processing on the external input reset signal rst_n and the four-stage register output signal through an OR gate, so that the length of the external input reset low level is ensured to be at least kept for more than 4 clock cycles.
The second stage filter circuit detects the low to high output signal of the first stage filter circuit to ensure that the low level length of the output signal of the first stage filter circuit changes to high level after lasting 4 clock cycles, and the method comprises the following steps:
the fifth register, the sixth register, the seventh register and the eighth register acquire a reset value 0 through power-on reset, clock input ends of the fifth register, the sixth register, the seventh register and the eighth register are connected with clock signals, and the fifth register, the sixth register, the seventh register and the eighth register stage by stage register, so that the output change condition of the first-stage filter circuit is detected;
the AND gate carries out AND logic processing on the four-stage register signals of the output signals of the second-stage filter circuit, so that the detection of the low-to-high output signals of the first-stage filter circuit is realized, and the length of the low level of the output signals of the first-stage filter circuit is ensured to be changed into the high level after lasting for 4 clock cycles.
The reset signal debouncing circuit counts according to the width of the output signal of the reset signal debouncing circuit, reaches a specified width and is regarded as an effective reset signal, and the method comprises the following steps:
the reset end of the reset signal debouncer circuit is connected with the output of the second-stage filter circuit, and when the output of the second-stage circuit is high, the reset signal debouncer circuit keeps 0 unchanged; a step of
When the output of the second-stage filter circuit is low, the reset signal debouncing circuit starts counting according to the clock signal, stops counting after the counting reaches the upper limit, and outputs a count full signal to the reset output circuit; if the count is not full, the output of the second-stage filter circuit is changed from low to high, which means that the reset holding time is relatively short, and the MCU system does not reset when the reset signal is ignored.
The reset output circuit outputs a reset signal to control the MCU to reset according to the output signal of the reset signal debouncing circuit, and the reset output circuit comprises the following steps:
when the output of the second-stage circuit is high, the reset output circuit keeps 0 unchanged;
when the output of the second-stage filter circuit is low, the output end of the reset output circuit is the output of the reset signal debouncing circuit.
The invention has the following beneficial effects and advantages:
1. the invention adopts a time sequence logic circuit to design sampling and debouncing processing of asynchronous reset signals, replaces a common same phase reset signal sampling circuit by reverse logic sampling and counting processing, realizes fault tolerance design on the reset signals, avoids interference to an MCU system due to reset jitter, and realizes higher stability.
2. The invention adopts twice four-stage register logic to realize the sampling of the reset signal input from the outside, ensures the duration time and better controls the working stability of the debouncing circuit.
3. The invention converts the asynchronous reset signal into the synchronous reset signal for release, avoids the circuit logic confusion caused by triggering the circuit again in a short period of sampling the signal under the clock triggering of the clock starting circuit, and further enhances the stability of the MCU system.
Drawings
FIG. 1 is a diagram of a reset filter circuit in an MCU design of the present invention.
Fig. 2 is a schematic diagram of an application example of the present invention in an embedded microcontroller system.
Detailed Description
The present invention will be described in detail with reference to the accompanying drawings.
The invention relates to a method for realizing a reset filter circuit design in an integrated circuit MCU (micro controller) design, which is used for carrying out filter processing on an externally input reset signal through the reset filter circuit, realizing smooth release and debouncing of the externally input reset signal, avoiding burrs generated by the jitter of the reset signal to the greatest extent, meeting the requirement of a circuit in the integrated circuit MCU design on the stability of the reset signal, and avoiding the situation of abnormal reset caused by the jitter or insufficient reset time of the reset signal.
As shown in fig. 1, a reset filter circuit in an integrated circuit MCU design includes: the device comprises a first-stage filter circuit, a second-stage filter circuit, a reset signal de-dithering circuit and a reset output circuit;
the first stage filter circuit includes four registers and a five-input OR gate logic. The four registers acquire a reset value 0 through power-on reset (por_n), the clock input end of each register is used for accessing a clock signal (clk), the four registers register step by step, and the change condition of an external reset input (rst_n) is detected;
the five-input OR gate is used for carrying out or processing on the externally input reset signal and the four-stage register signal, so that the detection of the low-to-high state of the externally input reset signal is realized, and the length of the externally input reset low level is ensured to be at least kept for more than 4 clock cycles.
The second stage filter circuit includes four registers and a four-input AND gate logic. The four registers acquire a reset value 0 through power-on reset, the clock input end of each register is used for accessing a clock signal, the four registers register step by step, and the output change condition of the first-stage filter circuit is detected;
and performing AND logic processing on the four-stage register signals of the output signals of the first-stage filter circuit through four-input AND gates, detecting the low-to-high output signals of the first-stage filter circuit, and ensuring that the low-level length of the output signals of the first-stage filter circuit changes into high level after lasting for 4 clock cycles.
The reset signal debouncing circuit comprises a counter; the width of the counter is determined according to design requirements, the reset end of the counter is connected with the output of the second-stage filter circuit, when the output of the second-stage filter circuit is high (not in a reset state), the counter is kept unchanged, when the output of the second-stage filter circuit is low (an external reset signal is effective), the counter starts counting according to a clock signal, stops counting after the counter reaches an upper limit, outputs a count full signal to the next-stage filter circuit, and if the output of the second-stage filter circuit is not full, the output of the second-stage filter circuit is changed from low to high, the reset keeping time is short, the reset signal is ignored, and the MCU system cannot reset.
The reset output circuit comprises a register; the register reset end is connected with the output of the second-stage filter circuit, when the output of the second-stage circuit is high (not in a reset state), the reset output register keeps 0 unchanged, and when the output of the second-stage circuit is low (an external reset signal is valid), the output end of the reset output circuit is the output (count full flag) of the reset signal debouncing circuit.
The reset filter circuit in the design of the integrated circuit MCU is completed, and after sampling and debouncing the externally input reset signal, the processed reset signal (filter_reset_n) is output
) The high level is active.
As shown in fig. 2, the external reset signal sampled and processed by the invention is connected to the reset control logic of the MCU, and after the MCU reset control logic samples various reset source signals, if a reset source is generated, the MCU reset logic outputs the reset of the MCU system, so as to reset the whole MCU system to return to the initial state.
Claims (8)
1. A reset filter circuit in an integrated circuit MCU design, comprising: the first-stage filter circuit, the second-stage filter circuit, the reset signal debouncing circuit and the reset output circuit are connected in sequence;
the first stage filter circuit is used for realizing the detection of the low to high of an external reset input signal so as to ensure that the length of the reset low level of the external input is at least kept for more than 4 clock cycles;
the second-stage filter circuit is used for detecting the low-to-high output signal of the first-stage filter circuit so as to ensure that the length of the low level of the output signal of the first-stage filter circuit changes into the high level after lasting for 4 clock cycles;
the reset signal debouncing circuit is used for counting according to the width of the output signal of the second-stage filter circuit, and the designated width is regarded as an effective reset signal;
the reset output circuit is used for outputting a reset signal to control the MCU to reset according to the output signal of the reset signal debouncing circuit;
the reset signal debounce circuit comprises a counter;
the counter reset end is connected with the output end of the second-stage filter circuit, the clock input end of the counter is used for accessing the clock signal clk, and the output end of the counter is connected with the reset output circuit.
2. The reset filter circuit in an integrated circuit MCU design of claim 1, wherein the first stage filter circuit comprises a first register, a second register, a third register, a fourth register, and an or gate;
the first register, the second register, the third register and the fourth register are sequentially connected;
the input end of the first register is used for accessing an externally input reset signal rst_n;
the input ends of the first register, the second register, the third register and the fourth register are respectively connected with four input ends of the OR gate, clock input ends of the first register, the second register, the third register and the fourth register are all used for accessing the clock signal clk, and reset ends of the first register, the second register, the third register and the fourth register are all used for accessing the external reset signal rst_n;
the output end of the fourth register is connected with the fifth input end of the OR gate;
the output end of the OR gate is used as the output end of the first stage filter circuit.
3. A reset filter circuit in an integrated circuit MCU design according to claim 1, wherein said second stage filter circuit comprises fifth, sixth, seventh, eighth and an and gate;
the input end of the fifth register is connected with the output end of the first-stage filter circuit;
the input ends of the sixth register, the seventh register and the eighth register are respectively connected with three input ends of an AND gate, clock input ends of the fifth register, the sixth register, the seventh register and the eighth register are all used for accessing a clock signal clk, and reset ends of the fifth register, the sixth register, the seventh register and the eighth register are all used for accessing an external reset signal rst_n;
the output end of the eighth register is connected with the fourth input end of the AND gate;
the output end of the AND gate is used as the output end of the second-stage filter circuit.
4. A reset filter circuit in an integrated circuit MCU design according to claim 1, wherein said reset output circuit comprises a ninth register;
the input end of the ninth register is connected with the output end of the counter, the clock input end of the ninth register is used for accessing the clock signal clk, and the output end of the ninth register is used for controlling the resetting of the MCU system.
5. The implementation method of the reset filter circuit design in the design of the integrated circuit MCU is characterized by comprising the following steps of:
the first-stage filter circuit detects the low-to-high of an external reset input signal to ensure that the length of the reset low level of the external input is at least kept for more than 4 clock cycles;
the second-stage filter circuit detects the low-to-high output signal of the first-stage filter circuit to ensure that the low-level length of the output signal of the first-stage filter circuit changes into high level after lasting for 4 clock cycles;
the reset signal debouncing circuit counts according to the width of the output signal of the second-stage filter circuit, and the specified width is reached to be regarded as an effective reset signal;
the reset output circuit is used for outputting a reset signal to control the MCU to reset according to the output signal of the reset signal debouncing circuit;
the reset signal debouncing circuit counts according to the width of the output signal of the reset signal debouncing circuit, reaches a specified width and is regarded as an effective reset signal, and the method comprises the following steps:
the reset end of the reset signal debouncer circuit is connected with the output of the second-stage filter circuit, and when the output of the second-stage circuit is high, the reset signal debouncer circuit keeps 0 unchanged;
when the output of the second-stage filter circuit is low, the reset signal debouncing circuit starts counting according to the clock signal, stops counting after the counting reaches the upper limit, and outputs a count full signal to the reset output circuit; if the count is not full, the output of the second-stage filter circuit is changed from low to high, which means that the reset holding time is relatively short, and the MCU system does not reset when the reset signal is ignored.
6. The method for implementing a reset filter circuit in an integrated circuit MCU design according to claim 5, wherein said first stage filter circuit performs a low-to-high detection of an external reset input signal to ensure that the length of the reset low level of the external input is maintained for at least 4 clock cycles or more, comprising the steps of:
the first register, the second register, the third register and the fourth register acquire a reset value 0 through a power-on reset end, the clock input ends of the first register, the second register, the third register and the fourth register are connected with a clock signal clk, the first register, the second register, the third register and the fourth register step by step, and the change condition of an external reset signal rst_n is detected;
the low-to-high detection of the external reset signal rst_n is realized by performing or processing on the external input reset signal rst_n and the four-stage register output signal through an OR gate, so that the length of the external input reset low level is ensured to be at least kept for more than 4 clock cycles.
7. The method for implementing a reset filter circuit in an integrated circuit MCU design according to claim 5, wherein the second stage filter circuit detects low to high output signals of the first stage filter circuit to ensure that the low level length of the output signals of the first stage filter circuit goes high after 4 clock cycles, comprising the steps of:
the fifth register, the sixth register, the seventh register and the eighth register acquire a reset value 0 through power-on reset, clock input ends of the fifth register, the sixth register, the seventh register and the eighth register are connected with clock signals, and the fifth register, the sixth register, the seventh register and the eighth register stage by stage register, so that the output change condition of the first-stage filter circuit is detected;
the AND gate carries out AND logic processing on the four-stage register signals of the output signals of the second-stage filter circuit, so that the detection of the low-to-high output signals of the first-stage filter circuit is realized, and the length of the low level of the output signals of the first-stage filter circuit is ensured to be changed into the high level after lasting for 4 clock cycles.
8. The method for implementing a reset filter circuit in an integrated circuit MCU design according to claim 5, wherein the reset output circuit outputs a reset signal to control the MCU reset according to the output signal of the reset signal debouncing circuit, comprising the steps of:
when the output of the second-stage circuit is high, the reset output circuit keeps 0 unchanged;
when the output of the second-stage filter circuit is low, the output end of the reset output circuit is the output of the reset signal debouncing circuit.
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