CN114397953A - Reset filter circuit design realization method in integrated circuit MCU design - Google Patents
Reset filter circuit design realization method in integrated circuit MCU design Download PDFInfo
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Abstract
The invention relates to a method for realizing the design of a reset filter circuit in the design of an integrated circuit MCU (microprogrammed control Unit), which carries out filtering processing on an externally input reset signal through the reset filter circuit, realizes the smooth release and the jitter removal of the externally input reset signal, avoids burrs generated by the jitter of the reset signal to the maximum extent, meets the requirement of a circuit in the design of the integrated circuit MCU on the stability of the reset signal, and avoids the condition of abnormal reset caused by the jitter or insufficient reset time of the reset signal.
Description
Technical Field
The invention belongs to the field of embedded microcontrollers, and provides a method for realizing the design of a reset filter circuit in the design of an integrated circuit MCU.
Background
With the development of the field of integrated circuits, the application of high-performance embedded microcontrollers in the fields of industrial control, automotive electronics and the like is more and more extensive, and the requirements on the processing capacity of the embedded microcontrollers are also more and more high. Meanwhile, the application fields of the embedded microcontroller are mostly portable equipment, consumer electronics and field control equipment, the requirements on the time sequence of the embedded microcontroller are very strict, the acquisition of external input signals must be accurate and stable, and the embedded microcontroller has strong fault-tolerant capability. Therefore, in order to meet the application requirements of the embedded microcontroller, the fault tolerance of the microcontroller to external input signals must be improved in the MCU design process, and the occurrence of failure conditions must be avoided as much as possible.
Disclosure of Invention
The invention aims to design a reset filter circuit in an integrated circuit MCU design to improve the stability of an external input key signal, namely a reset signal. The method for realizing the reset filter circuit design in the MCU design is utilized to carry out filter processing on the reset signal input from the outside, realize smooth release and debouncing of the external reset input signal, avoid the burr generated by the shake of the reset signal to the maximum extent, meet the requirement of the circuit in the integrated circuit MCU design on the stability of the reset signal, and avoid the condition of abnormal reset caused by the shake or insufficient reset time of the reset signal.
The technical scheme adopted by the invention for realizing the purpose is as follows: a reset filter circuit in an integrated circuit MCU design, comprising: the first-stage filter circuit, the second-stage filter circuit, the reset signal debouncing circuit and the reset output circuit are connected in sequence;
the first-stage filter circuit is used for realizing low-to-high detection of an external reset input signal so as to ensure that the length of a reset low level input externally keeps more than 4 clock cycles;
the second-stage filter circuit is used for detecting the low level of the output signal of the first-stage filter circuit to high level after the low level of the output signal of the first-stage filter circuit lasts for 4 clock cycles;
the reset signal debouncing circuit is used for counting according to the width of the output signal of the second-stage filter circuit, and the reset signal debouncing circuit is used for considering the reset signal as an effective reset signal when the output signal reaches the specified width;
and the reset output circuit is used for outputting a reset signal to control the MCU to reset according to the output signal of the reset signal debounce circuit.
The first-stage filter circuit comprises a first register, a second register, a third register, a fourth register and an OR gate;
the first register, the second register, the third register and the fourth register are connected in sequence;
the input end of the first register is used for accessing an externally input reset signal rst _ n;
the input ends of a first register, a second register, a third register and a fourth register are respectively connected with four input ends of an OR gate, the clock input ends of the first register, the second register, the third register and the fourth register are all used for accessing a clock signal clk, and the reset ends of the first register, the second register, the third register and the fourth register are all used for accessing an external reset signal rst _ n;
the output end of the fourth register is connected with the fifth input end of the OR gate;
and the output end of the OR gate is used as the output end of the first-stage filter circuit.
The second-stage filter circuit comprises a fifth register, a sixth register, a seventh register, an eighth register and an AND gate;
the fifth register, the sixth register, the seventh register and the eighth register are sequentially connected, and the input end of the fifth register is connected with the output end of the first-stage filter circuit;
the input ends of a sixth register, a seventh register and an eighth register are respectively connected with three input ends of an AND gate, the clock input ends of the fifth register, the sixth register, the seventh register and the eighth register are all used for accessing a clock signal clk, and the reset ends of the fifth register, the sixth register, the seventh register and the eighth register are all used for accessing an external reset signal rst _ n;
the output end of the eighth register is connected with the fourth input end of the AND gate;
and the output end of the AND gate is used as the output end of the second stage filter circuit.
The reset signal debouncing circuit comprises a counter;
the reset end of the counter is connected with the output end of the second-stage filter circuit, the clock input end of the counter is used for accessing a clock signal clk, and the output end of the counter is connected with the reset output circuit.
The reset output circuit comprises a ninth register;
the input end of the ninth register is connected with the output end of the counter, the clock input end of the ninth register is used for accessing a clock signal clk, and the output end of the ninth register is used for controlling the MCU system to reset.
A method for realizing the design of a reset filter circuit in the design of an integrated circuit MCU comprises the following steps:
the first stage filter circuit detects the low to high of an external reset input signal to ensure that the length of a reset low level input externally keeps more than 4 clock cycles;
the second-stage filter circuit detects the low-to-high of the output signal of the first-stage filter circuit so as to ensure that the low level of the output signal of the first-stage filter circuit is changed into high level after lasting for 4 clock cycles;
the reset signal debouncing circuit counts according to the width of the output signal of the second-stage filter circuit, and the reset signal debouncing circuit regards the reset signal as an effective reset signal when the specified width is reached;
and the reset output circuit is used for outputting a reset signal to control the MCU to reset according to the output signal of the reset signal debounce circuit.
The first stage filter circuit detects the low to high of an external reset input signal to ensure that the length of the reset low level of the external input is kept more than 4 clock cycles at least, and the method comprises the following steps:
the first register, the second register, the third register and the fourth register obtain a reset value 0 through a power-on reset terminal, clock input ends of the first register, the second register, the third register and the fourth register are accessed with a clock signal clk, the first register, the second register, the third register and the fourth register step by step, and the change condition of an external reset signal rst _ n is detected;
the externally input reset signal rst _ n and the four-stage register output signal are subjected to OR processing through an OR gate, so that the low-to-high detection of the externally input reset signal rst _ n is realized, and the length of the externally input reset low level is guaranteed to be kept more than 4 clock cycles at least.
The second-stage filter circuit detects the low-to-high state of the output signal of the first-stage filter circuit to ensure that the low level of the output signal of the first-stage filter circuit is changed into high level after lasting for 4 clock cycles, and the method comprises the following steps:
the reset value 0 is obtained by the fifth register, the sixth register, the seventh register and the eighth register through power-on reset, clock signals are accessed to the clock input ends of the fifth register, the sixth register, the seventh register and the eighth register, the fifth register, the sixth register, the seventh register and the eighth register are registered step by step, and the output change condition of the first-stage filter circuit is detected;
and logic processing is carried out on the four-level register signal of the output signal of the second-level filter circuit through an AND gate, so that the low-to-high detection of the output signal of the first-level filter circuit is realized, and the low level of the output signal of the first-level filter circuit is ensured to be changed into the high level after continuing for 4 clock cycles.
The reset signal debouncing circuit counts according to the width of the output signal of the reset signal debouncing circuit, and determines that the output signal reaches the specified width as an effective reset signal, and the method comprises the following steps:
the reset end of the reset signal debouncing circuit is connected to the output of the second-stage filter circuit, and when the output of the second-stage filter circuit is high, the reset signal debouncing circuit keeps 0 unchanged; a
When the output of the second-stage filter circuit is low, the reset signal debounce circuit starts counting according to the clock signal, stops counting after the counting reaches an upper limit, and outputs a counting full signal to the reset output circuit; if the count is not full, the output of the second stage filter circuit changes from low to high, which means that the reset holding time is short, and the MCU system cannot reset by neglecting the reset signal.
The reset output circuit outputs a reset signal to control the MCU to reset according to the output signal of the reset signal debouncing circuit, and the method comprises the following steps:
when the output of the second-stage circuit is high, the reset output circuit keeps 0 unchanged;
when the output of the second stage filter circuit is low, the output end of the reset output circuit is the output of the reset signal debouncing circuit.
The invention has the following beneficial effects and advantages:
1. the invention adopts a sequential logic circuit to design sampling and de-jitter processing of asynchronous reset signals, replaces a common same-phase reset signal sampling circuit by reverse logic sampling and counting processing, realizes fault-tolerant design of the reset signals, avoids the interference of reset jitter on an MCU system, and realizes higher stability.
2. The invention adopts twice four-stage register logic to realize sampling of the reset signal input from the outside, ensures the duration and better controls the working stability of the debouncing circuit.
3. The invention converts the asynchronous reset signal into the synchronous reset signal for releasing, thereby avoiding the circuit logic disorder caused by triggering the circuit again in a short period of sampling the signal by the clock starting circuit under the clock triggering, and further enhancing the stability of the MCU system.
Drawings
FIG. 1 is a diagram of a reset filter circuit in an MCU design of the present invention.
FIG. 2 is a schematic diagram of an exemplary application of the present invention in an embedded microcontroller system.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings.
The invention relates to a method for realizing the design of a reset filter circuit in the design of an integrated circuit MCU (microcontroller). the reset filter circuit is used for filtering an externally input reset signal to realize the smooth release and jitter removal of the externally input reset signal, so that burrs generated by the jitter of the reset signal are avoided to the greatest extent, the requirement of a circuit in the design of the integrated circuit MCU on the stability of the reset signal is met, and the condition of abnormal reset caused by the jitter or insufficient reset time of the reset signal is avoided.
As shown in fig. 1, a reset filter circuit in an integrated circuit MCU design includes: the device comprises a first-stage filter circuit, a second-stage filter circuit, a reset signal debouncing circuit and a reset output circuit;
the first stage of the filter circuit includes four registers and a five input or gate logic. The four registers obtain a reset value of 0 through power-on reset (por _ n), the clock input ends of the registers are used for accessing a clock signal (clk), and the four registers register step by step to detect the change condition of an external reset input (rst _ n);
the reset signal input from the outside and the four-stage register signal are subjected to OR processing through a five-input OR gate, so that the low-to-high detection of the external reset input signal is realized, and the length of the reset low level input from the outside is ensured to be kept at least more than 4 clock cycles.
The second stage filter circuit includes four registers and a four input and gate logic. The four registers obtain a reset value of 0 through power-on reset, the clock input ends of the registers are used for accessing clock signals, and the four registers register step by step to detect the output change condition of the first-stage filter circuit;
and the four-level register signal of the output signal of the first-level filter circuit is subjected to AND logic processing through a four-input AND gate, so that the low-to-high detection of the output signal of the first-level filter circuit is realized, and the low level of the output signal of the first-level filter circuit is ensured to be changed into the high level after lasting for 4 clock cycles.
The reset signal debouncing circuit comprises a counter; the width of the counter is determined according to design requirements, the reset end of the counter is connected with the output of the second-stage filter circuit, the counter keeps 0 unchanged when the output of the second-stage circuit is high (not in a reset state), the counter starts counting according to a clock signal when the output of the second-stage circuit is low (an external reset signal is effective), counting is stopped after the upper limit is reached, a counting full signal is output to the next-stage circuit, if the output of the second-stage filter circuit is changed from low to high when the counting is not full, the reset keeping time is short, the reset signal is ignored, and the MCU system cannot reset.
The reset output circuit comprises a register; the reset end of the register is connected with the output of the second stage filter circuit, the reset output register keeps 0 when the output of the second stage circuit is high (not in a reset state), the output of the reset output circuit is low (an external reset signal is effective), and the output end of the reset output circuit is the output of the reset signal debounce circuit (a counting full mark).
Therefore, the reset filter circuit in the integrated circuit MCU design is finished, and after sampling and de-jittering an externally input reset signal, the reset filter _ reset _ n is output
) And high is active.
As shown in fig. 2, the external reset signal sampled and processed by the present invention is connected to the reset control logic of the MCU, and after the MCU reset control logic samples various reset source signals, if a reset source is generated, the MCU reset logic outputs the MCU system reset for resetting the whole MCU system to return to the initial state.
Claims (10)
1. A reset filter circuit in an integrated circuit (MCU) design, comprising: the first-stage filter circuit, the second-stage filter circuit, the reset signal debouncing circuit and the reset output circuit are connected in sequence;
the first-stage filter circuit is used for realizing low-to-high detection of an external reset input signal so as to ensure that the length of a reset low level input externally keeps more than 4 clock cycles;
the second-stage filter circuit is used for detecting the low level of the output signal of the first-stage filter circuit to high level after the low level of the output signal of the first-stage filter circuit lasts for 4 clock cycles;
the reset signal debouncing circuit is used for counting according to the width of the output signal of the second-stage filter circuit, and the reset signal debouncing circuit is used for considering the reset signal as an effective reset signal when the output signal reaches the specified width;
and the reset output circuit is used for outputting a reset signal to control the MCU to reset according to the output signal of the reset signal debounce circuit.
2. The reset filter circuit in an integrated circuit (MCU) design according to claim 1, wherein the first stage filter circuit comprises a first register, a second register, a third register, a fourth register and an OR gate;
the first register, the second register, the third register and the fourth register are connected in sequence;
the input end of the first register is used for accessing an externally input reset signal rst _ n;
the input ends of a first register, a second register, a third register and a fourth register are respectively connected with four input ends of an OR gate, the clock input ends of the first register, the second register, the third register and the fourth register are all used for accessing a clock signal clk, and the reset ends of the first register, the second register, the third register and the fourth register are all used for accessing an external reset signal rst _ n;
the output end of the fourth register is connected with the fifth input end of the OR gate;
and the output end of the OR gate is used as the output end of the first-stage filter circuit.
3. The reset filter circuit in an integrated circuit MCU design of claim 1, wherein the second stage filter circuit comprises a fifth register, a sixth register, a seventh register, an eighth register and an AND gate;
the fifth register, the sixth register, the seventh register and the eighth register are sequentially connected, and the input end of the fifth register is connected with the output end of the first-stage filter circuit;
the input ends of a sixth register, a seventh register and an eighth register are respectively connected with three input ends of an AND gate, the clock input ends of the fifth register, the sixth register, the seventh register and the eighth register are all used for accessing a clock signal clk, and the reset ends of the fifth register, the sixth register, the seventh register and the eighth register are all used for accessing an external reset signal rst _ n;
the output end of the eighth register is connected with the fourth input end of the AND gate;
and the output end of the AND gate is used as the output end of the second stage filter circuit.
4. A reset filter circuit in an integrated circuit MCU design according to claim 1, wherein the reset signal debounce circuit comprises a counter;
the reset end of the counter is connected with the output end of the second-stage filter circuit, the clock input end of the counter is used for accessing a clock signal clk, and the output end of the counter is connected with the reset output circuit.
5. The integrated circuit MCU of claim 1, wherein the reset output circuit comprises a ninth register;
the input end of the ninth register is connected with the output end of the counter, the clock input end of the ninth register is used for accessing a clock signal clk, and the output end of the ninth register is used for controlling the MCU system to reset.
6. A method for realizing the design of a reset filter circuit in the design of an integrated circuit MCU is characterized by comprising the following steps:
the first stage filter circuit detects the low to high of an external reset input signal to ensure that the length of a reset low level input externally keeps more than 4 clock cycles;
the second-stage filter circuit detects the low-to-high of the output signal of the first-stage filter circuit so as to ensure that the low level of the output signal of the first-stage filter circuit is changed into high level after lasting for 4 clock cycles;
the reset signal debouncing circuit counts according to the width of the output signal of the second-stage filter circuit, and the reset signal debouncing circuit regards the reset signal as an effective reset signal when the specified width is reached;
and the reset output circuit is used for outputting a reset signal to control the MCU to reset according to the output signal of the reset signal debounce circuit.
7. The method as claimed in claim 6, wherein the first stage filter circuit performs low-to-high detection of the external reset input signal to ensure that the length of the reset low level of the external input is at least kept above 4 clock cycles, comprising the following steps:
the first register, the second register, the third register and the fourth register obtain a reset value 0 through a power-on reset terminal, clock input ends of the first register, the second register, the third register and the fourth register are accessed with a clock signal clk, the first register, the second register, the third register and the fourth register step by step, and the change condition of an external reset signal rst _ n is detected;
the externally input reset signal rst _ n and the four-stage register output signal are subjected to OR processing through an OR gate, so that the low-to-high detection of the externally input reset signal rst _ n is realized, and the length of the externally input reset low level is guaranteed to be kept more than 4 clock cycles at least.
8. The method of claim 6, wherein the second stage filter circuit detects the low-to-high output signal of the first stage filter circuit to ensure that the low level of the output signal of the first stage filter circuit changes to high level after lasting for 4 clock cycles, comprising the steps of:
the reset value 0 is obtained by the fifth register, the sixth register, the seventh register and the eighth register through power-on reset, clock signals are accessed to the clock input ends of the fifth register, the sixth register, the seventh register and the eighth register, the fifth register, the sixth register, the seventh register and the eighth register are registered step by step, and the output change condition of the first-stage filter circuit is detected;
and logic processing is carried out on the four-level register signal of the output signal of the second-level filter circuit through an AND gate, so that the low-to-high detection of the output signal of the first-level filter circuit is realized, and the low level of the output signal of the first-level filter circuit is ensured to be changed into the high level after continuing for 4 clock cycles.
9. The method as claimed in claim 6, wherein the reset signal debouncing circuit counts the number of times the width of the output signal of the reset signal debouncing circuit reaches a predetermined width, and determines that the reset signal is valid, and the method comprises the following steps:
the reset end of the reset signal debouncing circuit is connected to the output of the second-stage filter circuit, and when the output of the second-stage filter circuit is high, the reset signal debouncing circuit keeps 0 unchanged; a
When the output of the second-stage filter circuit is low, the reset signal debounce circuit starts counting according to the clock signal, stops counting after the counting reaches an upper limit, and outputs a counting full signal to the reset output circuit; if the count is not full, the output of the second stage filter circuit changes from low to high, which means that the reset holding time is short, and the MCU system cannot reset by neglecting the reset signal.
10. The method according to claim 6, wherein the reset output circuit outputs a reset signal to control the MCU to reset according to the output signal of the reset signal debouncing circuit, comprising:
when the output of the second-stage circuit is high, the reset output circuit keeps 0 unchanged;
when the output of the second stage filter circuit is low, the output end of the reset output circuit is the output of the reset signal debouncing circuit.
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