CN109164982B - Data processing circuit, data processing method and data storage device - Google Patents
Data processing circuit, data processing method and data storage device Download PDFInfo
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- CN109164982B CN109164982B CN201810965817.0A CN201810965817A CN109164982B CN 109164982 B CN109164982 B CN 109164982B CN 201810965817 A CN201810965817 A CN 201810965817A CN 109164982 B CN109164982 B CN 109164982B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0608—Saving storage space on storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
Abstract
The invention provides a data processing circuit, a data processing method and data storage equipment, and belongs to the technical field of data processing. Wherein, data processing circuit includes: and the detection unit is used for classifying the data to be processed according to the data length of the data to be processed, and the data length of each type of data to be processed is in the same range. By the technical scheme, FPGA logic resources and storage space can be effectively saved.
Description
Technical Field
The present invention relates to the field of data processing technologies, and in particular, to a data processing circuit, a data processing method, and a data storage device.
Background
In the algorithm development process, a large amount of data is often required to be processed. However, the size of data varies widely, and when a storage space of data is opened up in an FPGA (Field-Programmable Gate Array), the size is set according to the occupied amount of the storage space of the maximum data, and all other data open up the same storage space. However, if the value of only a few data is large and the value of other data is small, the storage space is opened up according to the maximum data, which results in waste of storage resources.
Disclosure of Invention
The invention aims to provide a data processing circuit, a data processing method and data storage equipment, which can effectively save FPGA logic resources and storage space.
To solve the above technical problem, embodiments of the present invention provide the following technical solutions:
in one aspect, a data processing circuit is provided, comprising:
and the detection unit is used for classifying the data to be processed according to the data length of the data to be processed, and the data length of each type of data to be processed is in the same range.
Further, the detection unit is specifically configured to divide the data to be processed into M classes, where the data length of each class of data to be processed is (k-1) × n +1 to k × n bits, where M and n are positive integers, and k is a positive integer not greater than M.
Further, the detection unit specifically includes:
the control circuit comprises M control devices, wherein the kth control device is used for detecting (k-1) n +1 to k n bits of data to be processed, judging whether effective data exist in the (k-1) n +1 to k n bits of the data to be processed or not, and outputting an enable signal according to the judgment results of the M control devices;
and the k-th group of multiplexers are used for outputting the data to be processed with the data length of (k-1) × n +1 to k × n bits.
Further, when M is equal to 4 and n is equal to 4, the control circuit specifically includes:
the first OR gate comprises four input ends and respectively receives the 13 th to 16 th data of the data to be processed;
the second OR gate comprises four input ends and respectively receives the 9 th to 12 th data of the data to be processed;
the third OR gate comprises four input ends and respectively receives the 5 th to 8 th data of the data to be processed;
the fourth OR gate comprises four input ends and respectively receives the 1 st to 4 th data of the data to be processed;
the first AND gate comprises two input ends, the first input end receives an inverted signal of the output signal of the first OR gate, and the second input end receives the output signal of the second OR gate;
the first input end of the first AND gate receives the inverted signal of the output signal of the first OR gate, the second input end of the first AND gate receives the inverted signal of the output signal of the first AND gate, and the third input end of the first AND gate receives the output signal of the second OR gate;
the first input end of the first AND gate receives the inverted signal of the output signal of the first OR gate, the second input end of the first AND gate receives the inverted signal of the output signal of the first AND gate, the third input end of the first AND gate receives the inverted signal of the output signal of the second AND gate, and the fourth output end of the first AND gate receives the output signal of the fourth OR gate;
the enabling ends of the first group of multiplexers receive output signals of the first OR gate;
the enabling end of the second group of multiplexers receives the output signal of the first AND gate;
the enabling end of the third group of multiplexers receives the output signal of the third AND gate;
the enabling end of the fourth group of multiplexers receives the output signal of the second AND gate.
An embodiment of the present invention further provides a data storage device, including the data processing circuit described above.
Further, still include:
and the storage unit is used for distributing storage space for the data to be processed according to the classification result of the data to be processed.
Further, the storage unit is specifically configured to allocate a storage space with a length k × n to each piece of data in the kth class of data to be processed.
An embodiment of the present invention further provides a data processing method applied to the data processing circuit, where the data processing method includes:
and classifying the data to be processed according to the data length of the data to be processed, wherein the data length of each type of data to be processed is in the same range.
Further, the method specifically comprises:
dividing the data to be processed into M types, wherein the data length of each type of the data to be processed is (k-1) × n +1 to k × n bits, M and n are positive integers, and k is a positive integer not greater than M.
Further, the method specifically comprises:
detecting data to be processed by using M control devices, wherein (k-1) × n +1 to k × n bits of the data to be processed are detected by using a k-th control device, judging whether effective data exist in the (k-1) × n +1 to k × n bits of the data to be processed, and outputting an enable signal according to the judgment results of the M control devices;
and receiving the data to be processed by utilizing M groups of multiplexers, and outputting the data to be processed with different data lengths according to the received enable signals, wherein the k-th group of multiplexers outputs the data to be processed with the data length of (k-1) × n +1 to k × n bits.
The embodiment of the invention has the following beneficial effects:
in the above scheme, the data processing circuit can classify the data to be processed according to the data length of the data to be processed, and the data length of each type of data to be processed is within the same range, so that storage space can be allocated for the data to be processed according to the classification result of the data to be processed, namely the data length range of the data to be processed, when the data to be processed is stored subsequently, and waste of storage resources can be avoided. When the method is applied to the FPGA, the logic resource and the storage space of the FPGA can be effectively saved, and the calculation speed can be improved to a certain extent on the basis of ensuring the subsequent calculation precision.
Drawings
FIG. 1 is a schematic diagram of a data processing circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a data storage device according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a control circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a first set of multiplexers in accordance with an embodiment of the present invention;
FIG. 5 is a block diagram of a second set of multiplexers in accordance with one embodiment of the present invention;
FIG. 6 is a block diagram of a third set of multiplexers in accordance with an embodiment of the present invention;
FIG. 7 is a block diagram of a fourth set of multiplexers in accordance with an embodiment of the present invention;
FIG. 8 is a diagram illustrating the logic resources required by the prior art to classify data with length not more than 16 bits using a comparator;
fig. 9 is a diagram illustrating logical resources required for classifying data having a length of no more than 16 bits according to an embodiment of the present invention.
Detailed Description
In order to make the technical problems, technical solutions and advantages to be solved by the embodiments of the present invention clearer, the following detailed description will be given with reference to the accompanying drawings and specific embodiments.
The embodiment of the invention aims at the situation that when the storage space of data is opened up in the FPGA design in the prior art, the storage space of the maximum data can be set according to the occupied amount of the storage space, and the same storage space can be opened up for all other data. However, if the values of a few data are large and the values of other data are small, the problem of waste of storage resources is caused by opening up a storage space according to the maximum data.
An embodiment of the present invention provides a data processing circuit, as shown in fig. 1, including:
the detecting unit 11 is configured to classify the data to be processed according to the data length of the data to be processed, where the data length of each type of data to be processed is in the same range.
In this embodiment, the data processing circuit may classify the data to be processed according to the data length of the data to be processed, and the data length of each type of data to be processed is within the same range, so that a storage space may be allocated to the data to be processed according to the classification result of the data to be processed, that is, the data length range of the data to be processed, when the data to be processed is stored subsequently, thereby avoiding the waste of storage resources. When the method is applied to the FPGA, the logic resource and the storage space of the FPGA can be effectively saved, and the calculation speed can be improved to a certain extent on the basis of ensuring the subsequent calculation precision.
Further, the detection unit 11 is specifically configured to divide the data to be processed into M classes, where the data length of each class of data to be processed is (k-1) × n +1 to k × n bits, where M and n are positive integers, and k is a positive integer not greater than M.
Further, the detecting unit 11 specifically includes:
the control circuit comprises M control devices, wherein the kth control device is used for detecting (k-1) n +1 to k n bits of data to be processed, judging whether effective data exist in the (k-1) n +1 to k n bits of the data to be processed or not, and outputting an enable signal according to the judgment results of the M control devices;
and the k-th group of multiplexers are used for outputting the data to be processed with the data length of (k-1) × n +1 to k × n bits.
In the technical scheme of the invention, the values of M and n can be designed according to actual needs and the size of the storage space so as to maximize the utilization rate of storage resources.
Further, when M is equal to 4 and n is equal to 4, the control circuit specifically includes:
the first OR gate comprises four input ends and respectively receives the 13 th to 16 th data of the data to be processed;
the second OR gate comprises four input ends and respectively receives the 9 th to 12 th data of the data to be processed;
the third OR gate comprises four input ends and respectively receives the 5 th to 8 th data of the data to be processed;
the fourth OR gate comprises four input ends and respectively receives the 1 st to 4 th data of the data to be processed;
the first AND gate comprises two input ends, the first input end receives an inverted signal of the output signal of the first OR gate, and the second input end receives the output signal of the second OR gate;
the first input end of the first AND gate receives the inverted signal of the output signal of the first OR gate, the second input end of the first AND gate receives the inverted signal of the output signal of the first AND gate, and the third input end of the first AND gate receives the output signal of the second OR gate;
the first input end of the first AND gate receives the inverted signal of the output signal of the first OR gate, the second input end of the first AND gate receives the inverted signal of the output signal of the first AND gate, the third input end of the first AND gate receives the inverted signal of the output signal of the second AND gate, and the fourth output end of the first AND gate receives the output signal of the fourth OR gate;
the enabling ends of the first group of multiplexers receive output signals of the first OR gate;
the enabling end of the second group of multiplexers receives the output signal of the first AND gate;
the enabling end of the third group of multiplexers receives the output signal of the third AND gate;
the enabling end of the fourth group of multiplexers receives the output signal of the second AND gate.
In the prior art, when the data length of data is judged, the data length is realized by using a comparator, and more logic resources are required to be occupied; in the technical scheme of the invention, the judgment of the data length is realized only by adopting an OR gate, an AND gate, a multiplexer and the like, so that the occupied logic resource can be greatly reduced.
The following describes the technical solution of the present invention in detail with reference to the accompanying drawings and specific embodiments, taking as an example that the data length of the data to be processed does not exceed 16 bits, and M and n are both 4:
as shown in fig. 3, the input terminal of the control circuit is used to input the Data _ in [15..0] to be processed, the output terminal is used to output the enable signal to the four groups of multiplexers D1-D4, the four groups of multiplexers D1-D4 receive the Data _ in [15..0] to be processed, and output the Data with different length ranges according to the enable signal, wherein, D1 outputs the Data with the length of 8-12 bits, D2 outputs the Data with the length of 13-16 bits, D4 outputs the Data with the length of 5-8 bits, and D3 outputs the Data with the length of 1-4 bits.
The control circuit comprises four OR gates: or _ inst1-or _ inst 4; three and gates: and _ inst1-and _ inst 3. Wherein, or _ inst1 has four input ends, respectively receiving the highest four-bit data of the data to be processed; or _ inst2 has four inputs for respectively receiving data of 9 th to 12 th bits of data to be processed; or _ inst3 has four inputs for receiving the 5 th to 8 th data bits of the data to be processed, respectively; or _ inst4 has four inputs for receiving the lowest four bits of data to be processed, respectively. and _ inst1 has two inputs, one of which receives the inverted signal of the output signal of or _ inst1 and the other of which receives the output signal of or _ inst 2; and _ inst2 has three inputs, one of which receives the inverted signal of the output signal of or _ inst1, the other of which receives the inverted signal of the output signal of or _ inst2, and the remaining one of which receives the output signal of or _ inst 3; and _ inst3 has four inputs, one of which receives the inverted signal of the output signal of or _ inst1, another of which receives the inverted signal of the output signal of or _ inst2, yet another of which receives the inverted signal of the output signal of or _ inst3, and the remaining of which receives the output signal of or _ inst 4.
Wherein, the output signal of or _ inst1 is used as the enable signal of D2; the output signal of and _ inst1 is used as the enable signal of D1; the output signal of and _ inst3 is used as the enable signal of D3; the output signal of and _ inst2 is used as the enable signal of D4.
As shown IN FIG. 4, D1 comprises 12 multiplexers having inputs IN1 and IN2, where IN1 inputs the output signal of and _ inst1, IN2 inputs the data to be processed, and when IN1 inputs high level, D1 outputs data, and the output data is data with length of 8-12 bits.
As shown IN fig. 5, D2 includes 16 multiplexers having input terminals IN1 and IN2, where IN1 inputs the output signal of or _ inst1, IN2 inputs the data to be processed, and when IN1 inputs a high level, D2 outputs data, and the output data is data with a length of 13-16 bits.
As shown IN fig. 6, D3 includes 8 multiplexers having inputs IN1 and IN2, where IN1 is input as the output signal of and _ inst3, IN2 is input as the data to be processed, and when IN1 is input with a high level, D3 outputs data, and the output data is data with a length of 1-4 bits.
As shown IN FIG. 7, D4 comprises 4 multiplexers having inputs IN1 and IN2, where IN1 inputs the output signal of and _ inst2, IN2 inputs the data to be processed, and when IN1 inputs high level, D4 outputs data, and the output data is data with length of 5-8 bits.
When the Data processing circuit is working, the Data _ out _16 outputs Data, starting from the most significant bit of Data _ in, specifically, firstly detecting whether the [15,12] bit (namely the most significant four bits) is 0, when the [15,12] bit is not 0 (namely low level), the OR gate or _ inst1 outputs 1 (namely high level), the AND gate and _ inst1, and _ inst2 and the AND _ inst3 do not work; when the [15,12] bit is 0, detecting whether the [11,8] bit (namely, the 9 th bit to the 12 th bit) is 0, if not, the AND gate and _ inst1 works, the and _ inst2 and the and _ inst3 do not work, and Data is output by the Data _ out _ 12; by analogy, the data with different lengths are output by different output ends, and the data classification is completed.
After Data having a length of not more than 16 bits is input to the Data processing circuit of this embodiment, Data having a length of 13 to 16 bits is output from the Data _ out _16, Data having a length of 9 to 12 bits is output from the Data _ out _12, Data having a length of 1 to 4 bits is output from the Data _ out _8, and Data having a length of 5 to 8 bits is output from the Data _ out _ 4.
As shown in fig. 8, when the comparator is used to classify data with a length not exceeding 16 bits, the number of logical resources (Total logical elements) to be used is 55, and as shown in fig. 9, when the data processing circuit of the present embodiment is used to classify data with a length not exceeding 16 bits, the number of logical resources to be used is 41, which can save about 25.45% of the logical resources.
An embodiment of the present invention further provides a data storage device, including the data processing circuit described above.
Further, as shown in fig. 2, the data storage device further includes:
and the storage unit 12 is used for allocating storage space for the data to be processed according to the classification result of the data to be processed.
In this embodiment, the data processing circuit may classify the data to be processed according to the data length of the data to be processed, and the data length of each type of data to be processed is within the same range, so that a storage space may be allocated to the data to be processed according to the classification result of the data to be processed, that is, the data length range of the data to be processed, when the data to be processed is stored subsequently, thereby avoiding the waste of storage resources. When the method is applied to the FPGA, the logic resource and the storage space of the FPGA can be effectively saved, and the calculation speed can be improved to a certain extent on the basis of ensuring the subsequent calculation precision.
Further, the storage unit is specifically configured to allocate a storage space with a length k × n to each piece of data in the kth class of data to be processed.
An embodiment of the present invention further provides a data processing method applied to the data processing circuit, where the data processing method includes:
and classifying the data to be processed according to the data length of the data to be processed, wherein the data length of each type of data to be processed is in the same range.
In this embodiment, the data processing circuit may classify the data to be processed according to the data length of the data to be processed, and the data length of each type of data to be processed is within the same range, so that a storage space may be allocated to the data to be processed according to the classification result of the data to be processed, that is, the data length range of the data to be processed, when the data to be processed is stored subsequently, thereby avoiding the waste of storage resources. When the method is applied to the FPGA, the logic resource and the storage space of the FPGA can be effectively saved, and the calculation speed can be improved to a certain extent on the basis of ensuring the subsequent calculation precision.
Further, the method specifically comprises:
dividing the data to be processed into M types, wherein the data length of each type of the data to be processed is (k-1) × n +1 to k × n bits, M and n are positive integers, and k is a positive integer not greater than M.
Furthermore, the detection unit comprises a control circuit and M groups of multiplexers, the control circuit comprises M control devices, wherein the kth control device is used for detecting (k-1) n +1 to k n bits of the data to be processed, judging whether valid data exist in the (k-1) n +1 to k n bits of the data to be processed, and outputting an enable signal according to the judgment results of the M control devices; and the k-th group of multiplexers are used for outputting the data to be processed with the data length of (k-1) × n +1 to k × n bits. The method specifically comprises the following steps:
detecting data to be processed by using M control devices, wherein (k-1) × n +1 to k × n bits of the data to be processed are detected by using a k-th control device, judging whether effective data exist in the (k-1) × n +1 to k × n bits of the data to be processed, and outputting an enable signal according to the judgment results of the M control devices;
and receiving the data to be processed by utilizing M groups of multiplexers, and outputting the data to be processed with different data lengths according to the received enable signals, wherein the k-th group of multiplexers outputs the data to be processed with the data length of (k-1) × n +1 to k × n bits.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (8)
1. A data processing circuit, comprising:
the detection unit is used for classifying the data to be processed according to the data length of the data to be processed, and the data length of each type of data to be processed is in the same range;
the detection unit is specifically used for dividing the data to be processed into M types, and the data length of each type of the data to be processed is (k-1) × n +1 to k × n bits, wherein M and n are positive integers, and k is a positive integer not greater than M;
the detection unit specifically includes:
the control circuit comprises M control devices, wherein the kth control device is used for detecting (k-1) n +1 to k n bits of data to be processed, judging whether effective data exist in the (k-1) n +1 to k n bits of the data to be processed or not, and outputting an enable signal according to the judgment results of the M control devices;
and the k-th group of multiplexers are used for outputting the data to be processed with the data length of (k-1) × n +1 to k × n bits.
2. The data processing circuit of claim 1, wherein when M equals 4 and n equals 4, the control circuit comprises:
the first OR gate comprises four input ends and respectively receives the 13 th to 16 th data of the data to be processed;
the second OR gate comprises four input ends and respectively receives the 9 th to 12 th data of the data to be processed;
the third OR gate comprises four input ends and respectively receives the 5 th to 8 th data of the data to be processed;
the fourth OR gate comprises four input ends and respectively receives the 1 st to 4 th data of the data to be processed;
the first AND gate comprises two input ends, the first input end receives an inverted signal of the output signal of the first OR gate, and the second input end receives the output signal of the second OR gate;
the first input end of the first AND gate receives the inverted signal of the output signal of the first OR gate, the second input end of the first AND gate receives the inverted signal of the output signal of the first AND gate, and the third input end of the first AND gate receives the output signal of the second OR gate;
the first input end of the first AND gate receives the inverted signal of the output signal of the first OR gate, the second input end of the first AND gate receives the inverted signal of the output signal of the first AND gate, the third input end of the first AND gate receives the inverted signal of the output signal of the second AND gate, and the fourth output end of the first AND gate receives the output signal of the fourth OR gate;
the enabling ends of the first group of multiplexers receive output signals of the first OR gate;
the enabling end of the second group of multiplexers receives the output signal of the first AND gate;
the enabling end of the third group of multiplexers receives the output signal of the third AND gate;
the enabling end of the fourth group of multiplexers receives the output signal of the second AND gate.
3. A data storage device comprising a data processing circuit as claimed in any one of claims 1-2.
4. The data storage device of claim 3, further comprising:
and the storage unit is used for distributing storage space for the data to be processed according to the classification result of the data to be processed.
5. The data storage device of claim 4, wherein the storage unit is specifically configured to allocate a storage space with a length k × n for each data in the kth class of data to be processed.
6. A data processing method applied to a data processing circuit according to any one of claims 1-2, the data processing method comprising:
and classifying the data to be processed according to the data length of the data to be processed, wherein the data length of each type of data to be processed is in the same range.
7. The data processing method according to claim 6, wherein the method specifically comprises:
dividing the data to be processed into M types, wherein the data length of each type of the data to be processed is (k-1) × n +1 to k × n bits, M and n are positive integers, and k is a positive integer not greater than M.
8. The data processing method according to claim 7, wherein the method specifically comprises:
detecting data to be processed by using M control devices, wherein (k-1) × n +1 to k × n bits of the data to be processed are detected by using a k-th control device, judging whether effective data exist in the (k-1) × n +1 to k × n bits of the data to be processed, and outputting an enable signal according to the judgment results of the M control devices;
and receiving the data to be processed by utilizing M groups of multiplexers, and outputting the data to be processed with different data lengths according to the received enable signals, wherein the k-th group of multiplexers outputs the data to be processed with the data length of (k-1) × n +1 to k × n bits.
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| CN102664637A (en) * | 2012-04-12 | 2012-09-12 | 北京中科晶上科技有限公司 | Method and device for confirming leading zero number of binary data |
| CN106406756A (en) * | 2016-09-05 | 2017-02-15 | 华为技术有限公司 | Space allocation method of file system, and apparatuses |
| CN107340992A (en) * | 2017-06-15 | 2017-11-10 | 西安微电子技术研究所 | A kind of fixed-point data screening circuit |
| CN108334541A (en) * | 2017-12-18 | 2018-07-27 | 中兴通讯股份有限公司 | A kind of date storage method, device, equipment and storage medium |
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