CN100464501C - Method and device for removing burrs in signal - Google Patents
Method and device for removing burrs in signal Download PDFInfo
- Publication number
- CN100464501C CN100464501C CNB2006101129157A CN200610112915A CN100464501C CN 100464501 C CN100464501 C CN 100464501C CN B2006101129157 A CNB2006101129157 A CN B2006101129157A CN 200610112915 A CN200610112915 A CN 200610112915A CN 100464501 C CN100464501 C CN 100464501C
- Authority
- CN
- China
- Prior art keywords
- output
- signal
- input
- vout
- latch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims description 15
- 230000000630 rising effect Effects 0.000 description 5
- 230000003750 conditioning effect Effects 0.000 description 4
- 230000001360 synchronised effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000003044 adaptive effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Images
Landscapes
- Manipulation Of Pulses (AREA)
- Logic Circuits (AREA)
Abstract
The invention is designed for removing the spurs from the input signal Vin and getting an output signal Vout. The apparatus comprises N+3 latches and a combinational logic circuit. All said latches receive a clock signal and output it after latching it one clock cycle; wherein N+2 latches are in cascade connection each other; the input of the first latch is the input signal Vin, and the output and input signals Vout of next N-1 latches is taken as the input of said combinational logic circuit; the output of the combinational logic circuit is inputted to a latch; said latch outputs the output signal; when all outputs of the N+1 latches are 1, the output is 1; when all outputs are 0, the output is 0; otherwise the output is the current value of Vout.
Description
Technical field
The present invention relates to a kind of signal processing method and device, relate in particular to the removal method and apparatus of burr in a kind of signal.
Background technology
In circuit shown in Figure 1, the output signal of chip 1 generates input signal through behind the input circuit of output circuit, signal transmssion line and chip 2, and is often jagged on this input signal.
The generation approach of burr probably has following three kinds:
1) output signal itself is just jagged.For example, output signal is not register output, but during combinational logic output, often just jagged in the signal.
The burr that produces when 2) on signal transmssion line, transmitting.For example the radio noise source induces burr signal on transmission line, the signal cross-talk between the signal transmssion line etc.
3) after handling, input circuit also may produce burr.If the rising edge of signal (or trailing edge) slow (as reaching the microsecond level) then near input circuit threshold value thresholding, may produce burr, as shown in Figure 2.
Vht is the high level thresholding among the figure, if i.e. input signal Vin 〉=Vht, output signal Vout=1; Vlt is the low level thresholding, if input signal Vin＜=Vlt, then output signal Vout=0; And if Vht〉Vin〉Vlt, then Vout can not obtain stable numerical value, may also may be 1 for 0.
Signal in the literary composition is digital signal.So-called burr, promptly its width is less than the signal minimum widith of definition.There are 3 such burrs among Fig. 2.
Burr in the signal tends to cause the misoperation of subsequent logic, so the removal of burr has become the common problem that must face of present interface circuit design.The approach and the subsequent conditioning circuit characteristic separately that produce according to burr have a lot of burr removal methods.
At the approach that burr produces, following three kinds of methods of eliminating burr are arranged usually:
1) at approach 1, can require to adopt register output, do not allow combinational logic output;
2) at approach 2, can when system design, require the intensity and the distance of control source of radio-frequency interference, can require crosstalking between the control signal wire;
3), may be required in adding Schmidt comparator on the input circuit at approach 3.
If can not control each approach that burr produces, that just needs special circuit to eliminate burr.According to the requirement difference of subsequent conditioning circuit to input, various burr removing methods are often arranged, for example:
1), so just can only be concerned about that clock is along near burr if input and output have synchronized relation;
2) subsequent conditioning circuit may only be concerned about the rising edge or the trailing edge of signal, so just can remove the burr of rising edge or trailing edge specially;
3) if subsequent conditioning circuit only to the level signal sensitivity of input, so just can adopt the method deburring of voting by a show of hands.
More than the main deficiency of these methods be, be not a general burr removing method, but at certain special circumstances, adaptive surface is narrower.
Summary of the invention
The technical problem to be solved in the present invention is that a kind of method and device thereof of removing burr in the signal will be provided, and has realized the bigger scope of application with less cost.
In order to solve the problems of the technologies described above, the invention provides a kind of method of removing burr in the signal, be used for removing the burr of input signal Vin, obtain output signal Vout, this method may further comprise the steps:
(a) selected clock signal, the burr width that eliminate is less than N clock cycle;
(b) the input signal Vin that needs deburring is carried out the N+2 level and latch, each grade latchs a clock cycle with the output signal of previous stage;
(c) described input signal Vin being latched each grade latch signal and the described output signal Vout that obtain through the 2nd grade to the N+2 level is input in the combinational logic circuit, be 1 if judge described each grade latch signal, described combinational logic circuit output valve is 1 signal Vout_pre, if be 0, described combinational logic circuit output valve is 0 signal Vout_pre, otherwise, the signal Vout_pre that described combinational logic circuit output valve is described output signal Vout currency;
(d) export after the signal Vout_pre that described combinational logic circuit is exported latchs a clock cycle, obtain described output signal Vout.
In a preferred embodiment, described latching by d type flip flop of signal finished.
The present invention provides a kind of device of removing burr in the signal again, is used for removing the burr of input signal Vin, obtains output signal Vout, it is characterized in that, comprises N+3 latch and a combinational logic circuit, wherein:
Described latch all receives a clock signal, export after input signal latched a clock cycle, wherein the 1st to N+2 mutual cascade of latch, the 1st latch be input as input signal Vin, the 2nd to the output of N+2 latch and the output signal Vout input as described combinational logic circuit, the output of this combinational logic circuit is input to N+3 latch again, exports described output signal Vout by this latch;
Described combinational logic circuit is 1 o'clock in described the 2nd output to N+2 latch entirely, is output as 1, as being 0 entirely, is output as 0, is output as the currency of output signal Vout in other cases.
In a preferred embodiment, described latch is a d type flip flop.
In a preferred embodiment, described combinational logic circuit comprises a NOR gate, one with the door, first variable connector and second variable connector, described NOR gate and be the 2nd output to N+2 latch with the input of door, the output of described NOR gate is connected to the control end of first variable connector, described output with door is connected to the control end of second variable connector, two of first variable connector are input as logical zero and output signal Vout, two outputs that are input as the logical one and first variable connector of second variable connector, the control end of first variable connector is 1 o'clock, be output as logical zero, otherwise be output as signal Vout, the control end of second variable connector is 1 o'clock, be output as logical one, otherwise be output as the output of first variable connector.
The present invention adapts to wide, no matter the burr that the sort of approach produces can be removed, the resource that takies is few, and output signal postpones little with respect to input signal.
Description of drawings
Fig. 1 is the schematic diagram of two chip chamber signal transmission.
Fig. 2 is near the schematic diagram that produces burr input circuit threshold value thresholding.
Fig. 3 is an embodiment of the invention manipulated or operated apparatus.
Fig. 4 is a kind of enforcement structure chart of combinational logic circuit among Fig. 3.
Fig. 5 is the oscillogram that embodiment of the invention burr is eliminated.
Embodiment
Shown in Figure 3 is the present embodiment manipulated or operated apparatus.As shown in the figure, comprise 5 d type flip flop D1～D5 and a combinational logic circuit, each d type flip flop is exported after a clock cycle signal latch, and signal point of observation and signal output point are all at the rising edge of clock.
Clk is a synchronised clock, is input to the input end of clock of all triggers.Vin is the input signal of band burr, the input of Vin input trigger D1 (D end), and trigger D1～D4 cascade successively, promptly the output of previous trigger (Q end) is connected to the input of a back trigger.Vin_d1, Vin_d2, Vin_d3 and Vin_d4 are respectively the output signals of trigger D1～D4, Vin_d1 has done one-level to Vin and has latched, Vin_d2 has done one-level to Vin_d1 and has latched, and Vin_d3 has done one-level to Vin_d2 and latched, and Vin_d4 has done one-level to Vin_d3 and latched.Therefore Vin_d1, Vin_d2, Vin_d3 and Vin_d4 are the one-level of Vin to the level Four latch signal.
Vin_d2, Vin_d3, Vin_d4 and Vout are as the input of combinational logic circuit, and the output signal Vout_pre of combinational logic circuit is input to trigger D5 again, and it is output as the output signal Vout that has removed burr.The structure of this combinational logic circuit comprises one three input NOR gate, three inputs and door and two two input mux as shown in Figure 4.Three input NOR gate are output as 1 when three input signal Vin_d2, Vin_d3, Vin_d4 are zero entirely, otherwise are 0; Three inputs and Men Zaisan input signal Vin_d2, Vin_d3, Vin_d4 were output as 1 at 1 o'clock, otherwise were 0.The output of three input NOR gate is as the control signal of first two input mux, and this control end is 1 o'clock, the value of I/O 1, and this value is logical zero, another input 0 of this two input mux is connected to output signal Vout.The output of three inputs and door is as the control signal of second two input mux, and this signal is 1 o'clock, the value of I/O 1, and this value is logical one, another input of this two input mux is connected to the output of first two input mux.
Those skilled in the art can understand, and the implementation of this combinational logic circuit has a variety of, but its function is: at second, third and fourth stage latch signal (being Vin_d2, Vin_d3 and Vin_d4) is 1 o'clock entirely, and output signal Vout_pre is 1; These three grades of latch signals are 0 o'clock entirely, and output signal Vout_pre is zero; Otherwise Vout_pre is the value of Vout, and it is constant promptly to keep the Vout value.
Signal Vout_pre is input to the input of trigger D5, latchs back output signal Vout, simultaneously this signal is input to combinational logic circuit.
As can be seen from Figure 5, the one-level latch signal Vin_d1 that obtains after the first order latchs is synchronized to the Clk clock zone, has removed near the burr of the width of non-rising edge less than a clock cycle simultaneously.Vin_d2 has done one-level again and has latched on the basis of Vin_d1, postponed 1 clock cycle than Vin_d1, to eliminate metastable state.Vin_d3 postpones a clock cycle again than Vin_d2, and Vin_d4 postpones a clock cycle again than Vin_d3.Therefore, less than two clock cycle, after it was synchronous by clock signal, the burr in Vin_d2, Vin_d3 and Vin_d4 signal can not be " 0 " or " 1 " simultaneously as the burr width, after logical circuit is handled, and will be by filtering.Have 4 width among Fig. 5 less than the burrs of two clock cycle, after treatment, do not had burr among the output signal Vout.
Come as can be seen from this embodiment,, can eliminate the burr width of width less than two Clk cycles when latching progression when being 5.So apparently, in other embodiments, as eliminating the burr of width less than N clock cycle, then with N+2 d type flip flop cascade, to be input to combinational logic circuit except that the output signal Vout of the output of the d type flip flop of the N+1 first d type flip flop and whole device and carry out computing, the output of this combinational logic circuit is connected to the input of last d type flip flop, can eliminates the burr of width less than N clock cycle.Wherein, the logic that combinational logic circuit is realized is: being output as 1 when the N+1 level latch signal of input is 1 entirely, is to be output as 0 at 0 o'clock entirely; Otherwise be output as the currency of Vout.As for the value of N, can be provided with according to the width of burr in the actual environment for use.And the clock cycle under prerequisite less than the signal minimum widith, the size that can take all factors into consideration the possible width of burr, the delay that brings and power consumption decides, the cycle is more little, power consumption is big more, but postpones more little.
In sum, the present invention has the following advantages:
1) adaptation is wide, no matter the burr that the sort of approach produces, as long as the burr width is less than signal itself Width, can remove.
2) resource that takies is few, for the burr of elimination width less than N Clk cycle, only needs N+3 Individual d type flip flop.
3) output signal postpone with respect to input signal little, for eliminating width less than N Clk cycle Burr only needs to postpone N+3 Clk cycle.
D type flip flop in the foregoing circuit also can replace with other element, as long as can realize letter Number delayed latch get final product.
Claims (5)
1. method of removing burr in the signal is used for removing the burr of input signal (Vin), obtains output signal (Vout), and this method may further comprise the steps:
(a) selected clock signal, the burr width that eliminate is less than N clock cycle;
(b) input signal that needs deburring is carried out the N+2 level and latch, each grade latchs a clock cycle with the output signal of previous stage;
(c) described input signal (Vin) being latched each grade latch signal and the described output signal (Vout) that obtain through the 2nd grade to the N+2 level is input in the combinational logic circuit, be 1 if judge described each grade latch signal, described combinational logic circuit output valve is 1 signal (Vout_pre), if be 0, described combinational logic circuit output valve is 0 signal (Vout_pre), otherwise described combinational logic circuit output valve is the signal (Vout_pre) of described output signal (Vout) currency;
(d) export after the signal (Vout_pre) that described combinational logic circuit is exported latchs a clock cycle, obtain described output signal (Vout).
2. the method for claim 1 is characterized in that: described latching by d type flip flop of signal finished.
3. device of removing burr in the signal is used for removing the burr of input signal (Vin), obtains output signal (Vout), it is characterized in that, comprises N+3 latch and a combinational logic circuit, wherein:
Described latch all receives a clock signal, export after input signal latched a clock cycle, wherein the 1st to N+2 mutual cascade of latch, the 1st latch be input as input signal (Vin), the 2nd to the input as described combinational logic circuit of the output of N+2 latch and output signal (Vout), the output of this combinational logic circuit is input to N+3 latch again, exports described output signal (Vout) by this latch;
Described combinational logic circuit is 1 o'clock in described the 2nd output to N+2 latch entirely, is output as 1, as being 0 entirely, is output as 0, is output as the currency of output signal (Vout) in other cases.
4. device as claimed in claim 3 is characterized in that: described latch is a d type flip flop.
5. device as claimed in claim 4, it is characterized in that, described combinational logic circuit comprises a NOR gate, one with the door, first variable connector and second variable connector, described NOR gate and be the 2nd output to N+2 latch with the input of door, the output of described NOR gate is connected to the control end of first variable connector, described output with door is connected to the control end of second variable connector, two of first variable connector are input as logical zero and output signal (Vout), second multichannel is opened two outputs that are input as the logical one and first variable connector that ` closes, the control end of first variable connector is 1 o'clock, be output as logical zero, otherwise be output as the currency of output signal (Vout), the control end of second variable connector is 1 o'clock, is output as logical one, otherwise is output as the output of first variable connector.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101129157A CN100464501C (en) | 2006-09-12 | 2006-09-12 | Method and device for removing burrs in signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101129157A CN100464501C (en) | 2006-09-12 | 2006-09-12 | Method and device for removing burrs in signal |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1917368A CN1917368A (en) | 2007-02-21 |
| CN100464501C true CN100464501C (en) | 2009-02-25 |
Family
ID=37738280
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006101129157A Expired - Fee Related CN100464501C (en) | 2006-09-12 | 2006-09-12 | Method and device for removing burrs in signal |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100464501C (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102195619B (en) * | 2010-03-02 | 2014-09-03 | 国民技术股份有限公司 | Method and circuit for detecting and eliminating signal glitch |
| CN102594305A (en) * | 2011-01-17 | 2012-07-18 | 上海华虹集成电路有限责任公司 | Digital burr filtering circuit for clock pins of smart card |
| CN102831092B (en) * | 2011-06-14 | 2016-12-28 | 上海华虹集成电路有限责任公司 | USB full-speed device data signal synchronous circuit |
| CN106896634B (en) * | 2017-03-22 | 2019-03-29 | 青岛海信电器股份有限公司 | A kind of laser drive current burr removal circuit and method |
| CN106896635B (en) * | 2017-03-22 | 2018-11-16 | 青岛海信电器股份有限公司 | A kind of laser drive current burr removal circuit and method |
| CN107665033B (en) * | 2017-08-28 | 2020-06-09 | 上海集成电路研发中心有限公司 | Digital logic circuit module with reset deburring function |
| CN110350890B (en) * | 2019-07-24 | 2020-06-30 | 广芯微电子（广州）股份有限公司 | Method for filtering signal burrs in digital circuit |
| CN113904655B (en) * | 2021-12-10 | 2022-02-25 | 极限人工智能有限公司 | Filter circuit and medical 3D endoscope |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5596284A (en) * | 1994-11-10 | 1997-01-21 | Brooktree Corporation | System for, and method of, minimizing noise in an integrated circuit chip |
| CN1281224A (en) * | 1999-07-14 | 2001-01-24 | 蒂雅克株式会社 | Noise removing device of digital data and data storage |
| CN1318162A (en) * | 1999-07-16 | 2001-10-17 | 瓦苏技术有限公司 | Digital electronic control unit |
| CN1624806A (en) * | 2003-08-28 | 2005-06-08 | 因芬尼昂技术股份公司 | Reference voltage detector for power-on sequence in a memory |
| US20060176085A1 (en) * | 2005-02-10 | 2006-08-10 | Oki Electric Industry Co., Ltd. | Comparator circuit with reduced switching noise |
-
2006
- 2006-09-12 CN CNB2006101129157A patent/CN100464501C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5596284A (en) * | 1994-11-10 | 1997-01-21 | Brooktree Corporation | System for, and method of, minimizing noise in an integrated circuit chip |
| CN1281224A (en) * | 1999-07-14 | 2001-01-24 | 蒂雅克株式会社 | Noise removing device of digital data and data storage |
| CN1318162A (en) * | 1999-07-16 | 2001-10-17 | 瓦苏技术有限公司 | Digital electronic control unit |
| CN1624806A (en) * | 2003-08-28 | 2005-06-08 | 因芬尼昂技术股份公司 | Reference voltage detector for power-on sequence in a memory |
| US20060176085A1 (en) * | 2005-02-10 | 2006-08-10 | Oki Electric Industry Co., Ltd. | Comparator circuit with reduced switching noise |
Non-Patent Citations (4)
| Title |
|---|
| 如何解决FPGA电路设计中的毛刺问题. 张志杰，汪翔.世界电子元器件. 2004 |
| 如何解决FPGA电路设计中的毛刺问题. 张志杰，汪翔.世界电子元器件. 2004 * |
| 消除CPLD/FPGA器件设计中的毛刺. 何伟，张玲.重庆大学学报，第25卷第12期. 2002 |
| 消除CPLD/FPGA器件设计中的毛刺. 何伟，张玲.重庆大学学报，第25卷第12期. 2002 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1917368A (en) | 2007-02-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100464501C (en) | Method and device for removing burrs in signal | |
| CN100508391C (en) | A device and method to eliminate signal burr | |
| US7952391B2 (en) | Digital noise filter | |
| CN103269212B (en) | Low cost low-power consumption Multilevel FIR filter implementation method able to programme | |
| CN101997539B (en) | Programmable logic circuit | |
| CN203909710U (en) | Multifunctional low-level reset circuit suitable for SoC chips | |
| CN101009487A (en) | Cross-clock domain asynchronous data processing, cross-clock domain method of the asynchronous data, and its device | |
| CN112667292B (en) | Asynchronous micro-pipeline controller | |
| CN105281708B (en) | A kind of high speed FIR filter achieving method based on segmentation parallel processing | |
| Lewis et al. | Reconfigurable latch controllers for low power asynchronous circuits | |
| CN105141286B (en) | Filter out the digital filter of one clock period pulse and burr | |
| CN102790605B (en) | asynchronous signal synchronizer | |
| CN108540128B (en) | Clock frequency dividing circuit and frequency dividing method thereof | |
| CN102594305A (en) | Digital burr filtering circuit for clock pins of smart card | |
| CN103874968A (en) | Energy-efficient pipeline circuit templates for high performance asynchronous circuits | |
| Al-Dulaimi et al. | Design and Implementation of Communication Digital FIR Filter for Audio Signals on the FPGA Platform. | |
| CN110350890B (en) | Method for filtering signal burrs in digital circuit | |
| CN103580647A (en) | Filter structure | |
| Kuo et al. | A programmable interpolation filter for digital communications applications | |
| CN106201950B (en) | Method for SOC asynchronous clock domain signal interface | |
| KR100429573B1 (en) | Method for creating Register transfer level code | |
| CN106571804A (en) | Standard interface circuit of high-impedance digital phase detector output stage | |
| CN2638332Y (en) | Cross time clock domain signal synchronous treatment circuit | |
| CN111600580A (en) | Overlapping clock high performance flip-flop | |
| US7463083B2 (en) | Noise reduction in digital systems when the noise is caused by simultaneously clocking data registers |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090225 Termination date: 20120912 |