CN102594305A - Digital burr filtering circuit for clock pins of smart card - Google Patents
Digital burr filtering circuit for clock pins of smart card Download PDFInfo
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- CN102594305A CN102594305A CN2011100095120A CN201110009512A CN102594305A CN 102594305 A CN102594305 A CN 102594305A CN 2011100095120 A CN2011100095120 A CN 2011100095120A CN 201110009512 A CN201110009512 A CN 201110009512A CN 102594305 A CN102594305 A CN 102594305A
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Abstract
Disclosed is a digital burr filtering circuit for clock pins of a smart card. The burr filtering circuit which is composed by a plurality of gate circuits is added at the input end of the clock pins of the smart card, high frequency burrs on the clock pins are filtered on the promise that the duty ratio is not affected. The circuit comprises a NOND gate, a NOR gate, an inverter, a delayed component chain, and a reset-set (RS) flip-flop. According to the digital burr filtering circuit for the clock pins of the smart card, nanosecond burrs can be filtered effectively, and the problem of interference to clock pins of the smart card is solved.
Description
Technical field
The present invention relates to a kind of numeral filter burr circuit, relate in particular to the numeral filter burr circuit that does not influence duty ratio in a kind of application of IC cards.
Background technology
Nowadays application of IC cards spreads to each field, such as each field of public transport, social security, identification or the like.Intelligent card chip Chevron Research Company (CRC) improves constantly the antijamming capability of smart card in order to improve the competitiveness of smart card product, and more high quality product is provided.In jamproof design, the antijamming capability that improves on the smart card clock pin is an important step of the antijamming capability of raising.
The foundry that the clock pin that smart card uses is generally processed by intelligent card chip is produced when chip manufacture and is provided.According to different foundries and different processes line, the circuit design of clock pin can be different.Can contain this schmitt trigger in the design generally speaking, have certain filter function.But the advantages of simple design that some foundries are also arranged does not contain this schmitt trigger, can not filtering.The clock pin of smart card product if there is not filter, is very dangerous, can influence the performance of entire chip.
The chip foundries does not provide under the situation of the clock pin that has this schmitt trigger, must be by intelligent card chip designer oneself exploitation filter circuit.If the employing analog circuit, the design more complicated, it is bigger to influence area of chip, and system integration person's task is also more loaded down with trivial details.The employing digital circuit is accomplished, and easier, area is smaller, integrated convenience.
Interference on the intelligent card chip clock pin, main interference from the high frequency burr.How designing a kind of numeral filter burr circuit, can solve the influence that above-mentioned Burr Problem is brought, can not influence the duty ratio of chip clock again, is technical problem to be solved by this invention.
Summary of the invention
The object of the invention provides a kind of numeral filter burr circuit that is applied to smart card clock pin, and the input that is employed in smart card clock pin adds a filter burr circuit that is made up of a plurality of gate circuits, and the high frequency burr on the clock pin is filtered.Can effectively filter the nanosecond burr and disturb, solve the anti-interference problem of smart card clock pin.
Numeral is filtered the burr circuit by two inverters, a NAND gate, and NOR gate, time delay device chain and a NAND gate rest-set flip-flop are formed, and the time delay device chain is made up of a plurality of time delay devices.
Two inverters, a NAND gate, the circuit that a NOR gate and a plurality of time delay device are formed is handled input clock signal, produces two paths of signals.The delay time width that the time delay device chain produces is greater than the width that disturbs burr.If input is the high level burr signal that on the low level basis, occurs, then can be filtered at the NOR gate output, be exaggerated into two burrs at the NAND gate output.If input is the low level burr signal that on the high level basis, occurs, then can be filtered at the NAND gate output, be exaggerated into two burrs at the NOR gate output, therefore at least one road signal is no burr signal.
The rest-set flip-flop of forming by NAND gate; Two paths of signals to above-mentioned is handled; According to the principle of NAND gate rest-set flip-flop, utilize carrot-free one road signal, mask other one road bistrichiasis thorn signal; Produce a clock signal with duty ratios such as former input clocks at last, this clock signal has filtered the high frequency burr.
Description of drawings
The numeral filter burr circuit diagram of Fig. 1 application of IC cards provided by the invention
The numeral filter burr circuit output signal oscillogram of Fig. 2 application of IC cards
Specific embodiments
Below in conjunction with each accompanying drawing the content that the present invention proposes is carried out detailed description.Fig. 1 is a circuit diagram of the present invention:
The input clock of the clock pin of intelligent card chip circuit is Clk_in, is Clk_inv through one-level inverter 1 back.According to the test data of smart card product test, confirm interference burr on the clock pin is in how many nano-seconds.Specifically realize technology to product, look into the standard cell lib explanation document that relevant foundries provides.Find the time delay device that delay function is provided, between area and time-delay ability, analyze, select respective type, the time delay device 4 of respective drive ability is formed a time delay device chain.The delay time width that this time delay device chain produces is just in time greater than the width that disturbs burr.Clk_inv produces signal Clk_del through behind the time delay device chain.
Clk_del and Clk_inv are through a NOR gate 2; Produce signal Clk_nor; Clk_nor is through an inverter; Produce signal Clk_nor_inv, this signal is used for doing
end of next stage rest-set flip-flop 5.Clk_del and Clk_inv are through a NAND gate 3; Produce signal Clk_nand, this signal is used for doing
end of next stage rest-set flip-flop 5.
Clk_nor_inv and Clk_nand input to NAND gate rest-set flip-flop 5.If existing attitude: the trigger input signal (
End) changes preceding state, use Q
nExpression; If next state: the state after the trigger input signal changes, use Q
N+1Expression, then through looking into truth table: the basic rest-set flip-flop property list that NAND gate is formed:
Q end obtains a signal with former clock same duty cycle, but phase place is opposite with former clock, and certain time-delay is arranged.The Q end output signal of rest-set flip-flop 5 through an inverter 6, is exported last signal Clk_out.This signal is the final burr clock signal afterwards that filters.This signal and former clock same duty cycle, phase place has certain time-delay, and the time of time-delay approximates the delay time of time delay device chain.The waveform of respectively exporting signal in the circuit as shown in Figure 2.
Claims (4)
1. a numeral that is applied to smart card clock pin is filtered the burr circuit; Constitute by NAND gate, NOR gate, inverter, time delay device chain and rest-set flip-flop; It is characterized in that circuit input signal is divided into two-way behind inverter and time delay device chain; One road signal is behind NOR gate and inverter, for another road signal of reset terminal
of subordinate's rest-set flip-flop is the set end
of subordinate's rest-set flip-flop behind NAND gate circuit
2. a kind of numeral filter burr circuit that is applied to smart card clock pin as claimed in claim 1 is characterized in that the said two paths of signals that behind inverter and time delay device chain, produces, and at least one road signal is no burr signal.
3. a kind of numeral filter burr circuit that is applied to smart card clock pin as claimed in claim 1, it is characterized in that: the delay time width that the time delay device chain produces is greater than the width that disturbs burr.
4. a kind of numeral filter burr circuit that is applied to smart card clock pin as claimed in claim 1; The rest-set flip-flop that it is characterized in that the NAND gate composition is handled the two paths of signals of circuit; Produce a clock signal with duty ratios such as former input clocks, this clock signal has filtered the high frequency burr.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100095120A CN102594305A (en) | 2011-01-17 | 2011-01-17 | Digital burr filtering circuit for clock pins of smart card |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100095120A CN102594305A (en) | 2011-01-17 | 2011-01-17 | Digital burr filtering circuit for clock pins of smart card |
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| Publication Number | Publication Date |
|---|---|
| CN102594305A true CN102594305A (en) | 2012-07-18 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2011100095120A Pending CN102594305A (en) | 2011-01-17 | 2011-01-17 | Digital burr filtering circuit for clock pins of smart card |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106330178A (en) * | 2015-07-02 | 2017-01-11 | 龙芯中科技术有限公司 | Digital delay phase-locked loop and method of controlling digital delay phase-locked loop |
| CN106936411A (en) * | 2015-12-30 | 2017-07-07 | 格科微电子（上海）有限公司 | The digital trigger of anti-noise jamming |
| CN109379063A (en) * | 2018-10-29 | 2019-02-22 | 无锡中微爱芯电子有限公司 | A kind of MCU clock switch circuit |
| CN110729991A (en) * | 2019-11-13 | 2020-01-24 | 珠海格力电器股份有限公司 | Time delay circuit and servo driver |
| CN111917288A (en) * | 2019-05-10 | 2020-11-10 | 北京兆易创新科技股份有限公司 | Charge pump system |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5418486A (en) * | 1994-01-28 | 1995-05-23 | Vlsi Technology, Inc. | Universal digital filter for noisy lines |
| CN1917368A (en) * | 2006-09-12 | 2007-02-21 | 北京中星微电子有限公司 | Method and device for removing burrs in signal |
| CN1964189A (en) * | 2006-12-01 | 2007-05-16 | 北京中星微电子有限公司 | A device and method to eliminate signal burr |
| CN101515796A (en) * | 2009-04-02 | 2009-08-26 | 钜泉光电科技（上海）有限公司 | Digital signal noise filtering device |
| JP2009278476A (en) * | 2008-05-16 | 2009-11-26 | Seiko Epson Corp | Semiconductor integrated circuit |
-
2011
- 2011-01-17 CN CN2011100095120A patent/CN102594305A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5418486A (en) * | 1994-01-28 | 1995-05-23 | Vlsi Technology, Inc. | Universal digital filter for noisy lines |
| CN1917368A (en) * | 2006-09-12 | 2007-02-21 | 北京中星微电子有限公司 | Method and device for removing burrs in signal |
| CN1964189A (en) * | 2006-12-01 | 2007-05-16 | 北京中星微电子有限公司 | A device and method to eliminate signal burr |
| JP2009278476A (en) * | 2008-05-16 | 2009-11-26 | Seiko Epson Corp | Semiconductor integrated circuit |
| CN101515796A (en) * | 2009-04-02 | 2009-08-26 | 钜泉光电科技（上海）有限公司 | Digital signal noise filtering device |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106330178A (en) * | 2015-07-02 | 2017-01-11 | 龙芯中科技术有限公司 | Digital delay phase-locked loop and method of controlling digital delay phase-locked loop |
| CN106330178B (en) * | 2015-07-02 | 2019-02-19 | 龙芯中科技术有限公司 | Digital delay locked loop and the method for controlling digital delay locked loop |
| CN106936411A (en) * | 2015-12-30 | 2017-07-07 | 格科微电子（上海）有限公司 | The digital trigger of anti-noise jamming |
| CN106936411B (en) * | 2015-12-30 | 2021-07-27 | 格科微电子（上海）有限公司 | Digital trigger with noise interference resistance |
| CN109379063A (en) * | 2018-10-29 | 2019-02-22 | 无锡中微爱芯电子有限公司 | A kind of MCU clock switch circuit |
| CN109379063B (en) * | 2018-10-29 | 2022-06-28 | 无锡中微爱芯电子有限公司 | MCU clock switching circuit |
| CN111917288A (en) * | 2019-05-10 | 2020-11-10 | 北京兆易创新科技股份有限公司 | Charge pump system |
| CN110729991A (en) * | 2019-11-13 | 2020-01-24 | 珠海格力电器股份有限公司 | Time delay circuit and servo driver |
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Application publication date: 20120718 |