CN1917368A - Method and device for removing burrs in signal - Google Patents
Method and device for removing burrs in signal Download PDFInfo
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- CN1917368A CN1917368A CN 200610112915 CN200610112915A CN1917368A CN 1917368 A CN1917368 A CN 1917368A CN 200610112915 CN200610112915 CN 200610112915 CN 200610112915 A CN200610112915 A CN 200610112915A CN 1917368 A CN1917368 A CN 1917368A
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Abstract
The invention is designed for removing the spurs from the input signal Vin and getting an output signal Vout. The apparatus comprises N+3 latches and a combinational logic circuit. All said latches receive a clock signal and output it after latching it one clock cycle; wherein N+2 latches are in cascade connection each other; the input of the first latch is the input signal Vin, and the output and input signals Vout of next N-1 latches is taken as the input of said combinational logic circuit; the output of the combinational logic circuit is inputted to a latch; said latch outputs the output signal; when all outputs of the N+1 latches are 1, the output is 1; when all outputs are 0, the output is 0; otherwise the output is the current value of Vout.
Description
Technical field
The present invention relates to a kind of signal processing method and device, relate in particular to the removal method and apparatus of burr in a kind of signal.
Background technology
In circuit shown in Figure 1, the output signal of chip 1 generates input signal through behind the input circuit of output circuit, signal transmssion line and chip 2, and is often jagged on this input signal.
The generation approach of burr probably has following three kinds:
1) output signal itself is just jagged.For example, output signal is not register output, but during combinational logic output, often just jagged in the signal.
The burr that produces when 2) on signal transmssion line, transmitting.For example the radio noise source induces burr signal on transmission line, the signal cross-talk between the signal transmssion line etc.
3) after handling, input circuit also may produce burr.If the rising edge of signal (or trailing edge) slow (as reaching the microsecond level) then near input circuit threshold value thresholding, may produce burr, as shown in Figure 2.
Vht is the high level thresholding among the figure, if i.e. input signal Vin＞=Vht, output signal Vout=1; Vlt is the low level thresholding, if input signal Vin＜=Vlt, then output signal Vout=0; And if Vht＞Vin＞Vlt, then Vout can not obtain stable numerical value, may also may be 1 for 0.
Signal in the literary composition is digital signal.So-called burr, promptly its width is less than the signal minimum widith of definition.There are 3 such burrs among Fig. 2.
Burr in the signal tends to cause the misoperation of subsequent logic, so the removal of burr has become the common problem that must face of present interface circuit design.The approach and the subsequent conditioning circuit characteristic separately that produce according to burr have a lot of burr removal methods.
At the approach that burr produces, following three kinds of methods of eliminating burr are arranged usually:
1) at approach 1, can require to adopt register output, do not allow combinational logic output;
2) at approach 2, can when system design, require the intensity and the distance of control source of radio-frequency interference, can require crosstalking between the control signal wire;
3), may be required in adding Schmidt comparator on the input circuit at approach 3.
If can not control each approach that burr produces, that just needs special circuit to eliminate burr.According to the requirement difference of subsequent conditioning circuit to input, various burr removing methods are often arranged, for example:
1), so just can only be concerned about that clock is along near burr if input and output have synchronized relation;
2) subsequent conditioning circuit may only be concerned about the rising edge or the trailing edge of signal, so just can remove the burr of rising edge or trailing edge specially;
3) if subsequent conditioning circuit only to the level signal sensitivity of input, so just can adopt the method deburring of voting by a show of hands.
More than the main deficiency of these methods be, be not a general burr removing method, but at certain special circumstances, adaptive surface is narrower.
Summary of the invention
The technical problem to be solved in the present invention is that a kind of method and device thereof of removing burr in the signal will be provided, and has realized the bigger scope of application with less cost.
In order to solve the problems of the technologies described above, the invention provides a kind of method of removing burr in the signal, be used for removing the burr of input signal Vin, obtain output signal Vout, this method may further comprise the steps:
(a) selected clock signal is established the burr width that will eliminate less than N clock cycle;
(b) the input signal Vin that needs deburring is carried out the N+2 level and latch, each grade latchs a clock cycle with the output signal of previous stage;
(c) judge back N+1 level latch signal, as being 1 entirely, output valve is 1 signal Vout_pre, and as being 0 entirely, output valve is 0 signal Vout_pre, otherwise output valve is the signal Vout_pre of Vout currency;
(d) export after signal Vout_pre is latched a clock cycle, obtain output signal Vout.
In a preferred embodiment, described latching by d type flip flop of signal finished.
The present invention provides a kind of device of removing burr in the signal again, is used for removing the burr of input signal Vin, obtains output signal Vout, it is characterized in that, comprises N+3 latch and a combinational logic circuit, wherein:
Described latch all receives a clock signal, export after input signal latched a clock cycle, N+2 the mutual cascade of latch, the 1st latch be input as input signal Vin, the output of a back N-1 latch and output signal Vout are as the input of described combinational logic circuit, the output of this combinational logic circuit is input to a latch again, exports described output signal Vout by this latch;
Described combinational logic circuit is 1 o'clock in the output of N+1 the latch in described back entirely, is output as 1, as being 0 entirely, is output as 0, is output as the currency of output signal Vout in other cases.
In a preferred embodiment, described latch is a d type flip flop.
In a preferred embodiment, described combinational logic circuit comprises a NOR gate, one with the door, first variable connector and second variable connector, described NOR gate and be the output of N-1 the latch in back with the input of door, the output of described NOR gate is connected to the control end of first variable connector, described output with door is connected to the control end of second variable connector, two of first variable connector are input as logical zero and output signal Vout, two outputs that are input as the logical one and first variable connector of second variable connector, the control end of first variable connector is 1 o'clock, be output as logical zero, otherwise be output as signal Vout, the control end of second variable connector is 1 o'clock, be output as logical one, otherwise be output as the output of first variable connector.
The present invention adapts to wide, no matter the burr that the sort of approach produces can be removed, the resource that takies is few, and output signal postpones little with respect to input signal.
Description of drawings
Fig. 1 is the schematic diagram of two chip chamber signal transmission.
Fig. 2 is near the schematic diagram that produces burr input circuit threshold value thresholding.
Fig. 3 is an embodiment of the invention manipulated or operated apparatus.
Fig. 4 is a kind of enforcement structure chart of combinational logic circuit among Fig. 3.
Fig. 5 is the oscillogram that embodiment of the invention burr is eliminated.
Embodiment
Shown in Figure 3 is the present embodiment manipulated or operated apparatus.As shown in the figure, comprise 5 d type flip flop D1～D5 and a combinational logic circuit, each d type flip flop is exported after a clock cycle signal latch, and signal point of observation and signal output point are all at the rising edge of clock.
Clk is a synchronised clock, is input to the input end of clock of all triggers.Vin is the input signal of band burr, the input of Vin input trigger D1 (D end), and trigger D1～D4 cascade successively, promptly the output of previous trigger (Q end) is connected to the input of a back trigger.Vin_d1, Vin_d2, Vin_d3 and Vin_d4 are respectively the output signals of trigger D1～D4, Vin_d1 has done one-level to Vin and has latched, Vin_d2 has done one-level to Vin_d1 and has latched, and Vin_d3 has done one-level to Vin_d2 and latched, and Vin_d4 has done one-level to Vin_d3 and latched.Therefore Vin_d1, Vin_d2, Vin_d3 and Vin_d4 are the one-level of Vin to the level Four latch signal.
Vin_d2, Vin_d3, Vin_d4 and Vout are as the input of combinational logic circuit, and the output signal Vout_pre of combinational logic circuit is input to trigger D5 again, and it is output as the output signal Vout that has removed burr.The structure of this combinational logic circuit comprises one three input NOR gate, three inputs and door and two two input mux as shown in Figure 4.Three input NOR gate are output as 1 when three input signal Vin_d2, Vin_d3, Vin_d4 are zero entirely, otherwise are 0; Three inputs and Men Zaisan input signal Vin_d2, Vin_d3, Vin_d4 were output as 1 at 1 o'clock, otherwise were 0.The output of three input NOR gate is as the control signal of first two input mux, and this control end is 1 o'clock, the value of I/O 1, and this value is logical zero, another input 0 of this two input mux is connected to output signal Vout.The output of three inputs and door is as the control signal of second two input mux, and this signal is 1 o'clock, the value of I/O 1, and this value is logical one, another input of this two input mux is connected to the output of first two input mux.
Those skilled in the art can understand, and the implementation of this combinational logic circuit has a variety of, but its function is: at second, third and fourth stage latch signal (being Vin_d2, Vin_d3 and Vin_d4) is 1 o'clock entirely, and output signal Vout_pre is 1; These three grades of latch signals are 0 o'clock entirely, and output signal Vout_pre is zero; Otherwise Vout_pre is the value of Vout, and it is constant promptly to keep the Vout value.
Signal Vout_pre is input to the input of trigger D5, latchs back output signal Vout, simultaneously this signal is input to combinational logic circuit.
As can be seen from Figure 4, the one-level latch signal Vin_d1 that obtains after the first order latchs is synchronized to the Clk clock zone, has removed near the burr of the width of non-rising edge less than a clock cycle simultaneously.Vin_d2 has done one-level again and has latched on the basis of Vin_d1, postponed 1 clock cycle than Vin_d1, to eliminate metastable state.Vin_d3 postpones a clock cycle again than Vin_d2, and Vin_d4 postpones a clock cycle again than Vin_d3.Therefore, less than two clock cycle, after it was synchronous by clock signal, the burr in Vin_d2, Vin_d3 and Vin_d4 signal can not be " 0 " or " 1 " simultaneously as the burr width, after logical circuit is handled, and will be by filtering.Have 4 width among Fig. 4 less than the burrs of two clock cycle, after treatment, do not had burr among the output signal Vout.
Come as can be seen from this embodiment,, can eliminate the burr width of width less than two Clk cycles when latching progression when being 5.So apparently, in other embodiments, as eliminating the burr of width less than N clock cycle, then with N+2 d type flip flop cascade, to be input to combinational logic circuit except that the output signal Vout of the output of the d type flip flop of the N+1 first d type flip flop and whole device and carry out computing, the output of this combinational logic circuit is connected to the input of last d type flip flop, can eliminates the burr of width less than N clock cycle.Wherein, the logic that combinational logic circuit is realized is: being output as 1 when the N+1 level latch signal of input is 1 entirely, is to be output as 0 at 0 o'clock entirely; Otherwise be output as the currency of Vout.As for the value of N, can be provided with according to the width of burr in the actual environment for use.And the clock cycle under prerequisite less than the signal minimum widith, the size that can take all factors into consideration the possible width of burr, the delay that brings and power consumption decides, the cycle is more little, power consumption is big more, but postpones more little.
In sum, the present invention has the following advantages:
1) adaptation is wide, no matter the burr that the sort of approach produces, as long as the burr width can be removed less than the width of signal itself.
2) resource that takies is few, for the burr of elimination width less than N Clk cycle, only needs N+3 d type flip flop.
3) output signal is little with respect to the input signal delay, for the burr of elimination width less than N Clk cycle, only needs to postpone N+3 Clk cycle.
D type flip flop in the foregoing circuit also can replace with other element, as long as can realize the delayed latch to signal.
Claims (5)
1, a kind of method of removing burr in the signal is used for removing the burr of input signal Vin, obtains output signal Vout, and this method may further comprise the steps:
(a) selected clock signal is established the burr width that will eliminate less than N clock cycle;
(b) the input signal Vin that needs deburring is carried out the N+2 level and latch, each grade latchs a clock cycle with the output signal of previous stage;
(c) judge back N+1 level latch signal, as being 1 entirely, output valve is 1 signal Vout_pre, and as being 0 entirely, output valve is 0 signal Vout_pre, otherwise output valve is the signal Vout_pre of Vout currency;
(d) export after signal Vout_pre is latched a clock cycle, obtain output signal Vout.
2, the method for claim 1 is characterized in that: described latching by d type flip flop of signal finished.
3, a kind of device of removing burr in the signal is used for removing the burr of input signal Vin, obtains output signal Vout, it is characterized in that, comprises N+3 latch and a combinational logic circuit, wherein:
Described latch all receives a clock signal, export after input signal latched a clock cycle, N+2 the mutual cascade of latch, the 1st latch be input as input signal Vin, the output of a back N-1 latch and output signal Vout are as the input of described combinational logic circuit, the output of this combinational logic circuit is input to a latch again, exports described output signal Vout by this latch;
Described combinational logic circuit is 1 o'clock in the output of N+1 the latch in described back entirely, is output as 1, as being 0 entirely, is output as 0, is output as the currency of output signal Vout in other cases.
4, device as claimed in claim 4 is characterized in that: described latch is a d type flip flop.
5, device as claimed in claim 4, it is characterized in that, described combinational logic circuit comprises a NOR gate, one with the door, first variable connector and second variable connector, described NOR gate and be the output of N-1 the latch in back with the input of door, the output of described NOR gate is connected to the control end of first variable connector, described output with door is connected to the control end of second variable connector, two of first variable connector are input as logical zero and output signal Vout, two outputs that are input as the logical one and first variable connector of second variable connector, the control end of first variable connector is 1 o'clock, be output as logical zero, otherwise be output as signal Vout, the control end of second variable connector is 1 o'clock, is output as logical one, otherwise is output as the output of first variable connector.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101129157A CN100464501C (en) | 2006-09-12 | 2006-09-12 | Method and device for removing burrs in signal |
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| CNB2006101129157A CN100464501C (en) | 2006-09-12 | 2006-09-12 | Method and device for removing burrs in signal |
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| CN1917368A true CN1917368A (en) | 2007-02-21 |
| CN100464501C CN100464501C (en) | 2009-02-25 |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102195619A (en) * | 2010-03-02 | 2011-09-21 | 国民技术股份有限公司 | Method and circuit for detecting and eliminating signal glitch |
| CN102594305A (en) * | 2011-01-17 | 2012-07-18 | 上海华虹集成电路有限责任公司 | Digital burr filtering circuit for clock pins of smart card |
| CN102831092A (en) * | 2011-06-14 | 2012-12-19 | 上海华虹集成电路有限责任公司 | Data signal synchronization circuit of universal serial bus (USB) full-speed device |
| CN106896635A (en) * | 2017-03-22 | 2017-06-27 | 青岛海信电器股份有限公司 | A kind of laser drive current burr removes circuit and method |
| CN106896634A (en) * | 2017-03-22 | 2017-06-27 | 青岛海信电器股份有限公司 | A kind of laser drive current burr removes circuit and method |
| CN107665033A (en) * | 2017-08-28 | 2018-02-06 | 上海集成电路研发中心有限公司 | It is a kind of that there is the Digital Logical Circuits module for resetting deburring function |
| CN110350890A (en) * | 2019-07-24 | 2019-10-18 | 广芯微电子（广州）股份有限公司 | The filtering method of signal burr in a kind of digital circuit |
| CN113904655A (en) * | 2021-12-10 | 2022-01-07 | 极限人工智能有限公司 | Filter circuit and medical 3D endoscope |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5596284A (en) * | 1994-11-10 | 1997-01-21 | Brooktree Corporation | System for, and method of, minimizing noise in an integrated circuit chip |
| TW472456B (en) * | 1999-07-14 | 2002-01-11 | Teac Corp | Noise signal free device and data memorizing device for digital data |
| AU5064099A (en) * | 1999-07-16 | 2001-02-05 | Vasu Tech Limited | Digital electronic control unit |
| US6956409B2 (en) * | 2003-08-28 | 2005-10-18 | Infineon Technologies Ag | Reference voltage detector for power-on sequence in a memory |
| JP4467445B2 (en) * | 2005-02-10 | 2010-05-26 | Ｏｋｉセミコンダクタ株式会社 | Comparator circuit |
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- 2006-09-12 CN CNB2006101129157A patent/CN100464501C/en not_active Expired - Fee Related
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| CN102195619A (en) * | 2010-03-02 | 2011-09-21 | 国民技术股份有限公司 | Method and circuit for detecting and eliminating signal glitch |
| CN102594305A (en) * | 2011-01-17 | 2012-07-18 | 上海华虹集成电路有限责任公司 | Digital burr filtering circuit for clock pins of smart card |
| CN102831092A (en) * | 2011-06-14 | 2012-12-19 | 上海华虹集成电路有限责任公司 | Data signal synchronization circuit of universal serial bus (USB) full-speed device |
| CN102831092B (en) * | 2011-06-14 | 2016-12-28 | 上海华虹集成电路有限责任公司 | USB full-speed device data signal synchronous circuit |
| CN106896634B (en) * | 2017-03-22 | 2019-03-29 | 青岛海信电器股份有限公司 | A kind of laser drive current burr removal circuit and method |
| CN106896635A (en) * | 2017-03-22 | 2017-06-27 | 青岛海信电器股份有限公司 | A kind of laser drive current burr removes circuit and method |
| CN106896634A (en) * | 2017-03-22 | 2017-06-27 | 青岛海信电器股份有限公司 | A kind of laser drive current burr removes circuit and method |
| CN106896635B (en) * | 2017-03-22 | 2018-11-16 | 青岛海信电器股份有限公司 | A kind of laser drive current burr removal circuit and method |
| CN107665033A (en) * | 2017-08-28 | 2018-02-06 | 上海集成电路研发中心有限公司 | It is a kind of that there is the Digital Logical Circuits module for resetting deburring function |
| CN107665033B (en) * | 2017-08-28 | 2020-06-09 | 上海集成电路研发中心有限公司 | Digital logic circuit module with reset deburring function |
| CN110350890A (en) * | 2019-07-24 | 2019-10-18 | 广芯微电子（广州）股份有限公司 | The filtering method of signal burr in a kind of digital circuit |
| CN110350890B (en) * | 2019-07-24 | 2020-06-30 | 广芯微电子（广州）股份有限公司 | Method for filtering signal burrs in digital circuit |
| CN113904655A (en) * | 2021-12-10 | 2022-01-07 | 极限人工智能有限公司 | Filter circuit and medical 3D endoscope |
| CN113904655B (en) * | 2021-12-10 | 2022-02-25 | 极限人工智能有限公司 | Filter circuit and medical 3D endoscope |
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| CN100464501C (en) | 2009-02-25 |
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