CN2886921Y - Multi-channel non mismatch clock control device - Google Patents
Multi-channel non mismatch clock control device Download PDFInfo
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- CN2886921Y CN2886921Y CN 200520134182 CN200520134182U CN2886921Y CN 2886921 Y CN2886921 Y CN 2886921Y CN 200520134182 CN200520134182 CN 200520134182 CN 200520134182 U CN200520134182 U CN 200520134182U CN 2886921 Y CN2886921 Y CN 2886921Y
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Abstract
The utility model provides a multi-channel non-unbalance clock control device, comprising a global clock circuit, a four-phase clock circuit, and two double-phase non-overlap clock circuits, wherein the four-phase clock circuit processes the frequency division to the clock input signal and produces a four-phase clock signal, the global clock circuit produces a global small pulse clock signal and a shield clock signal used for a pair of channel sampling clock signals and a pair of channel bottom-board sampling clock signals produced by the double-phase non-overlap clock circuit with 180 phase difference, between each pair of signals, the two double-phase non-overlap clock circuit totally produces four channel sampling clock signals and four channel bottom-board sampling clock signals. The phase difference of any channel sampling clock signals is divided equally. The phase difference of any channel bottom-board sampling clock signals is divided equally and synchronizes with the global small pulse clock signal. The global clock circuit eliminates the unbalance between various channels clock signals. The output clock signal definitely can meet the request of the multi-channel modulus switch.
Description
Technical field
The utility model relates to a kind of clock control device, and especially relating to a kind of multichannel does not have the mismatch clock control device.
Background technology
Analog to digital converter (ADC) converts analog quantity to digital quantity, is widely used.In Modern Communication System, need the analog to digital converter of high-speed, high precision, and the speed of analog to digital converter is subjected to the restriction of technology.For the speed that improves analog to digital converter can adopt clock intersection (time interleaving) technology, i.e. multichannel technology.Yet in the design of multi-channel circuit, have the clock mismatch between each passage, this can produce image spectra, has a strong impact on the performance of analog to digital converter, reduces the precision of analog to digital converter.Though can calibrate clock with calibration circuit, mismatch between clock is minimized, but just realize usually at sheet external application software, be difficult to circuit design in sheet, this is because the design of clock alignment circuit is very complicated, in design, because will there be certain error in calibration circuit itself, be difficult to the clock mismatch between accurate sense channel, and clock signal is adjusted.Therefore be difficult to reach the performance requirement of A/D converter with high speed and high precision.
Summary of the invention
The purpose of this utility model is to overcome the deficiency of prior art, provides a kind of and can eliminate the interchannel clock mismatch of each channel modulus converter four-channel mismatch-free clock control circuit.
Above-mentioned purpose of the present utility model is realized by following technical scheme:
A kind of four-channel mismatch-free clock control circuit includes a four-phase clock circuit 100 and two non-overlapping clock circuits 300,400 of two-phase, clock input signal
INBe connected to four-phase clock circuit 100, four-phase clock circuit 100 produces four four phase clock signal (0), (90), (180), the (270) of 90 ° of phase place inequality, 0 phase signal (0) and 180 ° of phase signal (180) in the four phase clock signals output to the non-overlapping clock circuit of first two-phase (300), 90 ° of phase signal (90) in the four phase clock signals and 270 ° of phase signal (270) output to non-overlapping clock circuit 300 output first and the third channel sampled clock signal of non-overlapping clock circuit 400, the first two-phases of second two-phase
1,
3With first and third channel base plate sampled clock signal
1p,
3p, non-overlapping clock circuit 400 output second and the four-way sampled clock signal of second two-phase
2,
1With second and four-way base plate sampled clock signal
2p,
4p, clock input signal
INConnect global clock circuit 200, four-phase clock circuit 100 output clock input signal
INTwo divided-frequency signal
2FPTo global clock circuit 200, global clock circuit 200 produces overall small-pulse effect clock signal
sOutput to two non-overlapping clock circuits 300,400 of two-phase, global clock circuit 200 also produces the shielding clock signal of 180 ° of two phase differences
p(0),
p(180), phase place is 180 ° shielding clock signal
p(180) output to the non-overlapping clock circuit 300 of first two-phase, phase place is 0 shielding clock signal
p(0) outputs to the non-overlapping clock circuit 400 of second two-phase.
Described global clock circuit is formed clock input signal by two phase inverter INV2, INV3, a NAND gate NAND1 and a d type flip flop DFF6
INBe connected to the input of the first phase inverter INV2 and NAND gate NAND1, the output of the first phase inverter INV2 is connected to another input of NAND gate NAND1, the output of NAND gate NAND1 is connected to the input of the second phase inverter INV3, and the output of the second phase inverter INV3 is overall small-pulse effect clock signal
IN, the input end of clock CK of d type flip flop DFF6 and data input pin D are connected the output of the first phase inverter INV2 respectively and by the two divided-frequency clock signal of four-phase clock circuit 100
2FP, its in-phase output end Q and reversed-phase output Q
ZBe respectively that phase place is 0 and 180 ° shielding clock signal
p(0),
p(180).
Described four-phase clock circuit 100 is made up of 5 d type flip flop DFF1, DFF2, DFF3, DFF4, DFF5 and a phase inverter INV1, and the input end of clock CK of the first d type flip flop DFF1 meets input clock signal
IN, reversed-phase output Q
ZD links to each other with data input pin, and in-phase output end Q is two divided-frequency clock signal
2FP, it connects the input end of clock CK of four d flip-flop DFF4 and the data input pin D of the second d type flip flop DFF2, and the input end of clock CK of the second trigger DFF2 connects input clock signal
IN, its in-phase output end Q connects the input end of clock CK of the 5th d type flip flop DFF5, its reversed-phase output Q
ZConnect the input of phase inverter INV1, the output of phase inverter INV1 connects the input end of clock CK of 3d flip-flop DFF3, the reversed-phase output Q of 3d flip-flop DFF3
ZD links to each other with data input pin, and its in-phase output end Q connects the data input pin D of four d flip-flop DFF4 and the 5th d type flip flop DFF5, the in-phase output end Q of four d flip-flop DFF4 and reversed-phase output Q
ZBe respectively four phase clock signal (0), the (180) of 0 and 180 ° of phase place, the in-phase output end Q of the 5th d type flip flop DFF5 and reversed-phase output Q
ZBe respectively four phase clock signal (90), the (270) of 90 ° and 270 ° phase places; The input of the non-overlapping clock circuit 300,400 of described two two-phases connects the overall small-pulse effect clock signal from global clock circuit 200
S, the input of the non-overlapping clock circuit 300 of first two-phase also connects in-phase output end Q, the reversed-phase output Q from the four d flip-flop DFF4 in the four-phase clock circuit 100
ZFour phase clock signal (0), the (180) of 0 and 180 ° of phase place, the input of the non-overlapping clock circuit 400 of second two-phase also connects in-phase output end Q, the reversed-phase output Q from the 5th d type flip flop DFF5 in the four-phase clock circuit 100
ZFour phase clock signal (90), the (270) of 90 ° and 270 ° phase places, non-overlapping clock circuit 300 phase difference outputs of first two-phase are 180 ° first and third channel sampled clock signal
1,
3With phase difference be 180 ° first and third channel base plate sampled clock signal
1p,
3pNon-overlapping clock circuit 400 phase difference outputs of second two-phase are 180 ° second and four-way sampled clock signal
2,
4With phase difference be 180 ° second and four-way base plate sampled clock signal
2p,
4pThe output of two non-overlapping clock circuits of two-phase is formed, four sampled clock signals of 90 ° of phase place inequality and four base plate sampled clock signals of 90 °, two the non-overlapping clock circuit of two-phase structures are identical, respectively contain two element circuits, two element circuit interconnections, each element circuit knot is identical, forms by a NAND gate, seven phase inverters, two NMOS pipes and a PMOS pipe; One of two input of the NAND gate NAND11 of the first module circuit of the non-overlapping clock circuit 300 of first two-phase fetch 0 phase place, the four phase clock signal (0) from four-phase clock circuit 100, the feedback end of another input termination second element circuit, NAND gate NAND11 output connects the input of the first phase inverter INV11 and the grid of PMOS pipe P11, the drain electrode of the input of the output termination second phase inverter INV12 of the first phase inverter INV11 and NMOS pipe N11 and the input of the 6th phase inverter INV16, the grid of NMOS pipe N11 connects the overall small-pulse effect clock signal from 200 outputs of global clock circuit
S, the source electrode of NMOS pipe N11 connects the drain electrode of the 2nd NMOS pipe N12, and the grid of the 2nd NMOS pipe N12 fetches the shielding clock signal from 180 ° of phase places of global clock circuit 200 outputs
p(180), the source ground of the 2nd NMOS pipe N12, the input of output termination the 3rd phase inverter INV13 of the second phase inverter INV12, the drain electrode of the input of output termination the 4th phase inverter INV14 of the 3rd phase inverter INV13 and PMOS pipe P11, the source electrode of PMOS pipe P11 connects power supply, the output of the 4th phase inverter INV14 is the feedback end of first module circuit, it is connected to the input of the NAND gate NAND31 of second element circuit, the output of the 4th phase inverter INV14 is also connected to the input of the 5th phase inverter INV15 simultaneously, the input of output termination the 7th phase inverter INV17 of the 6th phase inverter INV16, the output output first passage base plate sampled clock signal of the 7th phase inverter INV17
1p, when the output output first passage of the 5th phase inverter INV15 is sampled
Clock signal
1One of two input of the NAND gate NAND31 of second element circuit of the non-overlapping clock circuit 300 of first two-phase fetch four phase clock signal (180) from 180 ° of phase places of four-phase clock circuit 100, the feedback end of another input termination first module circuit, second element circuit output third channel base plate sampled clock signal
3pWith third channel sampled clock signal
3One of two input of the NAND gate NAND21 of the first module circuit of the non-overlapping clock circuit 400 of second two-phase fetch four phase clock signal (90) from 90 ° of phase places of four-phase clock circuit 100, the feedback end of another input termination second element circuit, first module circuit output second channel base plate sampled clock signal
2pWith second channel sampled clock signal
2One of two input of the NAND gate NAND41 of second element circuit of the non-overlapping clock circuit 400 of second two-phase fetch four phase clock signal (270) from 270 ° of phase places of four-phase clock circuit 100, the feedback end of another input termination first module circuit, second element circuit is exported four-way base plate sampled clock signal
4pWith four-way sampled clock signal
4Two non-overlapping clock circuits 300,400 of two-phase produce first, second, third and the four-way base plate sampled clock signal that phase difference is followed successively by 90 °
1p,
2p,
3p,
4pAnd phase difference is followed successively by 90 ° first, second, third and four-way channel sample clock signal
1,
2,
3,
4
Described in the element circuit of two non-overlapping clock circuits of two-phase the driving force of a NMOS pipe N11, N31, N21, N41 and the 2nd NMOS pipe N12, N32,22, N42 greater than the driving force of the first phase inverter INV11, INV31, INV21, INV41.
Advantage of the present utility model and effect: eliminate the interchannel clock mismatch of each channel modulus converter.The clock control circuit of four-way analog to digital converter of the present utility model adds a global clock, by with the clock signal of each passage mutually or, make the trailing edge of each channel clock signal consistent, thereby eliminated the mismatch between each channel clock signal with global clock.Experimental result shows that after handling by a global clock, it is very good that each interchannel clock signal is mated, and clock signal can satisfy the requirement of four-way analog to digital converter fully.
Description of drawings
Fig. 1 is the sampling hold circuit of four-way analog to digital converter of the present utility model.
Fig. 2 is a four-way analog to digital converter clock control circuit theory diagram of the present utility model.
Fig. 3 is a four-way analog to digital converter clock control circuit figure magnetizing current curve chart of the present utility model.
Fig. 4 is the oscillogram of no mismatch clock of the present utility model.
Wherein: 300 is that the non-overlapping clock circuit 1,400 of two-phase is the non-overlapping clock circuit 2 of two-phase
Embodiment
Below in conjunction with accompanying drawing and embodiment the utility model is described in further detail.
Fig. 1 is the sampling hold circuit of four-way analog to digital converter, and circuit is formed in parallel by four road sampling hold circuits, so sampling rate is 4 times of single sampling hold circuit.This sampling hold circuit adopts the base plate Sampling techniques, and sampled value is by backplane switch control signal
1p,
2p,
3p,
4pDecision, C1 among the figure, C2, C3, C4 are sampling capacitance, switch controlling signal
2,
3,
4Phase place and
1Differ 90 ° respectively, 180 °, 270 °.
1pWith
1Phase place is identical, but compares
1Turn-off a bit of time in advance.
Fig. 2 is a theory diagram of the present utility model, and circuit is made up of one four phase clock 100, a global clock 200 and two non-overlapping clock circuits 300 and 400 of two-phase.The input termination clock input signal of four-phase clock circuit 100
IN, be output as four phase clock signal (0), four phase clock signal (180), four phase clock signal (90) and four phase clock signal (270), and two divided-frequency clock signal
2FPTwo inputs of global clock circuit 200 connect clock input signal respectively
INWith two divided-frequency clock signal
2FP, be output as overall small-pulse effect clock signal
s, shielding clock signal
p(0) and shielding clock signal
p(180).Four inputs of the non-overlapping clock circuit 300 of two-phase meet 0 phase place, four phase clock signal (0), 180 ° of phase place four phase clock signal (180), overall small-pulse effect clock signal respectively
sWith 180 ° of of bit mask clock signal mutually
p(180), output is respectively first passage sampled clock signal
1, first passage base plate sampled clock signal
1p, third channel sampled clock signal
3With third channel base plate sampled clock signal
3pFour inputs of the non-overlapping clock circuit 400 of two-phase meet 90 ° of phase places, four phase clock signal (90), 270 ° of phase place four phase clock signal (270), overall small-pulse effect clock signal respectively
sWith 0 bit mask clock signal mutually
p(0), output is respectively second channel sampled clock signal
2, second channel base plate sampled clock signal
2p, four-way sampled clock signal
4With four-way base plate sampled clock signal
4pFour-phase clock circuit 100 is input signal 4 frequency divisions, and produces phase place and differ 0,90 ° respectively, and 180 °, 270 ° 4 tunnel four phase clock signals ( (0), (90), (180), (270)) and produced a two divided-frequency clock signal
2FPThe non-overlapping clock circuit of two-phase produces non-overlapping clock signal of two-way and respective base sampled clock signal, and output signal frequency is identical with frequency input signal.Overall situation small-pulse effect clock signal
sBe the very little small-pulse effect clock signal of duty ratio, signal frequency is identical with the input clock signal frequency, the base plate sampling clock phase of itself and the non-overlapping clock of two-phase or, the trailing edge of all base plate sampled clock signals is determined by same clock signal, has eliminated interchannel clock mismatch.
Fig. 3 is the mismatch-free clock control circuit of four-way analog to digital converter of the present utility model, is made up of the non-overlapping clock circuit of four-phase clock circuit, global clock circuit and two-phase.Four phase clocks be input as clock input signal
IN, be output as 0 phase place, four phase clock signal (0), 180 ° of phase place four phase clock signal (180), 90 ° of phase place four phase clock signal (90) and 270 ° of phase place four phase clock signal (270), and two divided-frequency clock signal
2FPThe CK termination input clock signal of d type flip flop DFF1
IN, output Q
ZD links to each other with input, and output Q is two divided-frequency clock signal
2FP, it connects the CK end of d type flip flop DFF4 and the D end of d type flip flop DFF2, the CK termination input clock signal of trigger DFF2
IN, in-phase output end Q connects the CK end of d type flip flop DFF5, reversed-phase output Q
ZThe input that connects phase inverter INV1, the output of phase inverter INV1 connect the CK end of d type flip flop DFF3, the reversed-phase output Q of d type flip flop DFF3
ZEnd links to each other with input D, and in-phase output end Q connects the D end of d type flip flop DFF4 and d type flip flop DFF5, output Q and the Q of d type flip flop DFF4
ZBe respectively 0 phase place, four phase clock signal (0) and 180 ° of phase place four phase clock signal (180), output Q and the Q of d type flip flop DFF5
ZBe respectively 90 ° of phase places, four phase clock signal (90) and 270 ° of phase place four phase clock signal (270).The input of global clock circuit meets input clock signal
INWith two divided-frequency clock signal
2FP, be output as overall small-pulse effect clock signal
s, 0 phase bit mask clock signal
p(0) with 180 ° of of bit mask clock signal mutually
p(180).Phase inverter INV2 input meets input clock signal
IN, output connects the end input of NAND gate NAND1 and the CK end of d type flip flop DFF6, another input termination input clock signal of NAND gate NAND1
IN, output connects the input of phase inverter INV3, and phase inverter INV3 is output as overall small-pulse effect clock signal
sThe D end of d type flip flop DFF6 connects the output Q of d type flip flop DFF1, output Q, Q
ZBe respectively 0 phase bit mask clock signal
p(0) with 180 ° of of bit mask clock signal mutually
p(180).The non-overlapping clock circuit 1 of two-phase be input as 0 phase place, four phase clock signal (0), 180 ° of phase place four phase clock signal (180), overall small-pulse effect clock signal
sWith 180 ° of of bit mask clock signal mutually
p(180), be output as first passage base plate sampled clock signal
1p, first passage sampled clock signal
1, third channel base plate sampled clock signal
3pWith third channel sampled clock signal
3The input of NAND gate NAND11 connects 0 phase place, four phase clock signal (0), output connects the input of phase inverter INV11 and the grid of PMOS pipe P11, phase inverter INV11 output connects the input of phase inverter INV12, the output of phase inverter INV12 connects the input of phase inverter INV13, the output of phase inverter INV13 connects the leakage of PMOS pipe P11 and the input of phase inverter INV14, the source of PMOS pipe P11 connects power supply, the output of phase inverter INV14 connects another input of NAND gate NAND31 and the input of phase inverter INV15, and phase inverter INV15 is output as first passage sampled clock signal
1The grid of NMOS pipe N12 connect 180 ° of phase bit mask clock signal
p(180), source ground connection is missed the source that NMOS manages N11, and the grid of NMOS pipe N11 connect overall small-pulse effect clock signal
s, leaking the output of connection phase inverter INV11 and the input of phase inverter INV16, the output of phase inverter INV16 connects the input of phase inverter INV17, and phase inverter INV17 is output as first passage base plate sampled clock signal
1pAnother input of NAND gate NAND31 connects 180 ° of phase places, four phase clock signal (180), output connects the input of phase inverter INV31 and the grid of PMOS pipe P31, phase inverter INV31 output connects the input of phase inverter INV32, the output of phase inverter INV32 connects the input of phase inverter INV33, the output of phase inverter INV33 connects the leakage of PMOS pipe P31 and the input of phase inverter INV34, the source of PMOS pipe P31 connects power supply, the output of phase inverter INV34 connects another input of NAND gate NAND11 and the input of phase inverter INV35, and phase inverter INV35 is output as third channel sampled clock signal
3The grid of NMOS pipe N32 connect 180 ° of phase bit mask clock signal
p(180), source ground connection is leaked the source that connects NMOS pipe N31, and the grid of NMOS pipe N31 connect overall small-pulse effect clock signal
s, leaking the output of connection phase inverter INV31 and the input of phase inverter INV36, the output of phase inverter INV36 connects the input section of phase inverter INV37, and phase inverter INV37 is output as third channel base plate sampled clock signal
3pThe non-overlapping clock circuit 2 of two-phase be input as 90 ° of phase places, four phase clock signal (90), 270 ° of phase place four phase clock signal (270), overall small-pulse effect clock signal
sWith 0 bit mask clock signal mutually
p(0), is output as second channel base plate sampled clock signal
2pWith second channel sampled clock signal
2, four-way base plate sampled clock signal
4pWith four-way sampled clock signal
4, the structure of its internal structure and non-overlapping two phase clock circuit 1 is identical.
Four-phase clock circuit is made up of 5 d type flip flops and a phase inverter.D type flip flop DFF1 is with input signal
IN2 frequency divisions, d type flip flop DFF2 postpones 1/4 cycle with the Q end output signal of d type flip flop DFF1.D type flip flop DFF4 and d type flip flop DFF5 are respectively to output signal 2 frequency divisions of d type flip flop DFF1 and d type flip flop DFF2.Phase inverter INV1 is to make the output signal of d type flip flop DFF4 and d type flip flop DFF5 consistent with the effect of d type flip flop DFF3.The global clock circuit is by two phase inverters, and a NAND gate and a d type flip flop are formed clock input signal
INBy producing frequency and clock input signal behind phase inverter INV2, phase inverter INV3 and the NAND gate NAND1
INIdentical small-pulse effect global clock signal
s, the d type flip flop DFF6 generation cycle is overall small-pulse effect clock signal
s2 times shielding clock signal
p(0) and
p(180), then with overall small-pulse effect clock signal
s, 0 phase bit mask clock signal
p(0) with 180 ° of of bit mask clock signal mutually
p(180) act on the non-overlapping clock circuit of two-phase, make each passage output clock not have mismatch.Concrete oscillogram such as Fig. 4.0 phase bit mask clock signal
p(0), 180 ° of phase bit mask clock signal
p(180) to overall small-pulse effect clock signal
sSome cycle masks, from oscillogram as can be seen, and
1p,
2p,
3p,
4pTrailing edge by overall small-pulse effect clock signal
sRising edge decision, clock signal like this
1p,
2p,
3p,
4pJust there is not mismatch.The non-overlapping clock circuit of two-phase generates the non-overlapping clock of two-phase with clock signal 0 phase clock (0) and 180 ° of phase place (180) of complementation, in order there not to be the mismatch clock preferably, the driving force of NMOS pipe N11, N12, N31, N32, N21, N22, N41, N42 is bigger than phase inverter INV11, INV31, INV21, INV41 among the figure.
Claims (4)
1, a kind of multichannel does not have the mismatch clock control device, includes a four-phase clock circuit (100) and two non-overlapping clock circuits of two-phase (300,400), clock input signal (
IN) be connected to four-phase clock circuit (100), four-phase clock circuit (100) produces four the four phase clock signals ( (0) of 90 ° of phase place inequality, (90), (180), (270)), 0 phase signal in the four phase clock signals ( (0)) and 180 ° of phase signals ( (180)) output to the non-overlapping clock circuit of first two-phase (300), 90 ° of phase signals in the four phase clock signals ( (90)) and 270 ° of phase signals ( (270)) output to the non-overlapping clock circuit of second two-phase (400), the non-overlapping clock circuit of first two-phase (300) output first and third channel sampled clock signal (
1,
3) and first and third channel base plate sampled clock signal (
1p,
3p), the non-overlapping clock circuit of second two-phase (400) output second and four-way sampled clock signal (
2,
4) and second and four-way base plate sampled clock signal (
2p,
4p);
It is characterized in that: clock input signal (
IN) connecting global clock circuit (200), four-phase clock circuit (100) is exported clock input signal (
IN) two divided-frequency signal (
2FP) to global clock circuit (200), global clock circuit (200) produces overall small-pulse effect clock signal (
s) outputing to two non-overlapping clock circuits of two-phase (300,400), global clock circuit (200) also produces the shielding clock signal ( of 180 ° of two phase differences
p(0),
p(180)), phase place is 180 ° shielding clock signal (
p(180)) output to the non-overlapping clock circuit of first two-phase (300), phase place is 0 shielding clock signal (
p(0)) outputs to the non-overlapping clock circuit of second two-phase (400).
2, multichannel according to claim 1 does not have the mismatch clock control device, it is characterized in that described global clock circuit forms clock input signal ( by two phase inverters (INV2, INV3), a NAND gate (NAND1) and a d type flip flop (DFF6)
IN) be connected to an input of first phase inverter (INV2) and NAND gate (NAND1), the output of first phase inverter (INV2) is connected to another input of NAND gate (NAND1), the output of NAND gate (NAND1) is connected to the input of second phase inverter (INV3), and the output of second phase inverter (INV3) is overall small-pulse effect clock signal (
IN), the input end of clock (CK) of d type flip flop (DFF6) is connected the output of first phase inverter (INV2) and the two divided-frequency clock signal ( that is come by four-phase clock circuit (100) respectively with data input pin (D)
2FP), its in-phase output end (Q) and reversed-phase output (Q
z) be respectively that phase place is 0 and 180 ° shielding clock signal (
p(0),
p(180)).
3, multichannel according to claim 2 does not have the mismatch clock control device, it is characterized in that: described four-phase clock circuit (100) is made up of 5 d type flip flops (DFF1, DFF2, DFF3, DFF4, DFF5) and a phase inverter (INV1), and the input end of clock (CK) of first d type flip flop (DFF1) meets input clock signal (
IN), reversed-phase output (Q
Z) link to each other with data input pin (D), in-phase output end (Q) is two divided-frequency clock signal (
2FP), it connects the input end of clock (CK) of four d flip-flop (DFF4) and the data input pin (D) of second d type flip flop (DFF2), and the input end of clock (CK) of second trigger (DFF2) connects input clock signal (
IN), its in-phase output end (Q) connects the input end of clock (CK) of the 5th d type flip flop (DFF5), its reversed-phase output (Q
Z) connecting the input of phase inverter (INV1), the output of phase inverter (INV1) connects the input end of clock (CK) of 3d flip-flop (DFF3), the reversed-phase output (Q of 3d flip-flop (DFF3)
Z) link to each other with data input pin (D), its in-phase output end (Q) connects the data input pin (D) of four d flip-flop (DFF4) and the 5th d type flip flop (DFF5), the in-phase output end (Q) of four d flip-flop (DFF4) and reversed-phase output (Q
Z) be respectively the four phase clock signals ( (0), (180)) of 0 and 180 ° of phase place, the in-phase output end (Q) of the 5th d type flip flop (DFF5) and reversed-phase output (Q
Z) be respectively the four phase clock signals ( (90), (270)) of 90 ° and 270 ° phase places;
The input of the non-overlapping clock circuits of described two two-phases (300,400) connects the overall small-pulse effect clock signal ( from global clock circuit (200)
s), the input of the non-overlapping clock circuit of first two-phase (300) also connects in-phase output end (Q), the reversed-phase output (Q from the four d flip-flop (DFF4) in the four-phase clock circuit (100)
Z) the four phase clock signals ( (0), (180)) of 0 and 180 ° of phase place, the input of the non-overlapping clock circuit of second two-phase (400) also connects in-phase output end (Q), the reversed-phase output (Q from the 5th d type flip flop (DFF5) in the four-phase clock circuit (100)
Z) the four phase clock signals ( (90), (270)) of 90 ° and 270 ° phase places, the non-overlapping clock circuit of first two-phase (300) phase difference output is 180 ° first and third channel sampled clock signal (
1,
3) and phase difference be 180 ° first and third channel base plate sampled clock signal (
1p,
3p), the non-overlapping clock circuit of second two-phase (400) phase difference output is 180 ° second and four-way sampled clock signal (
2,
4) and phase difference be 180 ° second and four-way base plate sampled clock signal (
2p,
4p), the output of two non-overlapping clock circuits of two-phase is formed, four sampled clock signals of 90 ° of phase place inequality and four base plate sampled clock signals of 90 °, two the non-overlapping clock circuit of two-phase structures are identical, respectively contain two element circuits, two element circuit interconnections, each element circuit knot is identical, forms by a NAND gate, seven phase inverters, two NMOS pipes and a PMOS pipe;
One of two input of the NAND gate (NAND11) of the first module circuit of the non-overlapping clock circuit of first two-phase (300) fetch 0 phase place, the four phase clock signals ( (0)) from four-phase clock circuit (100), the feedback end of another input termination second element circuit, NAND gate (NAND11) output connects the input of first phase inverter (INV11) and the grid of PMOS pipe (P11), the drain electrode of the input of output termination second phase inverter (INV12) of first phase inverter (INV11) and NMOS pipe (N11) and the input of the 6th phase inverter (INV16), the grid of NMOS pipe (N11) connects the overall small-pulse effect clock signal ( from global clock circuit (200) output
s), the source electrode of NMOS pipe (N11) connects the drain electrode of the 2nd NMOS pipe (N12), and the grid of the 2nd NMOS pipe (N12) fetches the shielding clock signal ( from 180 ° of phase places of global clock circuit (200) output
p(180)), the source ground of the 2nd NMOS pipe (N12), the input of output termination the 3rd phase inverter (INV13) of second phase inverter (INV12), the drain electrode of the input of output termination the 4th phase inverter (INV14) of the 3rd phase inverter (INV13) and PMOS pipe (P11), the source electrode of PMOS pipe (P11) connects power supply, the output of the 4th phase inverter (INV14) is the feedback end of first module circuit, it is connected to an input of the NAND gate (NAND31) of second element circuit, the output of the 4th phase inverter (INV14) is also connected to the input of the 5th phase inverter (INV15) simultaneously, the input of output termination the 7th phase inverter (INV17) of the 6th phase inverter (INV16), the output output first passage base plate sampled clock signal ( of the 7th phase inverter (INV17)
1p), the output output first passage sampled clock signal ( of the 5th phase inverter (INV15)
1);
One of two input of NAND gate (NAND31) of second element circuit of the non-overlapping clock circuit of first two-phase (300) fetch the four phase clock signals ( (180)) from 180 ° of phase places of four-phase clock circuit (100), the feedback end of another input termination first module circuit, second element circuit output third channel base plate sampled clock signal (
3p) and third channel sampled clock signal (
3);
One of two input of NAND gate (NAND21) of the first module circuit of the non-overlapping clock circuit of second two-phase (400) fetch the four phase clock signals ( (90)) from 90 ° of phase places of four-phase clock circuit (100), the feedback end of another input termination second element circuit, first module circuit output second channel base plate sampled clock signal (
2p) and second channel sampled clock signal (
2);
One of two input of NAND gate (NAND41) of second element circuit of the non-overlapping clock circuit of second two-phase (400) fetch the four phase clock signals ( (270)) from 270 ° of phase places of four-phase clock circuit (100), the feedback end of another input termination first module circuit, second element circuit is exported four-way base plate sampled clock signal (
4p) and four-way sampled clock signal (
4);
Two non-overlapping clock circuits of two-phase (300,400) produce first, second, third and the four-way base plate sampled clock signal ( that phase difference is followed successively by 90 °
1p,
2p,
3p,
4p) and phase difference be followed successively by 90 ° first, second, third and four-way channel sample clock signal (
1,
2,
3,
4).
4, multichannel according to claim 3 does not have the mismatch clock control device, it is characterized in that described in the element circuit of two non-overlapping clock circuits of two-phase NMOS pipe (N11, N31, N21, N41) and the 2nd NMOS manage the driving force of the driving force of (N12, N32,22, N42) greater than first phase inverter (INV11, INV31, INV21, INV41).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200520134182 CN2886921Y (en) | 2005-12-06 | 2005-12-06 | Multi-channel non mismatch clock control device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200520134182 CN2886921Y (en) | 2005-12-06 | 2005-12-06 | Multi-channel non mismatch clock control device |
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| Publication Number | Publication Date |
|---|---|
| CN2886921Y true CN2886921Y (en) | 2007-04-04 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1777032B (en) * | 2005-12-06 | 2010-12-08 | 东南大学 | Four-channel mismatch-free clock control circuit |
| CN105391508A (en) * | 2015-10-15 | 2016-03-09 | 盛科网络（苏州）有限公司 | Time division multiplexing architecture of quad serial gigabit media independent interface physical coding sublayer (QSGMII PCS) transmitting direction state machine, control method and control system therefor |
-
2005
- 2005-12-06 CN CN 200520134182 patent/CN2886921Y/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1777032B (en) * | 2005-12-06 | 2010-12-08 | 东南大学 | Four-channel mismatch-free clock control circuit |
| CN105391508A (en) * | 2015-10-15 | 2016-03-09 | 盛科网络（苏州）有限公司 | Time division multiplexing architecture of quad serial gigabit media independent interface physical coding sublayer (QSGMII PCS) transmitting direction state machine, control method and control system therefor |
| CN105391508B (en) * | 2015-10-15 | 2018-01-05 | 盛科网络（苏州）有限公司 | The time-multiplexed framework of QSGMII PCS sending direction state machines, its control method and system |
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