CN108809306A

CN108809306A - A kind of multi-channel high-accuracy adc circuit with mismatch error self-calibration function

Info

Publication number: CN108809306A
Application number: CN201810585152.0A
Authority: CN
Inventors: 陈珍海; 魏敬和; 何宁业; 薛颜; 于宗光; 桂江华; 周昱
Original assignee: CETC 58 Research Institute
Current assignee: CETC 58 Research Institute
Priority date: 2018-06-08
Filing date: 2018-06-08
Publication date: 2018-11-13
Anticipated expiration: 2038-06-08
Also published as: CN108809306B

Abstract

The present invention provides a kind of multi-channel high-accuracy adc circuits with mismatch error self-calibration function, belong to technical field of integrated circuits.The multi-channel high-accuracy adc circuit with mismatch error self-calibration function includes gain error compensation circuit, clock phase error compensation circuit, the positions N analog-digital converter, gain error sample circuit, clock phase error sample circuit and the control circuit in the channels M.The multi-channel high-accuracy adc circuit with mismatch error self-calibration function can be according to system accuracy and the automatic compromise selection calibration accuracy of hardware spending, and has the characteristics that low-power consumption.

Description

A kind of multi-channel high-accuracy adc circuit with mismatch error self-calibration function

Technical field

The present invention relates to technical field of integrated circuits, more particularly to a kind of multichannel with mismatch error self-calibration function High-precision adc circuit.

Background technology

Precision 14, sampling rate are more than the pipeline ADC of 100MSPS（Analog-digital converter）, it is always that all kinds of intermediate frequencies are adopted The main selection of sample system, thus applied to the electronic applications such as multi-carrier broadband wireless communication and radar reception on a large scale In.To reduce cost and improving reliability, all kinds of electronic systems become increasingly conspicuous for the demand of low-power consumption and miniaturization, to institute It is increasingly strict using the power consumption and area requirements of adc circuit.To improve the integrated level of pipeline ADC, generally use single-chip collection At the mode of multichannel adc circuit come occupied space when reducing board level system design.To realize the more of pipeline ADC circuit Channel is integrated, and used single channel pipeline ADC kernel circuitry must have some special requirement：First, the ADC kernels Must have low-power consumption and small area characteristic, otherwise, the power consumption and integrity problem that multichannel integrated belt comes are by very big restriction plate Grade system application；Secondly, which must use output port number as few as possible, and otherwise, the encapsulation brought after integrated is asked The wiring problem of the HW High Way of topic and board level system can bring very big limitation.

In addition to this, when multichannel ADC is when same chips are integrated, due to the device parameters between different chip areas There are mismatch, lead to synchronised clock and gain mismatch errors occur between multichannel ADC.Especially for High Speed High Precision ADC, The influence that clock and gain error mismatch between different channel ADC are brought can clearly, and this mismatch error is for radar There is bigger influence with system performances such as channel wireless radio multi communications.Therefore design it is a kind of can be to all kinds of mistakes between multichannel ADC Carry out self-alignment circuit with error has realistic meaning very much.

Invention content

The purpose of the present invention is to provide a kind of multi-channel high-accuracy adc circuit with mismatch error self-calibration function, To solve the problems, such as the clock and gain error mismatch of existing high-precision adc generation.

In order to solve the above technical problems, the present invention provides a kind of multi-channel high-accuracy with mismatch error self-calibration function Adc circuit, including gain error compensation circuit, clock phase error compensation circuit, the positions the N analog-digital converter in the channels M, gain mistake Quantizing circuit, clock phase error sample circuit and control circuit；The positions the N analog-digital converter in the channels M includes N moulds Number converter 1, N analog-digital converter 2 ..., N analog-digital converter M；

Wherein, M reference voltage output end mouth Vrc1, Vrc2 of the gain error compensation circuit ..., Vrc M are separately connected To N analog-digital converters 1, N analog-digital converters 2 ..., the reference voltage input port of N analog-digital converter M, the gain The M+1 reference voltage output end mouth Vrinref of error compensation circuit is connected to the benchmark of the gain error sample circuit Control source port；M output terminal of clock mouth CKc1, CKc2 of the clock phase error compensation circuit ..., CKc M difference Be connected to N analog-digital converters 1, N analog-digital converters 2 ..., the input end of clock mouth of N analog-digital converter M；

N analog-digital converters 1, N analog-digital converters 2 ..., the digital quantization code output end D1 of N analog-digital converter M, D2 ..., D M be separately connected M of the gain error sample circuit digital quantization code input terminal, the gain error quantization The calibration reference signal Vr_cal of circuit be output to N analog-digital converters 1, N analog-digital converters 2 ..., N analog-digital converters The positions K quantization code _ G of the input end of analog signal of M, the gain error sample circuit is output to the positions the K amount of the control circuit Change code _ G input terminals；

M+1 error clock output port CKout1, CKout2 of the clock phase error compensation circuit ..., CKout M M+1 input end of clock mouth of the clock phase error sample circuit, the clock phase error quantization are connected with CKinref The positions K quantization code _ CK of circuit is output to the positions K quantization code _ CK input terminals of control circuit；

M K delay code output ends of the control circuit are separately connected M K of the clock phase error compensation circuit Postpone code input terminal, M CK_Ctrl control signal output of the control circuit is separately connected the clock phase error and mends Repay M CK_Ctrl control signal input of circuit, the positions the K option code _ CK output ends and Ctrl_mode_ of the control circuit CK output ends be separately connected the clock phase error sample circuit the positions K option code _ CK input terminals and Ctrl_mode_CK it is defeated Enter end, M K compensation codes output ends of the control circuit are separately connected M K compensation of the gain error compensation circuit Code input terminal, M G_Ctrl control signal output of the control circuit are separately connected the M of the gain error compensation circuit The positions the K global adaptation code output end of a G_Ctrl control signal inputs, the control circuit connects the gain error compensation The positions the K global adaptation code input terminal of circuit, the positions the K option code _ G output ends and Ctrl_mode_G output ends of the control circuit It is separately connected the positions the K option code _ G input terminals and Ctrl_mode_G input terminals of the gain error sample circuit；

Wherein, N, M and K are arbitrary positive integer.

Optionally, the multi-channel high-accuracy adc circuit with mismatch error self-calibration function include calibration mode and Compensation model, and compensation model could be entered after calibration mode terminates；

When entering calibration mode, the multi-channel high-accuracy adc circuit with mismatch error calibration is first successively to the channels M The positions N analog-digital converters carry out error due to phase mis-match calibration, generate M groups K and postpone codes；Complete error due to phase mis-match calibration Afterwards, the multi-channel high-accuracy adc circuit with mismatch error calibration again successively carries out the positions the N analog-digital converter in the channels M Gain mismatch errors are calibrated, and K compensation codes of M groups are generated；

When entering compensation model, K delay K compensation codes of code and M groups of M groups remain unchanged, described to have mismatch error school Accurate multi-channel high-accuracy adc circuit carries out phase to the N digit mode converters in the channels M simultaneously and gain mismatch errors compensate, The gain error sample circuit and the clock phase error sample circuit are turned off to reduce power consumption.

Optionally, the clock phase error compensation circuit includes：Clock receiving circuit, clock duty cycle stabilizing circuit, Clock driver circuit, M delay circuit, M multi-phase clock generation circuit and M clock equivalent delay circuit, each deferred telegram Road, each multi-phase clock generation circuit and each clock equivalent delay circuit are corresponding one by one；

Wherein, the clock receiving circuit, the clock duty cycle stabilizing circuit and the clock driver circuit are sequentially connected, defeated Enter the input terminal that clock enters the clock driver circuit after the clock receiving circuit, the clock receiving circuit；Institute State M of clock driver circuit output clock CKin1, CKin2 ..., CKin M be respectively outputted to the input of M delay circuit The M+1 output clock CKinref at end, the clock driver circuit is output to the clock phase error sample circuit；M The control signal input of delay circuit is separately connected M CK_Ctrl control signal output of the control circuit, Ge Geyan The delay code input terminal of slow circuit is separately connected M K of the control circuit and postpones code output ends, each delay circuit when Clock output end is connected to the input end of clock of multi-phase clock generation circuit and clock equivalent delay circuit corresponding thereto simultaneously； Heterogeneous output clock CKc1, CKc2 of each multi-phase clock generation circuit ..., CKc M respectively enter the channels M the positions N modulus turn Parallel operation；Output terminal of clock CKout1, CKout2 of each clock equivalent delay circuit ..., CKout M be connected respectively to it is described M input end of clock of clock phase error sample circuit.

Optionally, the clock equivalent delay circuit includes：Multi-phase clock circuit equivalent delay unit, sampling hold circuit Equivalent delay unit, multistage sub- grade circuit equivalent delay unit and digital calibration circuit equivalent delay unit；Multistage sub- grade circuit Equivalent delay unit include the 1st grade of sub- grade circuit equivalent delay unit, the 2nd grade of sub- grade circuit equivalent delay unit ..., R grades Sub- grade circuit equivalent delay unit；

The multi-phase clock circuit equivalent delay unit, the equivalent delay unit of the sampling hold circuit, the 1st grade of sub- grade electricity The equivalent delay unit in road, the 2nd grade of sub- grade circuit equivalent delay unit ..., the R grades of sub- grade circuit equivalents delay it is single The first and described equivalent delay unit of digital calibration circuit is sequentially connected；The output terminal of clock of delay circuit is connected to corresponding more The input end of clock of phase clock circuit equivalent delay unit passes through the multi-phase clock circuit equivalent delay unit, described successively The equivalent delay unit of sampling hold circuit, the 1st grade of sub- grade circuit equivalent delay unit, the 2nd grade of sub- grade circuit equivalent Delay unit ..., it is defeated after the R grades of sub- grade circuit equivalent delay units and the equivalent delay unit of the digital calibration circuit Go out clock；

When the clock equivalent delay circuit enters calibration mode, the multi-phase clock circuit equivalent delay unit described is adopted The equivalent delay unit of sample holding circuit, multistage sub- grade circuit equivalent delay unit and the equivalent delay unit of the digital calibration circuit Normal work；When the clock equivalent delay circuit enters compensation model, the multi-phase clock circuit equivalent delay unit is adopted The equivalent delay unit of sample holding circuit, multistage sub- grade circuit equivalent delay unit and the equivalent delay unit of the digital calibration circuit It is closed；

Wherein, R is positive integer.

Optionally, the clock phase error sample circuit includes：Reference clock generation circuit, phase discriminator, loop filtering Device and K analog-digital converter circuits；

Wherein, M+1 input end of clock of phase discriminator be connected respectively to M output terminal of clock mouth CKout1, CKout2 ..., The output terminal of clock CKref of CKout M and the reference clock generation circuit；The control of the reference clock generation circuit inputs End connects the positions K option code _ CK output ends of the control circuit；The phase error signal output end Vp of the phase discriminator is connected to The input terminal of the loop filter；The output voltage Vi of the loop filter is input to the electricity of the K analog-digital converter Press input terminal；The positions K quantization code _ CK that the K analog-digital converter generates is output to the positions K quantization code _ CK of the control circuit Input port；The control circuit calibration control signal Ctrl_mode_CK output ports simultaneously be connected to the phase discriminator, The calibration control signal input mouth of the loop filter and the K analog-digital converter.

Optionally, the gain error compensation circuit includes：Reference voltage generating circuit, reference voltage remote driver circuit With M reference voltage regulating circuit；

Wherein, the reference voltage generating circuit output reference voltage is to the reference voltage remote driver circuit；The benchmark M reference voltage output end of voltage remote driver circuit is separately connected the reference voltage input of M reference voltage regulating circuit End, the M+1 reference voltage output end mouth Vrinref connect the reference voltage input of the gain error sample circuit；Respectively The control signal input of a reference voltage regulating circuit is separately connected the M G_Ctrl control signal outputs of the control circuit The compensation codes input terminal at end, each reference voltage regulating circuit is separately connected the M K compensation codes output of the control circuit End, reference voltage output end Vrc1, Vrc2 of each reference voltage regulating circuit ..., Vrc M be respectively outputted to the N in the channels M Position analog-digital converter.

Optionally, the gain error sample circuit includes calibration reference signal generation circuit and N bit digital subtraction circuits； Digital quantization code output end D1, D2 of the positions the N analog-digital converter in the channels M ..., D M be separately connected N bit digitals subtraction electricity The M+1 group digital code input terminals of the M group digital code input terminals on road, the N bit digitals subtraction circuit connect the calibration benchmark The output quantization code output end Dref of signal generating circuit；The control signal of the calibration reference signal generation circuit is connected to The positions K option code _ G output ports of the control circuit；The positions the K quantization code of the N bit digitals subtraction circuit _ G output ends connection To the positions K quantization code _ G input ports of the control circuit；The calibration control signal Ctrl_mode_G outputs of the control circuit Port connects the calibration control signal input mouth of the N bit digitals subtraction circuit and the calibration reference signal generation circuit.

Optionally, the control circuit includes：Core control circuit, option code generation circuit, adjustment code generation circuit, fortune Calculate circuit, K bit registers group _ G, K bit register group _ CK, compensation codes output register 1~compensation codes output register M, delay Code output register 1~delay code output register M and channel selection circuit；

Wherein, the input terminal of the core control circuit connects calibration activation information, the first output of the core control circuit End is connected to the control signal of the channel selection circuit, and second output terminal is connected to the control input of the computing circuit End, third output end are connected to the control signal of the option code generation circuit, and the 4th output end is connected to adjustment code and generates The control signal of circuit, the 5th output end are connected to the control signal of K bit registers group _ CK, and the 6th output end is connected to K The control signal of bit register group _ G, the 7th output end~calibration control signal of M+6 output ends generation M G_Ctrl1~ G_CtrlM, M+7 output end~the（2*M+6）Output end generates M calibration control signal CK_Ctrl1~CK_Ctrl M；Institute The data input pin for stating computing circuit receives the K bit registers group _ CK output ends and the K bit registers group _ G output ends hair The data gone out, and K error codes are generated according to the control instruction of the core control circuit, the K error codes convey simultaneously To compensation codes output register 1~compensation codes output register M and delay code output register 1~delay code output register M Data input pin, the control signal input of compensation codes output register 1~compensation codes output register M is separately connected M Calibration control signal G_Ctrl1~G_Ctrl M, the control signal of delay code output register 1~delay code output register M Input terminal is separately connected M calibration control signal CK_Ctrl1~CK_Ctrl M, and compensation codes 1~compensation codes of output register are defeated The output end for going out register M is separately connected the 1st~the M data input terminal of the channel selection circuit, delay code output deposit The output end of device 1~delay code output register M is separately connected the M+1 of the channel selection circuit~2*M data input End；The channel selection circuit exports K compensation codes or K delay codes according to the control instruction of the core control circuit；Institute It states option code generation circuit and K option codes is generated according to the control instruction of the core control circuit；The adjustment code generates electricity Road generates K global adaptation codes according to the control instruction of the core control circuit；The data of the K bit registers group _ CK are defeated Enter end and receive the positions K quantization code _ CK that the clock phase error sample circuit is sent, and according to the control of the core control circuit The data being stored in its internal register are sent to the computing circuit by system instruction；The data of the K bit registers group _ G Input terminal receives the positions K quantization code _ G that the gain error sample circuit is sent, and according to the control of the core control circuit The data being stored in its internal register are sent to the computing circuit by instruction.

Optionally, when carrying out gain mismatch errors calibration to the positions the N analog-digital converter in the channels M, the channel selection circuit The output that will carry out the corresponding compensation codes output register of the positions N analog-digital converter of gain mismatch errors calibration is opened, remaining benefit The output for repaying yard output register is closed；When carrying out the calibration of clock phase mismatch error to the positions the N analog-digital converter in the channels M, The channel selection circuit deposits the corresponding delay code output of the positions the N analog-digital converter for carrying out clock phase mismatch error calibration The output of device is opened, and the output of remaining delay code output register is closed.

Optionally, when the computing circuit generates K error codes using two points of successive approximation algorithms, each operation only changes 1 in K error codes.

A kind of multi-channel high-accuracy adc circuit with mismatch error self-calibration function is provided in the present invention, including Gain error compensation circuit, clock phase error compensation circuit, the positions the N analog-digital converter in the channels M, gain error sample circuit, Clock phase error sample circuit and control circuit.The multi-channel high-accuracy ADC electricity with mismatch error self-calibration function Road can be according to system accuracy and the automatic compromise selection calibration accuracy of hardware spending, and has the characteristics that low-power consumption.

Description of the drawings

Fig. 1 is the structural schematic diagram of the multi-channel high-accuracy adc circuit with mismatch error self-calibration function；

Fig. 2 is the structural schematic diagram of clock phase error compensation circuit；

Fig. 3 is the structural schematic diagram of clock phase error sample circuit；

Fig. 4 is the structural schematic diagram of clock driver circuit；

Fig. 5 is the structural schematic diagram of multi-phase clock generation circuit；

Fig. 6 is the structural schematic diagram of delay circuit；

Fig. 7 is the structural schematic diagram of clock equivalent delay circuit；

Fig. 8 is the structural schematic diagram of reference clock generation circuit；

Fig. 9 is the structural schematic diagram of gain error compensation circuit；

Figure 10 is the structural schematic diagram of gain error sample circuit；

Figure 11 is the structural schematic diagram of reference voltage remote driver circuit；

Figure 12 is the structural schematic diagram of reference voltage programming adjustment circuit；

Figure 13 is the structural schematic diagram for calibrating reference signal generation circuit；

Figure 14 is the structural schematic diagram of benchmark output quantization code generation circuit；

Figure 15 is the structural schematic diagram of control circuit.

Specific implementation mode

Below in conjunction with the drawings and specific embodiments to proposed by the present invention a kind of more with mismatch error self-calibration function Channel high-precision adc circuit is described in further detail.According to following explanation and claims, advantages and features of the invention It will become apparent from.It should be noted that attached drawing is all made of very simplified form and uses non-accurate ratio, only to it is convenient, Lucidly aid in illustrating the purpose of the embodiment of the present invention.

Embodiment one

The present invention provides a kind of multi-channel high-accuracy adc circuits with mismatch error self-calibration function, as shown in Figure 1.Institute It includes gain error compensation circuit, clock phase mistake to state the multi-channel high-accuracy adc circuit with mismatch error self-calibration function The positions N analog-digital converter, gain error sample circuit, clock phase error sample circuit and the control of poor compensation circuit, the channels M Circuit.The positions the N analog-digital converter in the channels M include N analog-digital converters 1, N analog-digital converters 2 ..., N moduluses turn Parallel operation M.

Wherein, M reference voltage output end mouth Vrc1, Vrc2 of the gain error compensation circuit ..., Vrc M difference Be connected to N analog-digital converters 1, N analog-digital converters 2 ..., the reference voltage input port of N analog-digital converter M；Separately Outside, the M+1 reference voltage output end mouth Vrinref of the gain error compensation circuit is connected to the gain error quantization The reference voltage input port of circuit；M output terminal of clock mouth CKc1 of the clock phase error compensation circuit, CKc2 ..., CKc M be connected respectively to N analog-digital converters 1, N analog-digital converters 2 ..., N analog-digital converter M when Clock input port.N analog-digital converters 1, N analog-digital converters 2 ..., the digital quantization code output end of N analog-digital converter M D1, D2 ..., D M be separately connected M of the gain error sample circuit digital quantization code input terminal D1, D2 ..., D M, The calibration reference signal Vr_cal of the gain error sample circuit is output to N analog-digital converters 1, N analog-digital converters 2 ... the positions K quantization code _ G of the, input end of analog signal of N analog-digital converter M, the gain error sample circuit is output to The positions K quantization code _ G input terminals of the control circuit.M+1 error clock output end of the clock phase error compensation circuit Mouthful CKout1, CKout2 ..., CKout M and CKinref be connected to M+1 clock of the clock phase error sample circuit Input port, the positions K quantization code _ CK that the positions K quantization code _ CK of the clock phase error sample circuit is output to control circuit are defeated Enter end.K delay 1 ~ M of code of M K delay code output ends of the control circuit are connected respectively to the clock phase error and mend Repay K delay 1 ~ M of code of M K delay code input terminals of circuit, M CK_Ctrl control signal output of the control circuit 1 ~ M of CK_Ctrl are connected respectively to M CK_Ctrl control signal inputs CK_ of the clock phase error compensation circuit 1 ~ M of Ctrl, when the positions the K option code _ CK output ends and Ctrl_mode_CK output ends of the control circuit are connected respectively to described Clock phase error quantifies the positions the K option code _ CK input terminals and Ctrl_mode_CK input terminals of circuit, M K of the control circuit Position K 1 ~ M of compensation codes of compensation codes output end are connected respectively to M K compensation codes input terminal K of the gain error compensation circuit 1 ~ M of compensation codes, M 1 ~ M of G_Ctrl control signal output G_Ctrl of the control circuit are connected respectively to the gain for position M G_Ctrl 1 ~ M of control signal input G_Ctrl of error compensation circuit, the positions the K global adaptation code of the control circuit are defeated Outlet is connected to the positions the K global adaptation code input terminal of the gain error compensation circuit, the positions K option code _ G of the control circuit Output end and Ctrl_mode_G output ends be connected respectively to the gain error sample circuit the positions K option code _ G input terminals and Ctrl_mode_G input terminals.Wherein, N, M and K are arbitrary positive integer.

Specifically, the multi-channel high-accuracy adc circuit with mismatch error self-calibration function include calibration mode and Two kinds of operating modes of compensation model, and can only could enter compensation model after calibration mode terminates.Into calibrating die When formula, the multi-channel high-accuracy adc circuit with mismatch error calibration is first successively to the positions the N analog-digital converter in the channels M Error due to phase mis-match calibration is carried out, K delay codes of M groups are generated；It is described that there is mismatch to miss after completing error due to phase mis-match calibration The multi-channel high-accuracy adc circuit of difference calibration carries out gain mismatch errors calibration to the positions the N analog-digital converter in the channels M successively again, Generate K compensation codes of M groups；When entering compensation model, K delay K compensation codes of code and M groups of M groups remain unchanged, the tool There is the multi-channel high-accuracy adc circuit that mismatch calibrates for error to carry out phase and gain mistake to the N digit mode converters in the channels M simultaneously With error compensation, the gain error sample circuit and the clock phase error sample circuit are turned off to reduce power consumption.

The operation principle of the above-mentioned multi-channel high-accuracy adc circuit with mismatch error self-calibration function is：Work as calibrating die When formula is opened, the control circuit controls clock phase error sample circuit by Ctrl_mode_CK signals and enters calibration first Pattern, while exporting K option code _ CK and giving clock phase error sample circuit；The multichannel with mismatch error calibration High-precision adc circuit starts to carry out error due to phase mis-match calibration to the positions the N analog-digital converter in the channels M；Control circuit then can be defeated Go out the first calibration control signal CK_Ctrl 1 and arrive clock phase error compensation circuit, proceeds by N analog-digital converter circuits 1 Error due to phase mis-match calibration.

Specifically it is illustrated in figure 2 clock phase error compensation circuit schematic diagram.The clock phase error compensation circuit Including：Clock receiving circuit, clock duty cycle stabilizing circuit, clock driver circuit, M delay circuit, M multi-phase clock generate Circuit and M clock equivalent delay circuit, each delay circuit, each multi-phase clock generation circuit and each clock equivalent delay Circuit is corresponding one by one：Delay circuit 1, multi-phase clock generation circuit 1 and clock equivalent delay circuit 1 correspond to, delay circuit 2, Multi-phase clock generation circuit 2 and clock equivalent delay circuit 2 correspond to ..., delay circuit M, multi-phase clock generation circuit M and when Clock equivalent delay circuit M is corresponded to.Wherein, the clock receiving circuit, the clock duty cycle stabilizing circuit and the clock drive Dynamic circuit is sequentially connected, and input clock enters the clock after the clock receiving circuit, the clock receiving circuit and drives The input terminal of dynamic circuit；M of clock driver circuit output clock CKin1, CKin2 ..., CKin M be connected respectively to M The input terminal of a delay circuit：Output clock CKin1 is connected to the input terminal of delay circuit 1, and output clock CKin2, which is connected to, to be prolonged The input terminal ..., output clock CKin M of slow circuit 2 are connected to the input terminal of delay circuit M.The clock driver circuit The M+1 output clock CKinref is output to the clock phase error sample circuit.The control signal of each delay circuit is defeated Enter 1 ~ M of control signal CK_Ctrl that end is separately connected the control circuit control signal output output：The control of delay circuit 1 Signal input part connection control signal CK_Ctrl1 processed, the control signal input connection control signal CK_ of delay circuit 2 The control signal input of Ctrl2 ..., delay circuit M connection control signal CK_Ctrl M.The delay code of each delay circuit Input terminal is separately connected the positions K 1 ~ M of delay code of the control circuit delay code output end output：The delay code of delay circuit 1 is defeated Enter K delay codes 1 of end connection, the delay code input terminal of delay circuit 2 connects K delay codes 2 ..., the delay of delay circuit M Code input terminal connects K delay code M.The output terminal of clock of each delay circuit is connected to multi-phase clock corresponding thereto simultaneously The input end of clock of generation circuit and clock equivalent delay circuit：When the output terminal of clock of delay circuit 1 is connected to multiphase simultaneously Clock generation circuit 1 and clock equivalent delay circuit 1, the output terminal of clock of delay circuit 2 are connected to multi-phase clock and generate electricity simultaneously Road 2 and the output terminal of clock of clock equivalent delay circuit 2 ..., delay circuit M be connected to simultaneously multi-phase clock generation circuit M and Clock equivalent delay circuit M.Heterogeneous output clock CKc1, CKc2 of each multi-phase clock generation circuit ..., CKc M respectively into Enter the positions the N analog-digital converter in the channels M：Heterogeneous output clock CKc1 enters N analog-digital converters 1, heterogeneous output clock CKc2 into Enter N analog-digital converters 2 ... heterogeneous output clock CKc M enter N analog-digital converter M.Each clock equivalent delay circuit Output terminal of clock CKout1, CKout2 ..., CKout M be connected respectively to the M of the clock phase error sample circuit Input end of clock.

It is illustrated in figure 3 the structural schematic diagram of the clock phase error sample circuit.The clock phase error quantization Circuit includes：Reference clock generation circuit, phase discriminator, loop filter and K analog-digital converter circuit.Wherein, the phase demodulation M+1 input end of clock of device be connected respectively to the M output terminal of clock mouth CKout1, CKout2 ..., CKout M and institute State the output terminal of clock CKref of reference clock generation circuit；The control signal of the reference clock generation circuit is connected to institute State the positions K option code _ CK output ends of control circuit；The phase error signal output end Vp of the phase discriminator is connected to the loop The input terminal of filter；The output voltage Vi of the loop filter is input to the voltage input end of the K analog-digital converter； The positions K quantization code _ CK of the K analog-digital converter is output to the positions K quantization code _ CK input ports of the control circuit；It is described The calibration control signal Ctrl_mode_CK output ports of control circuit are connected to the phase discriminator, the loop filter simultaneously With the calibration control signal input mouth of the K analog-digital converter.

Fig. 4 is a kind of realization method of clock driver circuit.The clock driver circuit includes that a multichannel clock produces Raw and predrive circuit and M+1 remote clock driving circuit, M+1 remote clock driving circuit are respectively：Remote clock drives Dynamic circuit 1, remote clock driving circuit 2 ..., remote clock driving circuit M and remote clock driving circuit ref.Clock duty It is input to multichannel clock generation and predrive circuit than stabilizing circuit output clock, generates M+1 road clocks and through M+1 clock Remote driver circuit obtains the roads M+1 output clock.Wherein, the roads M clock CKin1, CKin2 ..., CKin M are connected respectively to M Delay circuit：Clock CKin1 is connected to the input terminal of delay circuit 1, and clock CKin2 is connected to the input of delay circuit 2 End ..., clock CKin M are connected to the input terminal of delay circuit M.The roads M+1 clock CKinref is output to reference clock generation Circuit.The multichannel clock generates and rest-set flip-flop can be used in predrive circuit and reverser coupling is realized.The clock is remote Journey driving circuit is realized using reverser drive chain.

Clock phase calibration circuit for multichannel ADC can be used for M Channel Synchronous sampling ADCs, can be used for the channels M Time-interleaved ADC.When the present invention is used for M Channel Synchronous sampling ADCs, the multichannel clock generates and predrive circuit is produced The roads Sheng M+1 clock is the clock signal of same phase.When the present invention is used for M channel time intertexture ADC, when the multichannel The roads M clock CKin1 ~ CKin M caused by clock generation and predrive circuit are the clock signal of phase difference at equal intervals, phase difference For 360 °/M；The roads M+1 clock CKinref is identical as the clock all the way in the clock CKin1 ~ CKin M of the roads M, when for multichannel When the clock phase calibration circuit of ADC carries out the error due to phase mis-match calibration of N analog-digital converter circuit X, CKinref and CKinX phases are identical.

For production by assembly line, sub- grade circuit is the sampling and holding completed to analog input signal, needs one two Phase clock carrys out the working condition of control circuit.Fig. 5 is a kind of realization method of multi-phase clock generation circuit of the present invention.Wherein CKin The reference clock signal being an externally input, Φ 1 and Φ 2 are the two-phase disjoint signals of circuit output.Simultaneously in pipeline module In, the non-linear effects such as channel charge injection effect and the clock feed-through effect of switching tube are usually eliminated, need that auxiliary is added Clock signal, Φ 1 ' and Φ 2 ' are to eliminate auxiliary clock signal that is above-mentioned non-linear and designing.The clock circuit leads to It crosses a rest-set flip-flop to generate, non-overlapping interval time is controlled by the delay of two phase inverters.Auxiliary clock circuit is logical It crosses after non-overlapping clock signal is delayed with the signal with two phase inverters and is generated under AND gate circuit effect, can be made by AND gate circuit The rising edge alignment of two clock signals, auxiliary clock and the delay time of non-overlapping clock signal are determined by the delay size of phase inverter It is fixed.Two auxiliary clock Φ 1 ' and Φ 2 ' are respectively before corresponding original clock signal Φ 1 and Φ 2 is turned off when introducing two Shutdown.Multi-phase clock generation circuit shown in fig. 5 can be used for generating the non-overlapping clock of simple two-phase, by extend trigger and Feedback control loop can also generate 4 phases and not overlap clock.However to generate the clock of more leggy complexity, then by postponing locking phase Ring（DLL）Come generate more high stability more high phase place complexity clock signal.

Fig. 6 is delay circuit structural schematic diagram.The delay circuit includes delay cell selection decoding circuit and 2^K- 1 Numerical control delay unit.2^K- 1 numerical control delay unit be respectively numerical control delay unit 1, numerical control delay unit 2 ... numerical control be delayed Unit 2^K-1.The positions the K delay code of control circuit input enters delay cell selection decoding circuit and generates 2^K- 1 delay switch control Signal：S1, S2 ..., S2^K- 1,2^K- 1 delay switch control signal controls 2 respectively^KWhen the delay of -1 numerical control delay unit Between；CKin is connected to the input end of clock of numerical control delay unit 1, and the output terminal of clock of numerical control delay unit 1 is connected to numerical control and prolongs The input end of clock ..., numerical control delay unit 2 of Shi Danyuan 2^K- 1 clock output is CK.Described 2^K- 1 numerical control delay unit Delay remove by 2^KExcept -1 delay switch control signal control, also by calibration control signal CK_Ctrl controls.Prolong when described When slow circuit enters calibration mode, 2^KThe delay of -1 numerical control delay unit is by 2^K- 1 delay switch control signal control；Work as institute When stating delay circuit and entering compensation model, 2^KThe delay of -1 numerical control delay unit remains unchanged, not by 2^K- 1 delay switch control Signal control processed.

Specifically, Fig. 7 is the structural schematic diagram of clock equivalent delay circuit.The clock equivalent delay circuit includes：It is more Phase clock circuit equivalent delay unit, the equivalent delay unit of sampling hold circuit, multistage sub- grade circuit equivalent delay unit sum number Word calibrates circuit equivalent delay unit；Multistage sub- grade circuit equivalent delay unit include the 1st grade of sub- grade circuit equivalent delay unit, 2nd grade of sub- grade circuit equivalent delay unit ..., R grades of sub- grade circuit equivalent delay units.The multi-phase clock circuit equivalent It is delay unit, the equivalent delay unit of the sampling hold circuit, the 1st grade of sub- grade circuit equivalent delay unit, 2nd grade described Sub- grade circuit equivalent delay unit ..., the R grades of sub- grade circuit equivalent delay units and the digital calibration circuit it is equivalent Delay unit is sequentially connected；The output terminal of clock of delay circuit is connected to corresponding multi-phase clock circuit equivalent delay unit Input end of clock, successively pass through the multi-phase clock circuit equivalent delay unit, the equivalent delay unit of the sampling hold circuit, The 1st grade of sub- grade circuit equivalent delay unit, the 2nd grade of sub- grade circuit equivalent delay unit ..., the R grades of sub- grades Clock is exported after circuit equivalent delay unit and the equivalent delay unit of the digital calibration circuit.When clock equivalent delay electricity It is the multi-phase clock circuit equivalent delay unit, the equivalent delay unit of the sampling hold circuit, more when road enters calibration mode The sub- grade circuit equivalent delay unit of grade and the equivalent delay unit normal work of the digital calibration circuit；Prolong when the clock is equivalent It is the multi-phase clock circuit equivalent delay unit, the equivalent delay unit of sampling hold circuit, more when slow circuit enters compensation model The sub- grade circuit equivalent delay unit of grade and the equivalent delay unit of the digital calibration circuit are closed；Wherein, R is positive integer.

Fig. 8 is the reference clock generation circuit structure diagram.The reference clock generation circuit includes：One programmable Frequency regulating circuit and a programmable duty cycle adjustment circuit.The programmable frequency adjustment circuit and the programmable duty It is controlled by K option codes _ CK than adjustment circuit.Under the control of K option code _ CK, frequency and the fixed input of duty ratio Clock is successively after the programmable frequency adjustment circuit and the programmable duty cycle adjustment circuit, you can obtains difference The reference clock Ckref of frequency and duty ratio.

The structure of the gain error compensation circuit is as shown in Figure 9.The gain error compensation circuit includes：Reference voltage Generation circuit, reference voltage remote driver circuit and M reference voltage regulating circuit.M reference voltage regulating circuit be respectively Reference voltage regulating circuit 1, reference voltage regulating circuit 2 ..., reference voltage regulating circuit M.Wherein, the reference voltage production Raw circuit generates a reference voltage and is transported to the reference voltage remote driver circuit；The reference voltage remote driver circuit Under the control of K global adaptation codes, M reference voltage output end export M reference voltage V rin1, Vrin2 ..., Vrin M arrives the reference voltage input of M reference voltage regulating circuit respectively：Reference voltage V rin1 is delivered to reference voltage adjustment electricity Road 1, reference voltage V rin2 is delivered to reference voltage regulating circuit 2 ..., reference voltage V rin M are delivered to reference voltage adjustment Circuit M.The M+1 reference voltage output end mouth Vrinref output references voltage to the gain error sample circuit benchmark Voltage input end.It is defeated that the control signal input of each reference voltage regulating circuit is separately connected the control circuit control signal 1 ~ M of control signal G_Ctrl of outlet output：The control signal input incoming control signal G_ of reference voltage regulating circuit 1 Ctrl 1, control signal input incoming control signal G_Ctrl 2 ..., the reference voltage adjustment of reference voltage regulating circuit 2 The control signal input incoming control signal G_Ctrl M of circuit M.The compensation codes input terminal of each reference voltage regulating circuit It is respectively connected to the positions K 1 ~ M of compensation codes of the control circuit compensation codes output end output：The compensation codes of reference voltage regulating circuit 1 Input terminal inputs K compensation codes 1, and the compensation codes input terminal of reference voltage regulating circuit 2 inputs K compensation codes 2 ..., benchmark electricity The compensation codes input terminal of adjustment circuit M is pressed to input K compensation codes M.The reference voltage output end of each reference voltage regulating circuit Vrc1, Vrc2 ..., Vrc M be respectively outputted to the positions the N analog-digital converter in the channels M：The reference voltage of reference voltage regulating circuit 1 Output end Vrc1 is connected to N analog-digital converters 1, and the reference voltage output end Vrc2 of reference voltage regulating circuit 2 is connected to N The reference voltage output end Vrc M of analog-digital converter 2 ..., reference voltage regulating circuit M are connected to N analog-digital converter M.

Figure 10 is the structural schematic diagram of gain error sample circuit.The gain error sample circuit includes calibration benchmark letter Number generation circuit and N bit digital subtraction circuits.Digital quantization code output end D1, D2 of the positions the N analog-digital converter in the channels M ..., D M is connected to the M group digital code input terminals of the N bit digitals subtraction circuit, the M+1 group numbers of the N bit digitals subtraction circuit Code input terminal connects the output quantization code output end Dref of the calibration reference signal generation circuit.The calibration reference signal production The control signal of raw circuit is connected to the positions K option code _ G output ports of the control circuit；The calibration reference signal production The calibration reference signal Vr_cal that raw circuit generates is connected to the input end of analog signal of the positions the N analog-digital converter in the channels M simultaneously. The positions K quantization code _ G output ends of the N bit digitals subtraction circuit are connected to the positions K quantization code _ G input terminals of the control circuit Mouthful；The calibration control signal Ctrl_mode_G output ports of the control circuit are connected to the N bit digitals subtraction circuit and institute State the calibration control signal input mouth of calibration reference signal generation circuit.

A kind of realization method of voltage remote driver circuit on the basis of Figure 11.The reference voltage remote driver circuit includes One reference voltage programming adjustment circuit and M+1 voltage remote driver circuit.M+1 voltage remote driver circuit is respectively electricity Press remote driver circuit 1, voltage remote driver circuit 2 ..., voltage remote driver circuit M and voltage remote driver circuit ref. Bandgap voltage reference is output to M+1 voltage remote driver circuit simultaneously after entering reference voltage programming adjustment circuit.Base The output voltage of quasi- voltage-programming adjustment circuit is controlled by K global adaptation codes, and control circuit is by adjusting K global adaptation codes Realize the adjustment to the used reference voltage of all ADC channels.A kind of specific reality of voltage-programming adjustment circuit on the basis of Figure 12 Existing, structure is digital control type LDO circuit.Control signal is when setting to 0, PMOS tube M31 conductings, negative anti-due to operational amplifier Feedback acts on, reference voltage V_REFAn initial voltage is obtained through electric resistance partial pressure export V under the control of adjustment NMOS tube M30_R(0), Current mode K-bit DAC also will produce an adjustment electric current Ic to ground simultaneously, and adjustment electric current Ic flows through least significant end resistance R32 and arrives Ground can thus be superimposed the voltage of Yi ⊿ V=Ic × R32 on the resistance R32, be output to reference signal output circuit Voltage V_Rout=V_R(0)+ ⊿ V.According to electric resistance partial pressure relationship, output reference voltage signal V_RoutVariation can correspondingly be generated.Cause This, as long as K global adaptation codes of control can realize the purpose for changing output reference voltage.All bases in the embodiment of the present invention Quasi- voltage-regulating circuit is all made of circuit structure shown in Figure 12.Realization for M+1 voltage remote driver circuit can adopt It is realized with voltage follower.

Figure 13 is the calibration reference signal generation circuit structure diagram.The calibration reference signal generation circuit includes： One programmable calibration voltage generation circuit and benchmark output quantization code generation circuit.The programmable calibration voltage generation circuit Reference voltage input terminal be connected to the reference voltage V rinref of voltage remote driver circuit output, the programmable school Quasi- voltage generation circuit exports calibration reference voltage V r_cal under the control of K option codes；Benchmark output quantization code generates electricity Road output reference output quantization code Dref under the control of K option codes.The programmable calibration voltage generation circuit is using figure Circuit structure shown in 12 can be realized.Figure 14 is benchmark output quantization code generation circuit block diagram of the present invention.The benchmark output quantity Changing code generation circuit includes：ROM look-up tables, ROM and benchmark quantization code output circuit module, and by Ctrl_mode signal controls System, the benchmark output quantization code generation circuit only work in calibration mode.K option codes of input enter ROM look-up tables, obtain To ROM module, it is defeated that appropriate address is corresponded to the benchmark quantization code data stored in memory cell by ROM module for corresponding address Go out to give benchmark quantization code output circuit, benchmark quantization code output circuit to drive benchmark quantization code data Dref outputs.

It is the block diagram of the control circuit as described in Figure 15.The control circuit includes：Core control circuit, option code production Raw circuit, adjustment code generation circuit, computing circuit, K bit registers group _ G, K bit register group _ CK, compensation codes output register 1 ~compensation codes output register M, delay code output register 1~delay code output register M and channel selection circuit.Wherein, The input terminal of the core control circuit connects calibration activation information, and the first output end of the core control circuit is connected to institute The control signal of channel selection circuit is stated, second output terminal is connected to the control signal of the computing circuit, third output End is connected to the control signal of the option code generation circuit, and the control that the 4th output end is connected to adjustment code generation circuit is defeated Enter end, the 5th output end is connected to the control signal of K bit registers group _ CK, and the 6th output end is connected to K bit registers group _ G Control signal, the 7th output end~M+6 output ends generates M calibration and controls signal G_Ctrl1~G_CtrlM, M+7 Output end~the（2*M+6）Output end generates M calibration control signal CK_Ctrl1~CK_CtrlM；The number of the computing circuit The data that the K bit registers group _ CK output ends and the K bit registers group _ G output ends are sent out, and root are received according to input terminal K error codes are generated according to the control instruction of the core control circuit, the K error codes are transported to compensation codes output and post simultaneously The data input pin of storage 1~compensation codes output register M and delay code output register 1~delay code output register M, and And the control signal input of compensation codes output register 1~compensation codes output register M is separately connected M calibration control letter The control signal input of number G_Ctrl1~G_CtrlM, delay code output register 1~delay code output register M connect respectively M calibration control signal CK_Ctrl1~CK_CtrlM is met, referring specifically to Figure 15.Compensation codes 1~compensation codes of output register The output end of output register M is connected respectively to the 1st~the M data input terminal of the channel selection circuit, delay code output The output end of register 1~delay code output register M is connected respectively to M+1~2*M numbers of the channel selection circuit According to input terminal.The channel selection circuit exports K compensation codes or K delays according to the control instruction of the core control circuit Code；The option code generation circuit generates K option codes according to the control instruction of the core control circuit；The adjustment code production Raw circuit generates K global adaptation codes according to the control instruction of the core control circuit；The number of the K bit registers group _ CK The positions K quantization code _ CK that the clock phase error sample circuit is sent is received according to input terminal, and according to the core control circuit Control instruction the data being stored in its internal register are sent to the computing circuit；The K bit registers group _ G's Data input pin receives the positions K quantization code _ G that the gain error sample circuit is sent, and according to the core control circuit The data being stored in its internal register are sent to the computing circuit by control instruction.

In the circuit shown in Figure 15,1~M of calibration control signal G_Ctrl 1~M and CK_Ctrl in the calibration mode, appoints Anticipating, the moment, only there are one signal is effective.In carrying out gain mismatch errors calibration process to the positions the N in the channels M analog-digital converter, institute State channel selection circuit will carry out gain mismatch errors calibration the corresponding compensation codes output register of the positions N analog-digital converter it is defeated Go out to open, the output of remaining compensation codes output register is closed；Clock phase is carried out in the positions the N analog-digital converter to the channels M In mismatch error calibration process, the channel selection circuit will carry out the positions the N analog-digital converter of clock phase mismatch error calibration The output of corresponding delay code output register is opened, and the output of remaining delay code output register is closed.

When the computing circuit generates K error codes X using two points of successive approximation algorithms, each operation only changes K 1 in error codes X；To in the gain mismatch errors calibration process under the Y kind calibration reference voltages, K error codes need K compensation codes X cali (K) _ RY could be generated K times by wanting loop computation；Gain to the N analog-digital converter circuit X In mismatch error calibration process, due to needing to calibrate to Z alignment reference voltages, K error codes need circulating K compensation codes X cali_fin can just be obtained and remain unchanged by calculating K*Z times；To the positions the N analog-digital converter electricity in all channels M In the gain mismatch errors calibration process on road, K error codes, which need loop computation K*Z*M times just, can obtain K compensation codes X of M groups Cali_fin is simultaneously remained unchanged, to terminate the High Precision Gain mismatch error calibration circuit for multichannel ADC to the channels M The gain mismatch errors calibration process of N analog-digital converters.

The control circuit generates first group of K delay 1 cali of code (1) and first group of K option code _ CK；First group of K Position option code _ CK enters clock phase error sample circuit and generates the first reference clock CKinref (1), first group of K delay Code 1cali (1) enters clock phase error compensation circuit and to the first error clock output port CKout1；Clock phase error Sample circuit obtains phase error by comparing CKout1 and the first reference clock CKinref (1), and converted processing can obtain First group of K quantization code _ CK is simultaneously output to control circuit；Control circuit, which receives to obtain first group of K quantization code _ CK, is stored in it In internal K bit registers group _ CK；Control circuit generates second according to first group of K quantization code _ CK, using binary chop K delay 1 cali of code (2) of group.

And then, second group of K delay 1 cali of code (2) enters clock phase error compensation circuit and obtains phase delay Newer CKout1, clock phase error sample circuit is by comparing the newer CKout1 of phase and the first reference clock CKinref (1) obtains second group of K quantization code _ CK；Control circuit is according to second group of K quantization code _ CK, using binary chop Method generates K delay 1 cali of code (3) of third group.

It recycles successively, clock phase error sample circuit continues to generate K quantization code _ CK of L groups, and control circuit can use Binary chop generates K delay 1 cali of code (L+1) of L+1 groups.When control circuit generates K 1 cali of delay code of K groups (K) after, control circuit can keep K delay codes 1 constant, and N analog-digital converter circuits 1 of end calibrate for error.

And then, control circuit output X calibration control K option codes of signal CK_CtrlX and Group X, generate X base Punctual clock CKinref (X) proceeds by the error due to phase mis-match calibration of N analog-digital converter circuit X.It is described that there is mismatch to miss The multi-channel high-accuracy adc circuit of difference calibration uses and N 1 identical calibration processes of analog-digital converter circuit obtain K groups K Delay code X is simultaneously remained unchanged, and terminates the error due to phase mis-match calibration of N analog-digital converter circuit X.According to same calibration side Formula obtains K delay code M of K groups and keeps as control circuit output M calibration control signal CK_CtrlM to delay circuit M Constant, after the error due to phase mis-match calibration for terminating N analog-digital converter circuit M, control circuit can change Ctrl_mode_CK letters Number, the multi-channel high-accuracy adc circuit with mismatch error calibration completes the phase to the positions the N analog-digital converter in the channels M Mismatch error is calibrated.

And then, control circuit enters calibration mode by Ctrl_mode_G signals control gain error sample circuit, together When export K option code _ G and give gain error sample circuit, the multi-channel high-accuracy adc circuit with mismatch error calibration Start to carry out gain mismatch errors calibration to the positions the N analog-digital converter in the channels M；Control circuit output the first calibration control signal G_ Ctrl1 proceeds by the gain mismatch errors calibration of N analog-digital converter circuits 1 to gain error compensation circuit.Control circuit Then first group of K option code _ G is generated to enter gain error sample circuit and generate the first calibration reference voltage V r_cal (1)； First calibration reference voltage V r_cal (1) analog input signal as N analog-digital converters 1, make N analog-digital converters 1 into The normal analog-to-digital conversion work of row, carries out the gain mismatch errors calibration under the 1st kind of calibration reference voltage first；Control circuit after It is continuous to generate first group of K 1 cali of compensation codes (1), into gain error compensation circuit and obtain first passage reference voltage V r1 As the reference data voltage of N analog-digital converters 1, N analog-digital converters 1 obtain first group of first output quantity through analog-to-digital conversion Change code D1（1）；Gain error sample circuit is by first group of first output quantization code D1（1）It is handled to obtain first group of K amount Change code _ G and is output to control circuit；Reception is obtained the first group of K quantization code _ positions K of G storages inside it and posted by control circuit In storage group _ G；Control circuit can generate second group of K compensation codes 1 according to first group of K quantization code _ G using binary chop cali(2)。

And then, second group of K compensation codes 1cali (2) enters reference voltage regulating circuit 1 and obtains reference voltage update Vr1, N analog-digital converters 1 obtain second group of first output quantization code D1 through analog-to-digital conversion（2）；Gain error sample circuit By newer second group of first output quantization code D1（2）It is handled to obtain second group of K quantization code _ G and is output to control electricity Road；Control circuit can generate K 1 cali of compensation codes of third group according to second group of K quantization code _ G using binary chop (3)。

It recycles successively, gain error sample circuit will continue to generate K quantization code _ G of L groups, and control circuit can use two Lookup method is divided to generate K 1 cali of compensation codes (L+1) of L+1 groups.When control circuit generates K 1 cali of compensation codes (K) of K groups Afterwards, control circuit K 1 cali of compensation codes (K) of K groups can be stored in new register and be named as K 1 cali of compensation codes (K) _ R1 terminates the gain mismatch errors calibration under the 1st kind of calibration reference voltage.

Then control circuit generates K option code _ G of Y groups；K option code _ G of Y groups enter gain error sample circuit And generate Y calibration reference voltage V r_cal (Y)；Y calibrates moulds of the reference voltage V r_cal (Y) as N analog-digital converters 1 Quasi- input signal carries out the gain mismatch errors calibration under Y kind calibration reference voltages；High-precision for multichannel ADC increases Beneficial mismatch error calibration circuit will be used to be obtained with the identical mode of gain mismatch errors calibration under the 1st kind of calibration reference voltage To K 1 cali of compensation codes (K) _ RY, terminate the gain mismatch errors calibration under Y kind calibration reference voltages.It recycles successively, when High Precision Gain mismatch error calibration circuit for multichannel ADC obtains last group of K 1 cali of compensation codes (K) _ RZ, ties After gain mismatch errors calibration under beam Z kind calibration reference voltages, algorithm circuit in control circuit will be to obtained Z groups K 1 cali of compensation codes (K) _ R1~cali (K) _ RZ carries out operation, obtains final 1 cali_fin of the positions K compensation codes and keeps Constant, the gain that the High Precision Gain mismatch error calibration circuit for multichannel ADC terminates N analog-digital converter circuits 1 is lost With calibrating for error.

And then, control circuit output X calibration control signal G_CtrlX proceeds by N to gain error compensation circuit The gain mismatch errors calibration of position analog-digital converter circuit X.High Precision Gain mismatch error for multichannel ADC calibrates circuit Using obtaining K compensation codes X cali_fin with N 1 identical gain mismatch errors calibration processes of analog-digital converter circuit and protect Hold constant, the gain mismatch errors calibration of N analog-digital converter circuit X of end.According to same calibrating mode, work as control circuit M calibrations control signal G_CtrlM is exported to gain error compensation circuit, K compensation codes M cali_fin is obtained and keeps not Becoming, after the gain mismatch errors calibration for terminating N analog-digital converter circuit M, control circuit can change Ctrl_mode_G signals, The multi-channel high-accuracy adc circuit with mismatch error calibration completes the gain mismatch to the positions the N analog-digital converter in the channels M It calibrates for error；The calibration mode that High Precision Gain mismatch error for multichannel ADC calibrates circuit terminates.

In above description, N and M are arbitrary positive integer, and K is the positive integer no more than N, and X is the positive integer no more than M, L For the positive integer no more than K, Z is no more than 2^K- 1 positive integer, Y are the positive integer no more than Z.

Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims Range.

Claims

1. a kind of multi-channel high-accuracy adc circuit with mismatch error self-calibration function, which is characterized in that including gain error Compensation circuit, clock phase error compensation circuit, the channels M the positions N analog-digital converter, gain error sample circuit, clock phase Error quantization circuit and control circuit；The positions the N analog-digital converter in the channels M includes N analog-digital converters 1, N moduluses turn Parallel operation 2 ..., N analog-digital converter M；

Wherein, N, M and K are arbitrary positive integer.

2. the multi-channel high-accuracy adc circuit with mismatch error self-calibration function, feature exist as described in claim 1 In, the multi-channel high-accuracy adc circuit with mismatch error self-calibration function include calibration mode and compensation model, and Compensation model could be entered after calibration mode terminates；

3. the multi-channel high-accuracy adc circuit with mismatch error self-calibration function, feature exist as described in claim 1 In the clock phase error compensation circuit includes：Clock receiving circuit, clock duty cycle stabilizing circuit, clock driver circuit, M delay circuit, M multi-phase clock generation circuit and M clock equivalent delay circuit, when each delay circuit, each multiphase Clock generation circuit and each clock equivalent delay circuit are corresponding one by one；

4. the multi-channel high-accuracy adc circuit with mismatch error self-calibration function, feature exist as claimed in claim 3 In the clock equivalent delay circuit includes：The equivalent delay of multi-phase clock circuit equivalent delay unit, sampling hold circuit is single Member, multistage sub- grade circuit equivalent delay unit and digital calibration circuit equivalent delay unit；Multistage sub- grade circuit equivalent delay is single Member include the 1st grade of sub- grade circuit equivalent delay unit, the 2nd grade of sub- grade circuit equivalent delay unit ..., R grades of sub- grade circuits etc. Imitate delay unit；

Wherein, R is positive integer.

5. the multi-channel high-accuracy adc circuit with mismatch error self-calibration function, feature exist as described in claim 1 In the clock phase error sample circuit includes：Reference clock generation circuit, phase discriminator, loop filter and K modulus turn Converter circuit；

6. the multi-channel high-accuracy adc circuit with mismatch error self-calibration function, feature exist as described in claim 1 In the gain error compensation circuit includes：Reference voltage generating circuit, reference voltage remote driver circuit and M benchmark electricity Press adjustment circuit；

7. the multi-channel high-accuracy adc circuit with mismatch error self-calibration function, feature exist as described in claim 1 In the gain error sample circuit includes calibration reference signal generation circuit and N bit digital subtraction circuits；The positions the N mould in the channels M Digital quantization code output end D1, D2 of number converter ..., D M be separately connected the M group digital codes of the N bit digitals subtraction circuit The M+1 group digital code input terminals of input terminal, the N bit digitals subtraction circuit connect the calibration reference signal generation circuit Output quantization code output end Dref；The control signal of the calibration reference signal generation circuit is connected to the control circuit K option codes _ G output ports；The positions K quantization code _ G output ends of the N bit digitals subtraction circuit are connected to the control circuit The positions K quantization code _ G input ports；The calibration control signal Ctrl_mode_G output ports of the control circuit connect the N The calibration control signal input mouth of bit digital subtraction circuit and the calibration reference signal generation circuit.

8. the multi-channel high-accuracy adc circuit with mismatch error self-calibration function, feature exist as described in claim 1 In the control circuit includes：Core control circuit, option code generation circuit, adjustment code generation circuit, computing circuit, K post Storage group _ G, K bit register group _ CK, compensation codes output register 1~compensation codes output register M, delay code output register 1~delay code output register M and channel selection circuit；

9. the multi-channel high-accuracy adc circuit with mismatch error self-calibration function, feature exist as claimed in claim 8 In when carrying out gain mismatch errors calibration to the positions the N analog-digital converter in the channels M, the channel selection circuit will carry out gain mistake Output with the corresponding compensation codes output register of the positions N analog-digital converter to calibrate for error is opened, the output deposit of remaining compensation codes The output of device is closed；When carrying out the calibration of clock phase mismatch error to the positions the N analog-digital converter in the channels M, the channel selecting Circuit plays the output of the corresponding delay code output register of the positions the N analog-digital converter for carrying out clock phase mismatch error calibration It opens, the output of remaining delay code output register is closed.

10. the multi-channel high-accuracy adc circuit with mismatch error self-calibration function, feature exist as claimed in claim 8 In when the computing circuit generates K error codes using two points of successive approximation algorithms, each operation only changes in K error codes 1.