CN103916126A - Pipelined ADC circuit with digital correction module - Google Patents

Abstract

The invention relates to a pipelined ADC circuit with a digital correction module. In the design of a modular circuit, in order to avoid nonlinearity caused by the change of common CMOS switch-on resistance, firstly, with regard to an ADC overall structure, nine-stage pipelined units are used, the same 1.5 bit structures are adopted for all stages, and the circuit is more modular. By using the digital correction technology, the influence by non-ideal factors is lowered. Secondly, optimization design is performed on the modular circuit so as to reduce ADC errors. A single-capacitor sampling hold circuit and a gate-voltage bootstrapped switch are used, and therefore sampling linearity and accuracy are enhanced. Digital correction is achieved by using a full adder circuit so that the number of artificial circuits can be effectively reduced, and application of a digital circuit is increased. Meanwhile, ADC conversion accuracy and efficiency are enhanced, so that the influence on the circuit by errors and non-ideal features is effectively reduced.

Description

A kind of pipeline ADC circuit with figure adjustment module

Technical field

The present invention relates to a kind of pipeline ADC circuit, be specifically related to a kind of pipeline ADC circuit with figure adjustment module.

Background technology

Since the nineties in 20th century, the application of digital technology is more and more extensive.Have following reason to make digital technology more superior than traditional analogue technique: the first, insensitive due to noise and power source change etc. are disturbed, digital processing mode can reach the precision higher than simulation process mode; The second, digital signal can be preserved easily and can not produced distortion and lost integrity; The 3rd, Digital Signal Processing mode can realize more complicated Processing Algorithm eaily, is also beneficial to upgrading and the update of product; The 4th, the development of Computer-aided Design Technology makes digital technology can very convenient and effectively realize design automation; The 5th, development that the more important thing is lsi technology makes Digital Signal Processing speed more and more higher, and integrated function is more and more, and integrated level is more and more higher, realize cost more and more lower, digital integrated circuit has started to replace gradually original analog circuit.Along with the raising of arithmetic speed and the data managing capacity of microprocessor, the technology of Digital Signal Processing and theory are increasingly powerful and perfect, and digital technology is being brought into play more and more important effect.

Although digital technology has a lot of advantages, but occurring in nature is all continually varying analog quantity, discontinuous digital signal and computer is processed and transmitted, therefore after the analog quantity that analog quantity is converted into the signal of telecommunication through transducer, need become digital signal through mould/number (analog/digital) conversion, just can be input in digital system and process and control.So the quality of analog to digital converter (ADC) performance, directly affects the processing of accuracy and the follow-up digital system of converting analogue amount.ADC has become key and the bottleneck place of electronic technology development.ADC is increasing in the importance in analog IC field, and along with the raising of integrated circuit (IC) design and manufacture level, ADC is in technique, and structure, all has greatly improved in performance, but still can not meet the requirement of digital system.

The type of ADC has parallel (Flash), successive approximation (SAR), folded form (Folding), integral form, the over-sampling sigma-delta type recently growing up in addition and streamline (Pipelined) type.Pipeline ADC adopts multilevel hierarchy cascade to form, and each grade carries out the quantification of low precision, and then the Remainder of analogue quantity quantizing is delivered to next stage and carry out same conversion, thus a production line of picture.The low precision output of every one-level is combined, just obtained final high-precision digital output value.An analog sampling value will be passed through N level from being input to output, but all in all, because every one-level of pipeline organization all has sampling hold circuit, so at different levels can concurrent working, like this, at one time in, all levels is all processed different sampled values at the same time, thereby the speed of sampling just equals the speed of final digital quantization code conversion, has improved conversion efficiency.

In the situation that circuit precision allows, if improve the resolution of pipeline ADC, only need the more sub level of cascade.But actual central due to gain error, comparator imbalance, the reasons such as amplifier finite gain, the precision of pipeline ADC can be restricted.

In pipeline ADC, non-ideal characteristic and error are the factors that must consider, need improve by the optimization of structure the performance of actual pipeline ADC, reduce the impact of error and non-ideal characteristic.Main source of error in pipeline ADC comprises, switch is non-linear, comparator imbalance, amplifier non-ideal characteristic: comprise that limited gain error, imbalance etc., capacitance mismatch error, these factors can bring MDAC gain error, also there is the impact of the non-ideal factor such as thermal noise, clock feedthrough, make imperfectization of pipeline ADC transmission characteristic.

The present application one, to streamline adc circuit, can effectively reduce analog circuit, improves the application of digital circuit, improves ADC conversion accuracy and efficiency simultaneously, and comprises figure adjustment module, can effectively reduce error and the impact of non-ideal characteristic on circuit.

The content of invention

To achieve these goals, the present invention adopts following technical scheme:

There is a pipeline ADC circuit for figure adjustment module, comprise sampling hold circuit (S/H), 9 grades of flowing water cell processing modules, clock generation circuit module, delay process module and figure adjustment modules.

This maintenance sample circuit adopts upset around formula circuit structure, and whole circuit is in sampling phase and keep only using mutually an electric capacity;

These 9 grades of flowing water cell processing modules are for being converted to the digital signal of 10 by the analog signal of sampling;

This clock generation circuit module is for generation of 2 phase non-overlapping clock signals;

This delay process module is for aliging the digital signal of 9 pipelined units outputs;

This figure adjustment module has been added correction for the folded position of numeral output to each unit.

Pipeline ADC circuit as above, is further characterized in that: the realization of this figure adjustment module is to complete by 2 adder cascades with carry function.

Pipeline ADC circuit as above, is further characterized in that: this maintenance sample circuit also comprises a bootstrapped switch.

Brief description of the drawings

Fig. 1, the pipeline ADC integrated circuit schematic diagram the present invention relates to

Fig. 2, the 9 grade of 10 bit stream water unit the present invention relates to are processed structure chart

The sampling hold circuit schematic diagram of Fig. 3, the pipeline ADC that the present invention relates to

Bootstrap switch circuit schematic diagram in Fig. 3-A, sampling hold circuit

Current transmission device circuit diagram in Fig. 3-B, sampling hold circuit

The buffer circuits schematic diagram that in Fig. 3-C, sampling hold circuit, current transmission device forms

Fig. 4, the CLK modular circuit schematic diagram the present invention relates to

Fig. 5, the time delay module circuit diagram the present invention relates to

Fig. 6, the figure adjustment modular algorithm schematic diagram the present invention relates to

Fig. 7, the figure adjustment modular structure the present invention relates to

Fig. 8, the figure adjustment modular circuit schematic diagram the present invention relates to

Adder circuit and truth table schematic diagram in Fig. 9, the figure adjustment modular circuit that the present invention relates to

Embodiment

The pipeline ADC the present invention relates to adopts the pipeline ADC under 0.6 μ mBiCMOS technique, and pipeline ADC system adopts 2.5V power supply, and the input range of analog signal is-1V-1V that switching rate is 2M/s.This pipeline ADC comprises that sampling hold circuit, 9 grade of 10 bit stream water unit processing module, external clock produce circuit module and time delay and digital correction circuit module.

The design of integer electro-circuit of system as shown in Figure 1.Input analog amount VIN is by sampling hold circuit (S/H), through 9 level production line cell processing, the two digits output of every grade of unit is through time delay module (DELAY) in time after " alignment ", parallel input figure adjustment module (Digital Correction), produces 10 pipeline ADC output D9-D0.Wherein, outside 4MHz clock CLK-IN produces the non-overlapping clock output of 4 phase 2MHz by non-overlapping clock generation module (CLK-GEN), CLK1 and CLK2 keep driving clock as samplings at different levels, CLK11 and CLK22 be as each stages of digital output latch clock, and drive as the clock of delay circuit (DELAY).The adjacent two-stage of pipeline ADC will adopt the clock signal of single spin-echo to drive, being operated in of the each units alternately of guarantee sampled and the output maintenance stage like this, for example: when first order unit output residual signal, unit, the second level must operate at sample phase, the simulation output OUT1 of the sampling first order.The working method of pipeline system is just accomplished like this.An analog input value is from entering pipeline ADC, to drawing corresponding digital quantity, and must be through the time in 5 cycles, but because every one-level of streamline is being worked simultaneously, process the signal of different time, therefore, streamline numeral output speed is the same with sampling rate, is 2Mps.

The physical circuit of modules and to complete function as follows:

1, sampling hold circuit

The application uses the sampling hold circuit of amplifier for core composition, adopts upset around formula circuit structure, and whole circuit is being sampled mutually and kept only using an electric capacity mutually the problem that does not therefore exist electric capacity to mate.Contrast electric charge distribute type sampling hold circuit, upset is 1 around the ideal feedback coefficient of formula sampling hold circuit, is 2 times of electric charge distribute type sampling hold circuit, the requirement of the gain bandwidth to amplifier has simultaneously reduced by 50%.

As shown in Figure 3, circuit working principle is sampling hold circuit overall structure: two reverse clocks drive sampling hold circuit, and when CLK2 is high, circuit is in sampling phase, and when CLK1 is high, circuit is keeping phase.Connect in sampling phase switch S 1 and S3, S2 disconnects, and amplifier is resetted, and input voltage is sampled capacitor C two ends, and due to input and output short circuit, offset voltage has been stored on sampling capacitance, thereby has eliminated the impact of offset voltage.Keeping only having mutually switch S 2 to connect, by the feedback loop of amplifier, the sample voltage value of output C, and till being held sampling mutually next time.Owing to not there is not electric capacity coupling, the impact of noise is mainly considered in the optimization of sampling capacitance.

Wherein, switch S 1 is different from another two switches, and S2 and S3 are common cmos switches.Because S1 is the entrance of whole pipeline ADC input analog voltage, what therefore its switching characteristic showed is particularly important, the application adopts bootstrapping grid voltage switch, is in order to reduce the variation of switch S 1 conducting resistance with input voltage, namely reduces the nonlinear distortion of switch S 1.KG module is bootstrapped switch, and cmos switch mould is SCH module, and OP is operational amplifier.

(1) bootstrapped switch

Conventionally in circuit, adopt cmos switch, but the physical characteristic of metal-oxide-semiconductor has determined that it is not a desirable switch, the conducting resistance of metal-oxide-semiconductor is subject to the impact of its gate source voltage, and it is all the more so in sampling hold circuit, because in the sampling hold circuit of pipeline ADC, be input as analog signal, and be added in the sampled clock signal of cmos switch tube grid, in the time of switch conduction, grid voltage is constant high level, therefore the gate source voltage of CMOS pipe changes along with the variation of input signal, and then affects the variation of conducting resistance.Make switch introduce nonlinearity erron, have harmonic distortion by the input signal of metal-oxide-semiconductor.And for sampling hold circuit, this error is unallowed, produce at the very start error otherwise can input ADC in analog signal, make the precision of subsequent conditioning circuit all become nonsensical.Bootstrapped switch is that the electric capacity charging by handle is connected with input signal, provides grid voltage to metal-oxide-semiconductor, and the gate source voltage difference of metal-oxide-semiconductor is just the magnitude of voltage on electric capacity like this, and this voltage is certain value, has solved the nonlinear problem of switching tube.

Physical circuit operation principle is as Fig. 3-A, and M7 and M8 are basic cmos switch pipes, carry out the transmission of control inputs output voltage.The two-part structure up and down of circuit is the same, upper partial circuit driving N switching tube M7, and lower partial circuit drives P switching tube M8, and sampling clock is CLK, and keeping clock is its inversion signal XCLK.From the first half, capacitor C 1 two ends are connected respectively with the grid of input Vin and M7 by transmission gate switch, and in the maintenance stage, CLK is that 0, M3 connects, and the grid of M7 connects negative supply by M3, ensures that switching tube is in stable the closing of maintenance stage.Transmission gate A1 and A2 close, and capacitor C 1 one end meets negative supply V by M1 _ss, the other end is received common mode electrical level V by M2 _cm, electric capacity is charged, and after charging, C1 both end voltage is V _cm-V _ss; In sample phase, CLK is 1, transmission gate A1, and A2 connects, and M1, M2, M3 disconnect.Input Vin connects with C1, receives M7 grid by A1, and M7 grid voltage is V like this _in+ V _cm-V _ss, realized grid voltage along with input voltage changes and floats.

V _gs,m7＝V _in+V _cm-V _ss-V _in＝V _cm-V _ss (4.1)

The gate source voltage of M7 is Vcm-Vss, and this is a definite value, thereby has solved the nonlinear distortion of switch.The latter half circuit is same principle, sample phase, and the grid step voltage of M8 is V _in+ V _cm-V _dD.

V _gs,m8＝V _in+V _cm-V _DD-V _in＝V _cm-V _DD (4.2)

Pipeline ADC use ± 2.5V the power supply of the application's design, V _cm=0, can find out, in sample phase, M7 and M8 remain conducting state, and gate source voltage is constant, conducting resistance is constant.

(2) current transmission device

In 1.5 pipeline ADC system configurations that relate in the application, the signal demand of inputting every primary unit drives SubADC and MDAC circuit, in order to improve input signal driving force, add buffer at the input of every primary unit, realized by current transmission device.

Formula 4-3 is second generation current transmission device (Current Conveyor II) circuit, is 3 end current-mode devices, and X and Y are input, and Z is output.Current transmission device characteristic is: Y port is voltage input end, ideally impedance infinity, and port input current is zero; X port is current input terminal, and ideally input impedance infinitesimal is followed Y port voltage; The electric current of X port is followed in the electric current output of Z port.Be expressed in matrix as:

$\left(\begin{array}{c}{I}_y\\ V_x\\ I_z\end{array}\right)=\left(\begin{array}{ccc}0& 0& 0\\ a_v& 0& 0\\ 0& a_i& 0\end{array}\right)\·\left(\begin{array}{c}{V}_y\\ I_x\\ V_z\end{array}\right)---\left(4.3\right)$

Wherein a _v=1-ε _v, a _i=1-ε _i, ε _vand ε _irepresent respectively the error that voltage and current is followed the trail of.Ideally, error is that 0, X terminal voltage is equal to Y terminal voltage, and Z end electric current is also equal to X end electric current.In side circuit, can there is certain error.

As shown in Fig. 3-B, the output current reaction type CCII circuit that the application's current transmission device adopts amplifier to form, its operation principle is: transistor M4-M8 and M10, and M11 has formed an operational amplifier, and M5 grid is amplifier negative terminal, M6 grid is amplifier anode, X is amplifier output, is also the negative input end of amplifier simultaneously, forms like this voltage-voltage negative feedback, make X end input impedance reduction be approximately zero, X terminal voltage and accurately follow Y terminal voltage.Flow through the electric current of M10 and M11 and flow through M12, the electric current of M13 is identical, and therefore Z end has copied the electric current of X end.M9 and C1 are as frequency compensation.M1-M3 provides bias voltage for circuit.The way of realization of this CCII circuit is having good performance aspect noise, the linearity and voltage follow precision.

In the pipeline ADC that the application relates to, current transmission device is used as voltage buffer, connects into the structure of Fig. 3-C.The Y end of high impedance is as input, and low-impedance X port voltage is followed Y port voltage, has very strong driving force, exports as buffer.Connect X end and Z end by electric capacity, make the faster of output voltage stabilization, and can reduce noise jamming.

2,9 grade of 10 bit stream water unit processing module

Fig. 2 is the structure chart of 10 bit stream line system levels.In each stage pipeline structure of reality, no longer include independent sampling and keep module, whole pipeline ADC only has independent sampling to keep module S/H at input end of analog signal.Analog signal, through the sampling of sampling hold circuit, is input in first order pipelined units, and the two digits amount of quantification is input in time delay module, and Remainder of analogue quantity outputs to the second level and processes, the like.Whole circuit is worked under the driving of the non-overlapping clock of two-phase, the clock signal of being inputted by outside, by non-overlapping clock-generating circuit module, produce non-overlapping clock, control alternations between sampling and quantification at different levels, control delay circuit 2 bit digital output " alignment " in time at different levels simultaneously, the digital signal of 18 is delivered to figure adjustment module and fold the figure adjustment that position is added, finally obtain the digital quantity of 10.

3, external clock produces circuit module

Non-overlapping clock produces circuit and produces 2 phase non-overlapping clock signal CLK1 by external clock, CLK2, to drive units alternatelies at different levels to be operated in sampling and hold period, worked in each unit simultaneously, the non-overlapping clock that therefore produces two-phase is the basic place of realizing " streamline ".

CLK modular circuit as shown in Figure 4.By an external clock input, produce the clock signal output of two single spin-echos.Its principle is to produce the nonoverlapping clock signal of two-phase by a rest-set flip-flop.The output A of the NOR gate in upper and lower two-way and two inverters thereafter, B cross-couplings is to the input of NOR gate, form a rest-set flip-flop, CLK input is equivalent to set end S, input is equivalent to reset terminal R, A point is exactly the end of rest-set flip-flop so, B point is exactly the Q end of rest-set flip-flop, the signal that A is ordered is like this contrary with CLK, and B point signal is identical with CLK, and this has just realized the generation of the non-overlapping clock of two-phase, from A, B holds output to add respectively two inverters, is in order to improve conversion speed, to clock signal shaping.

4, time delay and digital correction circuit module

Delay circuit: delay circuit is for the output digit signals of 9 pipelined units is alignd.Because in the time that the analog signal of a sampling enters pipeline ADC system, this analog signal is always first processed in first order unit, thereby the output of generation numeral at first, the 9th grade is the unit of finally processing this analog sampling value, numeral output is also last, and the output of adjacent cells numeral differs half period.This numeral output of 18 of 9 grades will be alignd in time, just can deliver to the figure adjustment unit of next stage and process and final output.

Time delay alignment is to realize by the cascade of upper edge d type flip flop, and the numeral output of every primary unit is by the time delay of the d type flip flop of varying number, Zhongdao output.Each d type flip flop can be thought a register, brings in the typing of controlling data by CP.Circuit as shown in Figure 5, d type flip flop quantity digital output channel from first order unit to afterbody unit reduces successively, the d type flip flop of every a line is all controlled by an identical clock, the clock of adjacent lines is all anti-phase, odd-numbered line clock is CLK1, even number line clock is CLK2, phase phasic difference half period.

Digital correction circuit: digital correction circuit has been added correction to the folded position of numeral output of each unit., there are 18 outputs 9 level production line unit, and through figure adjustment, folded position is added and obtains 10 final bit digital outputs.

In view of the impact of the non-ideal factor analyzed above, the design's single-stage streamline adopts .5 bit architecture, but the output that the problem of simultaneously bringing is exactly ADC can not be as ideal situation, and every grade of shifter-adder obtains.But need to adopt other algorithm to combine output at different levels, draw correct ADC digital quantity.Figure adjustment technology that Here it is.According to the .5 position pipelined units principle of practical application, carry out computational analysis.Can draw the specific implementation form of exporting to carry out figure adjustment according to the numeral of every one-level.

Calculate the ADC alignment technique of positive input scope below, the ADC figure adjustment technical logic of positive and negative input range is the same with it.

The analog input of i level is

$V_{\mathrm{in}}\left(i\right)=V_{\mathrm{dac}}\left(i\right)+\frac{V_{\mathrm{out}}\left(i\right)}{2^{B-1}}---\left(3.15\right)$

Again because the output of i level is the input of i+1 level

$V_{\mathrm{in}}\left(i\right)=V_{\mathrm{dac}}\left(i\right)+\frac{V_{\mathrm{in}}(i+1)}{2^{B-1}}---\left(3.16\right)$

Recycled 3.15 formulas, obtain the first order and input the expression formula of namely ADC analog input

$\begin{array}{c}{V}_{\mathrm{in}}\left(1\right)=V_{\mathrm{dac}}\left(1\right)+\frac{V_{\mathrm{in}}\left(2\right)}{2^{B-1}}\\ =V_{\mathrm{dac}}\left(1\right)+\frac{V_{\mathrm{dac}}\left(2\right)}{2^{B-1}}+\frac{V_{\mathrm{dac}}\left(3\right)}{2^{2(B-1)}}+\·\·\·+\frac{V_{\mathrm{dac}}\left(i\right)}{2^{(i-1)(B-1)}}+\·\·\·+\frac{V_{\mathrm{dac}}\left(N\right)}{2^{(N-1)(B-1)}}+\frac{V_{\mathrm{out}}\left(N\right)}{2^{N(B-1)}}---\left(3.17\right)\end{array}$

Wherein, last being similarly the value of afterbody surplus equivalence to first order input, is whole ADC quantization error, is designated as V _res.

The SubADC of i level is output as D _i(binary system).

D _i＝(b _B-1b _B-2···b ₁b ₀) (3.18)

Decimally be expressed as

$D_{\mathrm{out}}\left(i\right)=\underset{j=0}{\overset{B-1}{\mathrm{\Σ}}}{b}_{i,j}\·2^j---\left(3.19\right)$

The output analog voltage of i level SubDAC is

$V_{\mathrm{dac}}\left(i\right)=D_{\mathrm{out}}\left(i\right)\·\frac{\mathrm{FS}}{2^B}---\left(3.20\right)$

So 3.20 substitutions 3.17

$V_{\mathrm{in}}\left(1\right)\begin{array}{c}=\underset{i=1}{\overset{N}{\mathrm{\Σ}}}[\frac{\mathrm{FS}}{2^B}\·\frac{D_{\mathrm{out}}\left(i\right)}{2^{(i-1)(B-1)}}]+\frac{V_{\mathrm{out}}\left(N\right)}{2^{N(B-1)}}\\ =\underset{i=1}{\overset{N}{\mathrm{\Σ}}}[D_{\mathrm{out}}\left(i\right)\·\frac{\mathrm{FS}}{2^{\mathrm{iB}-i+1}}]+V_{\mathrm{res}}\end{array}---\left(3.21\right)$

The maximum of quantization error:

$\max V_{\mathrm{res}}=\frac{\mathrm{FS}}{2^{\mathrm{NB}}}---\left(3.22\right)$

Therefore 3.21 formulas are deformed into

$V_{\mathrm{in}}\left(1\right)=\underset{i=1}{\overset{N}{\mathrm{\Σ}}}[D_{\mathrm{out}}\left(i\right)\·2^{(N-i)(B-1)}]\·\frac{\mathrm{FS}}{2^{\mathrm{NB}-N+1}}+V_{\mathrm{res}}---\left(3.23\right)$

In 3.23 formulas, note A _outfor

$A_{\mathrm{out}}=\underset{i=1}{\overset{N}{\mathrm{\Σ}}}[D_{\mathrm{out}}\left(i\right)\·2^{(N-i)(B-1)}]---\left(3.24\right)$

Suppose A _outbe exactly the numeral output D of whole ADC _out, the figure place that folded position, each level production line unit is added the total ADC obtaining so should be NB-N+1, and least significant bit is

$1\mathrm{LSB}=\frac{\mathrm{FS}}{2^{\mathrm{NB}-N+1}}---\left(3.25\right)$

Therefore the analog quantity of inputting ADC should be expressed as:

$V_{\mathrm{in}}\left(1\right)=A_{\mathrm{out}}\·\frac{\mathrm{FS}}{2^{\mathrm{NB}-N+1}}+V_{\mathrm{res}}---\left(3.26\right)$

The application ± 10 pipeline ADCs of 1.5/grade of 1V input range.9 level production line unit, the folded position of two digits output of adjacent level is added, and carries out numeral and revises, and obtains 10 final position digital signals.

The realization of figure adjustment module as shown in Figure 6, is to complete by 2 adder cascades with carry function.As shown in Figure 7, due to from the first order to afterbody, numeral is exported big-endian adder from low level to high-order carry, the output of every grade shifter-adder successively, i.e. 0 and 1 addition of subordinate at the corresponding levels.0 of 1 of the first order and afterbody does not need to add computing, but for the unification of signal lag, thus they respectively with 0 addition.

As shown in Figure 8, ADDER module is adder circuit to circuit, completes two binary addition functions.B11-B90 is 18 output valves of time delay module.Use 10 adder cascades, the folded position of two digits output of each unit is added, be that the low level of this unit and a high position for next unit are added, the like, the low level of the 9th grade of unit is exactly the least significant digit amount of final pipeline ADC, but for 10 bit digital quantity have identical time delay, it and numeral 0 are added.A high position for the first order is added with 0 equally.Through figure adjustment, obtain the final 10 bit digital output D9-D0 of pipeline ADC like this.

Wherein adder as shown in Figure 9, I1, I2 is respectively the input of addend and summand, CI end for low level carry input, C-out be carry output (being designated as CO), D for entirely add with.The logical relation that can draw input and output from truth table is $D=I1\·\stackrel{\‾}{\mathrm{CO}}+I2\·\stackrel{\‾}{\mathrm{CO}}+\mathrm{CI}\·\stackrel{\‾}{\mathrm{CO}}+I1\·I2\·\mathrm{CI},$ CO=I1·I2+CI·I2+CI·I1。

The sort circuit design of the present application can be optimized the design of modular circuit, the speed of raising analog to digital converter, adopts digital self calibration technology further to improve the linearity and the precision of ADC simultaneously.

Claims (3)

1. a pipeline ADC circuit that has figure adjustment module, comprises sampling hold circuit, 9 grades of flowing water cell processing modules, and clock generation circuit module, delay process module and figure adjustment module, is characterized in that:

This maintenance sample circuit adopts upset around formula circuit structure, and whole circuit is in sampling phase and keep only using mutually an electric capacity;

These 9 grades of flowing water cell processing modules are for being converted to the digital signal of 10 by the analog signal of sampling;

This clock generation circuit module is for generation of 2 phase non-overlapping clock signals;

This delay process module is for aliging the digital signal of 9 pipelined units outputs;

This figure adjustment module has been added correction for the folded position of numeral output to each unit.

2. pipeline ADC circuit as claimed in claim 1, is further characterized in that: the realization of this figure adjustment module is to complete by 2 adder cascades with carry function.

3. pipeline ADC circuit as claimed in claim 1, is further characterized in that: this maintenance sample circuit also comprises a bootstrapped switch.