CN104467857B - Gradually-appoximant analog-digital converter system - Google Patents

Gradually-appoximant analog-digital converter system Download PDF

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CN104467857B
CN104467857B CN201410837097.1A CN201410837097A CN104467857B CN 104467857 B CN104467857 B CN 104467857B CN 201410837097 A CN201410837097 A CN 201410837097A CN 104467857 B CN104467857 B CN 104467857B
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appoximant
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CN104467857A (en
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姚兵兵
刘力源
刘剑
吴南健
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Institute of Semiconductors of CAS
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Abstract

The invention provides a kind of gradually-appoximant analog-digital converter system.In the gradually-appoximant analog-digital converter system, analog-digital converter array uses packet design, and using the method for estimation of chain circulation, the capacitance mismatch of single-channel SAR ADC in itself can be eliminated, the non-ideal factors such as gain mismatch and offset voltage mismatch between SAR ADC arrays introduce non-linear, the calibration of completion analog-digital converter array that can be rapidly and efficiently, greatly reduces design complexities and reduces power consumption.

Description

Gradually-appoximant analog-digital converter system
Technical field
The present invention relates to electronics industry technical field of electronic components, more particularly to a kind of gradually-appoximant analog-digital converter (SAR ADC) system.
Background technology
Analog-digital converter is analog circuit and the interface circuit of digital circuit in signal processing.Wherein SAR ADC because Reduced to be suitable for process, it is simple in construction, it is structure very popular in recent years.In the sensor array of medium accuracy In, therefore it is also widely applied.
But in array analog-digital converter, mismatch result in serious non-linear.Except single-pass caused by capacitance mismatch Non-linear, the gain mismatch between passage, offset voltage mismatch etc. of road analog-digital converter in itself, further limits battle array The linearity of column analog-to-digital converter.
In recent years, the SARADC that is introduced as calibrating of redundancy concept and LMS wave filters provides new thinking, corresponding auxiliary Help under the support of circuit, these technologies are applied in single channel and time-interleaved SAR ADC calibration.
The content of the invention
(1) technical problems to be solved
In view of above-mentioned technical problem, the invention provides a kind of gradually-appoximant analog-digital converter system, to eliminate single channel The non-ideal factor such as the capacitance mismatch of SAR ADC, gain mismatch and offset voltage mismatch between SAR ADC arrays in itself introduces It is non-linear.
(2) technical scheme
Gradually-appoximant analog-digital converter system of the present invention includes：Register cell, for storing mismatch parameter matrix, its In, the mismatch parameter matrix is 2 × Z matrix；Gradually-appoximant analog-digital converter array, it includes 2Z analog-digital converter, should 2Z analog-digital converter is divided into two group-group M and group N, and every group includes Z analog-digital converter, wherein, two adjacent analog-digital converters Adhere to different groups separately, same group of analog-digital converter uses identical capacitor design, and the analog-digital converter of difference group is using different Capacitor design, within a signal period, each analog-digital converter in gradually-appoximant analog-digital converter array difference Initial quantization is carried out to input analog signal, obtains 0-1 code vectors；And LMS wave filter groups, it is connected to the Approach by inchmeal mould Number converter array and register cell, it performs following operation in the signal period, to the mismatch parameter in register Each element of matrix is updated：The 0-1 code vectors of the two adjacent analog-digital converter for belonging to different groups outputs are received successively, The estimation of parameter vector corresponding to two analog-digital converter in mismatch parameter matrix is completed, after the signal period has been performed, Complete the once estimation and renewal to mismatch parameter matrix.Wherein, the modulus in the gradually-appoximant analog-digital converter array turns Parallel operation is gradually-appoximant analog-digital converter.
(3) beneficial effect
In gradually-appoximant analog-digital converter system of the present invention, analog-digital converter array uses packet design, and uses chain type The method of estimation of circulation, the calibration of completion analog-digital converter array that can be rapidly and efficiently, greatly reduces design complexities simultaneously Reduce power consumption.
Brief description of the drawings
Fig. 1 is the structural representation according to gradually-appoximant analog-digital converter system of the embodiment of the present invention；
Fig. 2 is that an analog-digital converter shows in analog-digital converter array in the present embodiment gradually-appoximant analog-digital converter system It is intended to；
Fig. 3 is the schematic diagram that LMS wave filter groups carry out mismatch parameter correction in Fig. 1 gradually-appoximant analog-digital converter systems；
Fig. 4 is the flow chart that LMS wave filters carry out mismatch parameter correction.
Embodiment
For the object, technical solutions and advantages of the present invention are more clearly understood, below in conjunction with specific embodiment, and reference Accompanying drawing, the present invention is described in more detail.It should be noted that in accompanying drawing or specification description, similar or identical portion Divide and all use identical figure number.The implementation for not illustrating or describing in accompanying drawing, it is those of ordinary skill in art Known form.In addition, though the demonstration of the parameter comprising particular value can be provided herein, it is to be understood that parameter is without definite etc. In corresponding value, but can be similar to be worth accordingly in acceptable error margin or design constraint.Mentioned in embodiment Direction term, such as " on ", " under ", "front", "rear", "left", "right" etc., only it is the direction of refer to the attached drawing.Therefore, the side used Protection scope of the present invention is intended to be illustrative and not intended to limit to term.
In gradually-appoximant analog-digital converter system of the present invention, analog-digital converter array uses packet design, is followed using chain type The method of estimation of ring carries out the calibration of analog-digital converter array.Specifically：
(1) capacitor array in analog-digital converter array in analog-digital converter：C=(CMSB, CMSB-1... C2, C1, C0) Meet following condition：
1st, for i ∈ { 1,2 ..., MSB-1, MSB }, meet
2、
3rd, MSB ＞ log2c
Wherein, formula 1 is the adequate condition that analog-digital converter has good differential nonlinearity (DNL).CiRepresent i-th of electric capacity Capacitance, c is the electric capacity gross area (size), is given in design with reference to indexs such as the noises of system.
In theory, different solutions is had to capacitor array C based on formula 1, formula 2, the constraints of formula 3, and based on each solution The capacitor array of design has identical resolution ratio.
Analog-digital converter array is referred to using packet design：In analog-digital converter array, identical group of analog-digital converter Capacitor array designed using identical C, difference group is designed using different C.
(2) calibration that analog-digital converter array is carried out using the method for estimation of chain circulation is referred to：By different groups of modulus Converter sampling quantifies the output result of identical input signal, inputs LMS (least mean square) wave filter group, chain type The mismatch parameter of circulation estimation analog-digital converter array；When mismatch parameter converges to certain precision, calibration terminates.
Gradually-appoximant analog-digital converter system of the present invention is described in detail using multiple embodiments below.
In one exemplary embodiment of the present invention, there is provided a kind of gradually-appoximant analog-digital converter system.Fig. 1 is root According to the structural representation of gradually-appoximant analog-digital converter system of the embodiment of the present invention.As shown in figure 1, the present embodiment Approach by inchmeal mould Number converter system includes：Register cell, gradually-appoximant analog-digital converter (SARADC) array, LMS wave filter groups and output Circuit and control module.
Each part of the present embodiment gradually-appoximant analog-digital converter system is described in detail individually below.
Fig. 1 is refer to, gradually-appoximant analog-digital converter (SAR ADC) array, it includes 4 analog-digital converters, 4 moulds Number converter is divided into two group-group M and group N, and every group includes 2 analog-digital converters.4 analog-digital converters are labeled respectively For：ADC-M0、ADC-N0、ADC-M1、ADC-N1。
Wherein, the analog-digital converter in same group uses identical capacitor design, i.e., is designed using identical DAC.One In the individual signal period, each analog-digital converter in gradually-appoximant analog-digital converter (SAR ADC) array is respectively to input Analog signal carries out initial quantization, obtains 0-1 code vectors.
Fig. 2 is that an analog-digital converter shows in analog-digital converter array in the present embodiment gradually-appoximant analog-digital converter system It is intended to.As shown in Fig. 2 the analog-digital converter includes：
DAC electric capacity sequences, analog signal is sampled as sampling hold circuit in ADC sample phase, gradually The suitable datum of stage offer is approached to complete the quantization of analog signal；
Switching network, entering during Approach by inchmeal is controlled by controlling the connected mode of electric capacity in DAC electric capacity sequences Journey；
Comparator, the rear end of DAC capacitor arrays is connected to, for completing relatively and to obtain binary system output knot every time Fruit (" 0 " or " 1 ")；
Output control circuit, for controlling analog-digital converter to work exactly in order.
Fig. 2 is refer to, if MSB=6.As described previously for group M and group N, same group of analog-digital converter uses identical Capacitor design, the analog-digital converter of difference group use different capacitor designs.
For each analog-digital converter in group M, it includes 7 electric capacity.Situation using LSB bit electric capacity as unit electric capacity Under, the vector of the capacitance composition of 7 electric capacity is：
CM=(11,7,7,3,2,1,1)=(10+1,7,6+1,3,2,1,1)
For each analog-digital converter in group N, it includes 7 electric capacity.Situation using LSB bit electric capacity as unit electric capacity Under, the vector of the capacitance composition of 7 electric capacity is：
CN=(10,8,6,4,2,1,1)=(10,7+1,6,3+1,2,1,1)
It should be noted that only giving a kind of specific capacitor combination herein, those skilled in the art can also basis Actual conditions, meet other capacitor combinations of formula 1- formulas 3 from others, and 7 electric capacity that should not be limited in the present embodiment, The present invention can be equally realized, is no longer described in detail herein.
In addition, the size for setting capacitance in technique meets normal distribution, and standard deviation is the 10% of LSB capacitances, other The distribution of electric capacity meets central-limit theorem.
As shown in figure 1, SAR ADC array (ADC-M of the identical input test signal by 2 × 20, ADC-N0, ADC- M1, ADC-N1) quantify, each analog-digital converter obtains corresponding 6 dimension output 0-1 code vectors.Four analog-digital converters obtain 6 Tie up 0-1 code vectors-DM0, DN0, DM1, DN1.In view of offset voltage be present, gradually-appoximant analog-digital converter array is in each vector Finally increase one-dimensional, and 1 (offset voltage exists always) is entered as, with D 'M0, D 'N0, D 'M1, D 'N1Represent.Gain mismatch is to ginseng Matrix number expression formula does not influence.
Register cell is used to store mismatch parameter matrix.In the present embodiment, analog-digital converter array includes 4 moduluses Converter, 4 analog-digital converters are divided into two group-group M and group N, and every group includes 2 analog-digital converters.Accordingly, deposit The mismatch parameter matrix stored in device is 2 × 2 matrixes：Wherein：
WMi=(gMi*CM·eMi, VOSMi)
WNi=(gNi*CN·eNi, VOSNi)
Wherein, gMiAnd gNiIt is gain parameter, VOSMiAnd VOSNiIt is offset voltage parameter, eMiAnd eNiIt is the mistake of capacitor array The diagonal matrix formed with parameter, i=0,1.
It should be noted that register and LMS wave filter groups are provided separately by the present embodiment.But in some cases, Register is built-in with LMS wave filter groups.In this case, the mismatch parameter matrix will be stored in built in LMS wave filter groups Register in, equally should be within protection scope of the present invention.
Fig. 1 is refer to, LMS wave filter groups are connected to the gradually-appoximant analog-digital converter array and register cell, its Following operation is performed in the signal period, each element of the mismatch parameter matrix in register is updated：Successively The 0-1 code vectors of the two adjacent analog-digital converter for belonging to different groups outputs are received, complete two modulus in mismatch parameter matrix The estimation of parameter vector corresponding to converter, after the signal period has been performed, complete once estimating to mismatch parameter matrix Meter and renewal
Fig. 3 is the schematic diagram that LMS wave filter groups carry out mismatch parameter correction in Fig. 1 gradually-appoximant analog-digital converter systems. Fig. 3 is refer to, on the basis of 4 analog-digital converters in analog-digital converter array are grouped, LMS wave filter groups perform Operate below, each element of the mismatch parameter matrix in register is updated：
Step A：Utilize analog-digital converter ADC-M0And ADC-N07 dimensional vector D ' of outputM0、D‘N0, complete to the first two mould Parameter (W corresponding to number converterM0, WN0) estimation and renewal；
Fig. 4 is the flow chart that LMS wave filters carry out mismatch parameter correction.As shown in figure 4, to parameter (WM0, WN0) estimation Basic procedure include：
Sub-step A1：Calculation error function e=D 'M0·WM0-D‘N0·WN0；
Sub-step A2：The parameter vector stored in renewal register：
WM0=WM0-u·e·(D‘M0-D‘N0)
WN0=WN0+u·e·(D‘M0-D‘N0)
Wherein, u is learning rate parameter, according to precision of A/D converter, the convergence rate and convergence precision of calibration process Compromise selection, typically takes the numerical value between 0.001~0.1.The estimation procedure in general LMS wave filter groups are no longer detailed herein Expansion.
Step B：Utilize analog-digital converter ADC-N0And ADC-M17 dimensional vector D ' of outputN0、D‘M1, complete to two moduluses Parameter (W corresponding to converterN0, WM1) estimation and renewal；
Wherein, parameter WN0, WM1It is consistent with the correlator step in step A, no longer repeat herein.
Step C：Utilize analog-digital converter ADC-M1And ADC-N17 dimensional vector D ' of outputM1、D‘N1, complete to two moduluses Parameter (the W of converterM1, WN1) estimation and renewal；
Wherein, parameter WM1, WN1It is consistent with the correlator step in step A, no longer repeat herein.
Step D：Utilize analog-digital converter ADC-N1And ADC-M07 dimensional vector D ' of outputN1、D‘M0, complete to two moduluses Parameter (the W of converterN1, WM0) estimation and renewal.
Wherein, parameter WN1, WM0It is consistent with the correlator step in step A, no longer repeat herein.
So far, the estimation and renewal of the parameter vector of first signal period are completed.
Change input signal, in the next signal cycle, above-mentioned estimation procedure is repeated, until parameter matrixConverge to the precision of design requirement.
It should be noted that the calibration of parameter matrix needs certain condition of convergence.One adequate condition is, if will The multigroup binary code inputted during LMS wave filter successive ignitions forms matrix, then the rank of matrix is necessarily equal to be calibrated The number of unknown parameter vector in mismatch parameter matrix.
Output circuit and control module, the rear end of LMS wave filter groups is connected to, for controlling SARADC arrays and LMS Wave filter group works exactly in order, and exports the final data signal of gradually-appoximant analog-digital converter system：(WM0·D’M0, WN0·D”N0, WM1·D’M1, WN1·D’N1)。
In real work, the renewal of parameter matrix and the output procedure of whole gradually-appoximant analog-digital converter array are only Vertical.Those skilled in the art will be apparent that correlated process, no longer describe in detail herein.
It should be noted that the LMS wave filters of prior art, which are often used for realizing, comprises only two groups of parameter vector systems Calibration.And in the present embodiment by the packet design of SAR ADC arrays, and parameter school is carried out by the way of chain circulation Standard, first, the condition of convergence is greatly reduced, second, can be protected while LMS wave filter groups realize local convergence to parametric calibration Demonstrate,prove global convergence.
In the present embodiment, analog-digital converter array includes 4 analog-digital converters, 4 analog-digital converters be divided into two groups- Group M and group N, but the present invention is not limited thereto.
In other embodiments of the present invention, analog-digital converter array can include 2Z analog-digital converter, and Z is integer.Should 2Z analog-digital converter is equally divided into two group-group M and group N, and two adjacent analog-digital converters adhere to different groups separately. The mismatch parameter matrix stored in register is 2 × Z matrix.
In this case, LMS wave filter groups perform following operation in a signal period, to the mismatch in register Each element of parameter matrix is updated：From two analog-digital converter (ADC-M0, ADC-N0) start, successively by two adjacent moduluses 7 dimension 0-1 code vector input LMS wave filters of converter output, complete the estimation and renewal of the parameter of two analog-digital converters, its In, analog-digital converter ADC-NZWith analog-digital converter ADC-M0It is considered as adjacent analog-digital converter.It is complete after predetermined period has been performed The estimation and renewal of paired mismatch parameter matrix.
So far, the present embodiment is described in detail combined accompanying drawing.According to above description, those skilled in the art There should be clear understanding to gradually-appoximant analog-digital converter system of the present invention.
In summary, in gradually-appoximant analog-digital converter system of the present invention, analog-digital converter array uses packet design, and Using the method for estimation of chain circulation, the calibration of completion analog-digital converter array that can be rapidly and efficiently, design is greatly reduced Complexity simultaneously reduces power consumption.
Particular embodiments described above, the purpose of the present invention, technical scheme and beneficial effect are carried out further in detail Describe in detail it is bright, should be understood that the foregoing is only the present invention specific embodiment, be not intended to limit the invention, it is all Within the spirit and principles in the present invention, any modification, equivalent substitution and improvements done etc., it should be included in the guarantor of the present invention Within the scope of shield.

Claims (7)

  1. A kind of 1. gradually-appoximant analog-digital converter system, it is characterised in that including：
    Register cell, for storing mismatch parameter matrix, wherein, the mismatch parameter matrix is 2 × Z matrix；
    Gradually-appoximant analog-digital converter array, it includes 2Z analog-digital converter, and the 2Z analog-digital converter is divided into two group-group M With a group N, every group includes Z analog-digital converter, wherein, two adjacent analog-digital converters adhere to different groups, same group of modulus separately Converter uses identical capacitor design, and the analog-digital converter of difference group uses different capacitor designs, in a signal period Interior, each analog-digital converter in the gradually-appoximant analog-digital converter array is tentatively measured to input analog signal respectively Change, obtain 0-1 code vectors；And
    LMS wave filter groups, the gradually-appoximant analog-digital converter array and register cell are connected to, it is in the signal period Operated below middle execution, each element of the mismatch parameter matrix in register is updated：Two adjacent category are received successively In the 0-1 code vectors that different groups of analog-digital converters export, complete corresponding to two analog-digital converter to join in mismatch parameter matrix The estimation of number vector, after the signal period has been performed, complete once estimation and renewal to mismatch parameter matrix；
    Wherein, the analog-digital converter in the gradually-appoximant analog-digital converter array is gradually-appoximant analog-digital converter；
    Wherein, 2Z analog-digital converter in the gradually-appoximant analog-digital converter array is followed successively by：ADC-M0,ADC- N0,……,ADC-Mi,ADC-Ni,……,ADC-Mz-1,ADC-Nz-1；ADC-Mi,ADC-NiRespectively Approach by inchmeal analog-to-digital conversion I-th of analog-digital converter in device array group M and group N；The ADC-Nz-1With ADC-M0It is considered as adjacent analog-digital converter；
    Wherein, the 0-1 code vectors of the analog-digital converter output MSB dimensions；The gradually-appoximant analog-digital converter array is in the MSB The finally increase of the 0-1 code vectors of dimension is one-dimensional, and is entered as 1, and the 0-1 code vectors that the MSB+1 is tieed up are inputted to LMS wave filters Group；
    Wherein, the LMS wave filter groups receive successively the 0-1 codes of the two adjacent analog-digital converters outputs for belonging to different groups to Amount, the estimation of parameter vector corresponding to two analog-digital converter in mismatch parameter matrix is completed in such a way：
    Sub-step A1：Calculation error function e=D 'Mp·WMp-D‘Nq·WNq；
    Sub-step A2：The parameter vector stored in renewal register：
    WMp=WMp-u·e·(D‘Mp-D‘Nq)
    WNq=WNq+u·e·(D‘Mp-D‘Nq)
    Wherein, D 'MpFor p-th of analog-digital converter-ADC-M in group MpThe 0-1 code vectors of corresponding MSB+1 dimensions, WMpJoin for mismatch ADC-M in matrix numberpCorresponding parameter vector；D‘NqFor q-th of analog-digital converter-ADC-N in group NqCorresponding MSB+1 dimensions 0-1 code vectors, WNqFor ADC-N in mismatch parameter matrixqCorresponding parameter vector；U is learning rate parameter；P=q or | p-q | =1.
  2. 2. gradually-appoximant analog-digital converter system according to claim 1, it is characterised in that the gradually analog-digital converter Each analog-digital converter in array is the analog-digital converter of MSB dimensions, and it includes DAC electric capacity sequence C=(CMSB, CMSB-1,……C2,C1,C0), the DAC electric capacity sequence Cs meet following condition：
    1. for i ∈ { 1,2 ... ..., MSB-1, MSB }, meet
    ②
    3. MSB ＞ log2c；
    Wherein, CiThe capacitance of i-th of electric capacity in DAC electric capacity sequence Cs is represented, c is the electric capacity gross area, same group of analog-to-digital conversion Device correspondingly meets a solution of above-mentioned condition, and the analog-digital converter of difference group correspondingly meets the different solutions of above-mentioned condition.
  3. 3. gradually-appoximant analog-digital converter system according to claim 2, it is characterised in that turn for the gradually modulus Each analog-digital converter in converter array, it also includes：
    Switching network, the process during Approach by inchmeal is controlled by controlling the connected mode of electric capacity in DAC electric capacity sequences；
    Comparator, the rear end of DAC capacitor arrays is connected to, for completing relatively and to obtain a binary system output result every time；
    Output control circuit, for controlling analog-digital converter to work exactly in order.
  4. 4. gradually-appoximant analog-digital converter system according to claim 1, it is characterised in that the learning rate parameter u Between 0.001~0.1.
  5. 5. gradually-appoximant analog-digital converter system according to claim 1, it is characterised in that real by K signal period The convergence of the existing mismatch parameter matrix, wherein, the corresponding input analog signal of each signal period, K >=20.
  6. 6. gradually-appoximant analog-digital converter system according to any one of claim 1 to 5, it is characterised in that also include：
    Output circuit and control module, the rear end of LMS wave filter groups is connected to, for controlling SAR ADC arrays and LMS to filter Device group works exactly in order, and exports the final data signal of gradually-appoximant analog-digital converter system.
  7. 7. gradually-appoximant analog-digital converter system according to any one of claim 1 to 5, it is characterised in that described to post Storage unit is separately provided, or is arranged in the gradually-appoximant analog-digital converter array or LMS wave filter groups.
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CN108141219B (en) * 2017-12-12 2021-07-09 深圳市汇顶科技股份有限公司 Method for analog-to-digital conversion and analog-to-digital converter
CN110380729B (en) * 2019-09-02 2022-04-22 电子科技大学 Successive approximation analog-to-digital converter quantization method based on prediction and local oversampling
CN112865798A (en) * 2021-01-15 2021-05-28 中国科学院半导体研究所 Noise shaping successive approximation analog-to-digital converter and noise shaping method
CN116318142A (en) * 2023-02-08 2023-06-23 北京士模微电子有限责任公司 Analog-to-digital converter calibration method and analog-to-digital converter
CN117439604B (en) * 2023-12-18 2024-04-09 杭州晶华微电子股份有限公司 Analog-to-digital converter, fully differential analog-to-digital converter and sensor measurement system

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