CN104467857A - Successive approximation analog-digital converter system - Google Patents
Successive approximation analog-digital converter system Download PDFInfo
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- CN104467857A CN104467857A CN201410837097.1A CN201410837097A CN104467857A CN 104467857 A CN104467857 A CN 104467857A CN 201410837097 A CN201410837097 A CN 201410837097A CN 104467857 A CN104467857 A CN 104467857A
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Abstract
The invention provides a successive approximation analog-digital converter system. According to the successive approximation analog-digital converter system, the grouping design is adopted in analog-digital converter arrays, the chained cyclic estimation method is adopted, and single-channel SAR ADC capacitance mismatching can be eliminated; due to nonlinearity led by non-ideal factors such as gain mismatching and offset voltage mismatching between SAR ADC arrays, calibration of the analog-digital converter arrays can be rapidly and efficiently completed, the design complexity is greatly lowered, and the power consumption is reduced.
Description
Technical field
The present invention relates to electron trade technical field of electronic components, particularly relate to a kind of gradually-appoximant analog-digital converter (SAR ADC) system.
Background technology
Analog to digital converter is the interface circuit of analog circuit and digital circuit in signal processing.Wherein SAR ADC is because be suitable for process and reduce, and structure is simple, is very welcome structure in recent years.In the sensor array of medium accuracy, therefore it be also widely applied.
But in array analog to digital converter, mismatch result in serious non-linear.The single channel analog to digital converter itself caused except capacitance mismatch non-linear, the gain mismatch between passage, offset voltage mismatch etc., further limit the linearity of array analog to digital converter.
In recent years, the calibration SARADC that is introduced as of redundancy concept and LMS filter provides new thinking, and under the support of corresponding auxiliary circuit, these technology obtain application in the calibration of single channel and time-interleaved SAR ADC.
Summary of the invention
(1) technical problem that will solve
In view of above-mentioned technical problem, the invention provides a kind of gradually-appoximant analog-digital converter system, to eliminate the capacitance mismatch of single-channel SAR ADC itself, it is non-linear that the non-ideal factors such as the gain mismatch between SAR ADC array and offset voltage mismatch are introduced.
(2) technical scheme
Gradually-appoximant analog-digital converter system of the present invention comprises: register cell, and for storing mismatch parameter matrix, wherein, this mismatch parameter matrix is the matrix of 2 × Z; Gradually-appoximant analog-digital converter array, it comprises 2Z analog to digital converter, this 2Z analog to digital converter is divided into two groups-group M and group N, often group comprises Z analog to digital converter, wherein, two adjacent analog to digital converters adhere to different groups separately, the analog to digital converter of same group adopts identical capacitor design, the analog to digital converter of different group adopts different capacitor design, within a signal period, each analog to digital converter in this gradually-appoximant analog-digital converter array carries out initial quantization to input analog signal respectively, obtains 0-1 code vector; And LMS bank of filters, be connected to described gradually-appoximant analog-digital converter array and register cell, it operates below performing in the described signal period, each element of mismatch parameter matrix in register is upgraded: receive the two adjacent 0-1 code vectors belonging to the analog to digital converter output of different group successively, complete the estimation of the parameter vector that this two analog to digital converter is corresponding in mismatch parameter matrix, after executing the described signal period, complete the once estimation to mismatch parameter matrix and renewal.Wherein, the analog to digital converter in described gradually-appoximant analog-digital converter array is gradually-appoximant analog-digital converter.
(3) beneficial effect
In gradually-appoximant analog-digital converter system of the present invention, analog to digital converter array adopts packet design, and adopts the method for estimation of chain circulation, rapidly and efficiently can complete the calibration of analog to digital converter array, greatly reduces design complexities and reduce power consumption.
Accompanying drawing explanation
Fig. 1 is the structural representation according to embodiment of the present invention gradually-appoximant analog-digital converter system;
Fig. 2 is the schematic diagram of an analog to digital converter in analog to digital converter array in the present embodiment gradually-appoximant analog-digital converter system;
Fig. 3 is the schematic diagram that in Fig. 1 gradually-appoximant analog-digital converter system, LMS bank of filters carries out mismatch parameter correction;
Fig. 4 is the flow chart that LMS filter carries out mismatch parameter correction.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly understand, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.It should be noted that, in accompanying drawing or specification describe, similar or identical part all uses identical figure number.The implementation not illustrating in accompanying drawing or describe is form known to a person of ordinary skill in the art in art.In addition, although herein can providing package containing the demonstration of the parameter of particular value, should be appreciated that, parameter without the need to definitely equaling corresponding value, but can be similar to corresponding value in acceptable error margin or design constraint.The direction term mentioned in embodiment, such as " on ", D score, "front", "rear", "left", "right" etc., be only the direction with reference to accompanying drawing.Therefore, the direction term of use is used to illustrate and is not used for limiting the scope of the invention.
In gradually-appoximant analog-digital converter system of the present invention, analog to digital converter array adopts packet design, adopts the method for estimation of chain circulation to carry out the calibration of analog to digital converter array.Specifically:
(1) capacitor array in analog to digital converter array in analog to digital converter: C=(C
mSB, C
mSB-1... C
2, C
1, C
0) meet the following conditions:
1, for i ∈ 1,2 ..., MSB-1, MSB}, meet
2、
3、MSB＞log
2c
Wherein, formula 1 is the adequate condition that analog to digital converter has good differential nonlinearity (DNL).C
irepresent the capacitance of i-th electric capacity, c is the electric capacity gross area (size), and when designing, the index such as noise of coupling system is given.
In theory, the constraints based on formula 1, formula 2, formula 3 has different solutions to capacitor array C, and has identical resolution based on each capacitor array separating design.
Analog to digital converter array adopts packet design to refer to: in analog to digital converter array, and the capacitor array of the analog to digital converter of identical group adopts identical C design, and different group adopts different C designs.
(2) calibration adopting the method for estimation of chain circulation to carry out analog to digital converter array refers to: by the Output rusults of the identical input signal of analog to digital converter sample quantization of difference group, input LMS (leastmean square) bank of filters, chain circulation estimates the mismatch parameter of analog to digital converter array; When mismatch parameter converges to certain precision, calibration terminates.
Multiple embodiment is below adopted to be described in detail to gradually-appoximant analog-digital converter system of the present invention.
In one exemplary embodiment of the present invention, provide a kind of gradually-appoximant analog-digital converter system.Fig. 1 is the structural representation according to embodiment of the present invention gradually-appoximant analog-digital converter system.As shown in Figure 1, the present embodiment gradually-appoximant analog-digital converter system comprises: register cell, gradually-appoximant analog-digital converter (SARADC) array, LMS bank of filters and output circuit and control module.
Below respectively each part of the present embodiment gradually-appoximant analog-digital converter system is described in detail.
Please refer to Fig. 1, gradually-appoximant analog-digital converter (SAR ADC) array, it comprises 4 analog to digital converters, and these 4 analog to digital converters are divided into two groups-group M and group N, and often group comprises 2 analog to digital converters.These 4 analog to digital converters are marked as respectively: ADC-M
0, ADC-N
0, ADC-M
1, ADC-N
1.
Wherein, the analog to digital converter in same group adopts identical capacitor design, namely adopts identical DAC design.Within a signal period, each analog to digital converter in this gradually-appoximant analog-digital converter (SAR ADC) array carries out initial quantization to input analog signal respectively, obtains 0-1 code vector.
Fig. 2 is the schematic diagram of an analog to digital converter in analog to digital converter array in the present embodiment gradually-appoximant analog-digital converter system.As shown in Figure 2, this analog to digital converter comprises:
DAC electric capacity sequence, in the sample phase of ADC as sampling hold circuit to analog signal sampling, provide suitable reference level to complete the quantification of analog signal in the Approach by inchmeal stage;
Switching network, by the connected mode of electric capacity in control DAC electric capacity sequence to control the process in Approach by inchmeal process;
Comparator, is connected to the rear end of DAC capacitor array, for complete each relatively and obtain a binary system Output rusults (" 0 " or " 1 ");
Output control circuit, works in order exactly for controlling analog to digital converter.
Please refer to Fig. 2, if MSB=6.As mentioned above, for group M and group N, the analog to digital converter of same group adopts identical capacitor design, and the analog to digital converter of different group adopts different capacitor design.
For each analog to digital converter in group M, it comprises 7 electric capacity.In units of the electric capacity of LSB position when electric capacity, the vector of the capacitance composition of these 7 electric capacity is:
C
M＝(11，7，7，3，2，1，1)＝(10+1，7，6+1，3，2，1，1)
For each analog to digital converter in group N, it comprises 7 electric capacity.In units of the electric capacity of LSB position when electric capacity, the vector of the capacitance composition of these 7 electric capacity is:
C
N＝(10，8，6，4，2，1，1)＝(10，7+1，6，3+1，2，1，1)
It should be noted that, only give a kind of specific capacitor combination herein, those skilled in the art can also according to actual conditions, select other other capacitor combinations meeting formula 1-formula 3, and 7 electric capacity that should not be limited in the present embodiment, the present invention can be realized equally, no longer describe in detail herein.
In addition, if the size of capacitance meets normal distribution in technique, and standard deviation is 10% of LSB capacitance, and the distribution of other electric capacity meets central-limit theorem.
As shown in Figure 1, identical input test signal passes through the SAR ADC array (ADC-M of 2 × 2
0, ADC-N
0, ADC-M
1, ADC-N
1) quantize, each analog to digital converter obtains corresponding 6 dimensions and exports 0-1 code vector.The 6 dimension 0-1 code vector-D that four analog to digital converters obtain
m0, D
n0, D
m1, D
n1.Consider to there is offset voltage, gradually-appoximant analog-digital converter array finally increases one dimension at each vector, and assignment is 1 (offset voltage exists always), with D '
m0, D '
n0, D '
m1, D '
n1represent.Gain mismatch does not affect parameter matrix expression formula.
Register cell is for storing mismatch parameter matrix.In the present embodiment, analog to digital converter array comprises 4 analog to digital converters, and these 4 analog to digital converters are divided into two groups-group M and group N, and often group comprises 2 analog to digital converters.Accordingly, the mismatch parameter matrix stored in register is 2 × 2 matrixes:
Wherein:
W
Mi＝(g
Mi*C
M·e
Mi，V
OSMi)
W
Ni＝(g
Ni*C
N·e
Ni，V
OSNi)
Wherein, g
miand g
nigain parameter, V
oSMiand V
oSNioffset voltage parameter, e
miand e
nithe diagonal matrix that the mismatch parameter of capacitor array is formed, i=0,1.
It should be noted that, register and LMS bank of filters are provided separately by the present embodiment.But in some cases, in LMS bank of filters, be built-in with register.In this case, this mismatch parameter matrix will be stored in the built-in register of LMS bank of filters, equally should within protection scope of the present invention.
Please refer to Fig. 1, LMS bank of filters is connected to described gradually-appoximant analog-digital converter array and register cell, it operates below performing in the described signal period, each element of mismatch parameter matrix in register is upgraded: receive the two adjacent 0-1 code vectors belonging to the analog to digital converter output of different group successively, complete the estimation of the parameter vector that this two analog to digital converter is corresponding in mismatch parameter matrix, after executing the described signal period, complete the once estimation to mismatch parameter matrix and renewal
Fig. 3 is the schematic diagram that in Fig. 1 gradually-appoximant analog-digital converter system, LMS bank of filters carries out mismatch parameter correction.Please refer to Fig. 3, on the basis of dividing into groups to the analog to digital converter of 4 in analog to digital converter array, LMS bank of filters performs following operation, upgrades each element of the mismatch parameter matrix in register:
Steps A: utilize analog to digital converter ADC-M
0and ADC-N
0the 7 dimensional vector D ' exported
m0, D '
n0, complete the parameter (W corresponding to the first two analog to digital converter
m0, W
n0) estimation and renewal;
Fig. 4 is the flow chart that LMS filter carries out mismatch parameter correction.As shown in Figure 4, to parameter (W
m0, W
n0) the basic procedure of estimation comprise:
Sub-step A1: error of calculation function e=D '
m0w
m0-D '
n0w
n0;
Sub-step A2: upgrade the parameter vector stored in register:
W
M0＝W
M0-u·e·(D‘
M0-D‘
N0)
W
N0＝W
N0+u·e·(D‘
M0-D‘
N0)
Wherein, u is learning rate parameter, and according to precision of A/D converter, the convergence rate of calibration process and convergence precision compromise are selected, and generally get the numerical value between 0.001 ~ 0.1.The LMS bank of filters that this estimation procedure is general, launches herein no longer in detail.
Step B: utilize analog to digital converter ADC-N
0and ADC-M
1the 7 dimensional vector D ' exported
n0, D '
m1, complete the parameter (W corresponding to two analog to digital converters
n0, W
m1) estimation and renewal;
Wherein, parameter W
n0, W
m1consistent with the correlator step in steps A, no longer repeat herein.
Step C: utilize analog to digital converter ADC-M
1and ADC-N
1the 7 dimensional vector D ' exported
m1, D '
n1, complete the parameter (W to two analog to digital converters
m1, W
n1) estimation and renewal;
Wherein, parameter W
m1, W
n1consistent with the correlator step in steps A, no longer repeat herein.
Step D: utilize analog to digital converter ADC-N
1and ADC-M
0the 7 dimensional vector D ' exported
n1, D '
m0, complete the parameter (W to two analog to digital converters
n1, W
m0) estimation and renewal.
Wherein, parameter W
n1, W
m0consistent with the correlator step in steps A, no longer repeat herein.
So far, estimation and the renewal of the parameter vector of first signal period is completed.
Change input signal, in the next signal cycle, repeat above-mentioned estimation procedure, until parameter matrix
Converge to the precision of designing requirement.
It should be noted that, the calibration of parameter matrix needs certain condition of convergence.An adequate condition is, if many groups binary code of inputting during LMS filter successive ignition is formed matrix, so this rank of matrix must equal the number of unknown parameter vector in mismatch parameter matrix to be calibrated.
Output circuit and control module, be connected to the rear end of LMS bank of filters, works exactly in order for control SARADC array and LMS bank of filters, and export the final digital signal of gradually-appoximant analog-digital converter system: (W
m0d '
m0, W
n0d "
n0, W
m1d '
m1, W
n1d '
n1).
In real work, the renewal of parameter matrix and the output procedure of whole gradually-appoximant analog-digital converter array are independently.Those skilled in the art know correlated process very much, no longer describe in detail herein.
It should be noted that, the LMS filter of prior art is often used for realizing the calibration only containing two groups of parameter vector systems.And in the present embodiment by the packet design of SAR ADC array, and adopt the mode of chain circulation to carry out parametric calibration, one is greatly reduce the condition of convergence, and two is can ensure global convergence LMS bank of filters realizes local convergence to parametric calibration while.
In the present embodiment, analog to digital converter array comprises 4 analog to digital converters, and these 4 analog to digital converters are divided into two groups-group M and group N, but the present invention is not as limit.
In other embodiments of the present invention, analog to digital converter array can comprise 2Z analog to digital converter, and Z is integer.This 2Z analog to digital converter can be divided into two groups-group M and group N equally, and two adjacent analog to digital converters adhere to different groups separately.The mismatch parameter matrix stored in register is the matrix of 2 × Z.
In this case, operate below LMS bank of filters performs in a signal period, each element of the mismatch parameter matrix in register is upgraded: from two analog to digital converter (ADC-M
0, ADC-N
0) start, the 7 dimension 0-1 code vector input LMS filters exported by two adjacent analog to digital converters successively, complete estimation and the renewal of the parameter of two analog to digital converters, wherein, and analog to digital converter ADC-N
zwith analog to digital converter ADC-M
0be considered as adjacent analog to digital converter.After executing predetermined period, complete the estimation to mismatch parameter matrix and renewal.
So far, by reference to the accompanying drawings the present embodiment has been described in detail.Describe according to above, those skilled in the art should have gradually-appoximant analog-digital converter system of the present invention and have clearly been familiar with.
In sum, in gradually-appoximant analog-digital converter system of the present invention, analog to digital converter array adopts packet design, and adopts the method for estimation of chain circulation, rapidly and efficiently can complete the calibration of analog to digital converter array, greatly reduce design complexities and reduce power consumption.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a gradually-appoximant analog-digital converter system, is characterized in that, comprising:
Register cell, for storing mismatch parameter matrix, wherein, this mismatch parameter matrix is the matrix of 2 × Z;
Gradually-appoximant analog-digital converter array, it comprises 2Z analog to digital converter, this 2Z analog to digital converter is divided into two groups-group M and group N, often group comprises Z analog to digital converter, wherein, two adjacent analog to digital converters adhere to different groups separately, the analog to digital converter of same group adopts identical capacitor design, the analog to digital converter of different group adopts different capacitor design, within a signal period, each analog to digital converter in this gradually-appoximant analog-digital converter array carries out initial quantization to input analog signal respectively, obtains 0-1 code vector; And
LMS bank of filters, be connected to described gradually-appoximant analog-digital converter array and register cell, it operates below performing in the described signal period, each element of mismatch parameter matrix in register is upgraded: receive the two adjacent 0-1 code vectors belonging to the analog to digital converter output of different group successively, complete the estimation of the parameter vector that this two analog to digital converter is corresponding in mismatch parameter matrix, after executing the described signal period, complete the once estimation to mismatch parameter matrix and renewal;
Wherein, the analog to digital converter in described gradually-appoximant analog-digital converter array is gradually-appoximant analog-digital converter.
2. gradually-appoximant analog-digital converter system according to claim 1, is characterized in that, each analog to digital converter in described successively analog to digital converter array is the analog to digital converter of MSB dimension, and it comprises DAC electric capacity sequence C=(C
mSB, C
mSB-1... C
2, C
1, C
0), this DAC electric capacity sequence C meets the following conditions:
1. for i ∈ 1,2 ..., MSB-1, MSB}, meet
②
③MSB＞log
2c；
Wherein, C
irepresent the capacitance of i-th electric capacity in DAC electric capacity sequence C, c is the electric capacity gross area, and the analog to digital converter correspondence of same group meets a solution of above-mentioned condition, and the analog to digital converter correspondence of different group meets the difference solution of above-mentioned condition.
3. gradually-appoximant analog-digital converter system according to claim 2, is characterized in that, for each analog to digital converter in described successively analog to digital converter array, it also comprises:
Switching network, by the connected mode of electric capacity in control DAC electric capacity sequence to control the process in Approach by inchmeal process;
Comparator, is connected to the rear end of DAC capacitor array, for complete each relatively and obtain a binary system Output rusults;
Output control circuit, works in order exactly for controlling analog to digital converter.
4. gradually-appoximant analog-digital converter system according to claim 2, is characterized in that, 2Z analog to digital converter in described gradually-appoximant analog-digital converter array is followed successively by: ADC-M
0, ADC-N
0..., ADC-M
i, ADC-N
i..., ADC-M
z-1, ADC-N
z-1;
Wherein, ADC-M
i, ADC-N
ibe respectively i-th analog to digital converter in gradually-appoximant analog-digital converter array group M and group N; Described ADC-N
z-1with ADC-M
0be considered as adjacent analog to digital converter.
5. gradually-appoximant analog-digital converter system according to claim 1, is characterized in that, described analog to digital converter exports the 0-1 code vector of MSB dimension;
The last increase one dimension of the 0-1 code vector that described gradually-appoximant analog-digital converter array is tieed up at this MSB, and assignment is 1, and the 0-1 code vector tieed up by this MSB+1 inputs to LMS bank of filters.
6. gradually-appoximant analog-digital converter system according to claim 5, it is characterized in that, described LMS bank of filters receives the two adjacent 0-1 code vectors belonging to the analog to digital converter output of different group successively, completes the estimation of the parameter vector that this two analog to digital converter is corresponding in mismatch parameter matrix in such a way:
Sub-step A1: error of calculation function e=D '
mpw
mp-D '
nqw
nq;
Sub-step A2: upgrade the parameter vector stored in register:
W
Mp＝W
Mp-u·e·(D′
Mp-D′
Nq)
W
Nq＝W
Nq+u·e·(D′
Mp-D′
Nq)
Wherein, D '
mpfor p analog to digital converter-ADC-M in group M
pthe 0-1 code vector of corresponding MSB+1 dimension, W
mpfor ADC-M in mismatch parameter matrix
pcorresponding parameter vector; D '
nqfor q analog to digital converter-ADC-N in group N
qthe 0-1 code vector of corresponding MSB+1 dimension, W
nqfor ADC-N in mismatch parameter matrix
qcorresponding parameter vector; U is learning rate parameter; P=q or | p-q|=1.
7. gradually-appoximant analog-digital converter system according to claim 6, is characterized in that, described learning rate parameter u is between 0.001 ~ 0.1.
8. gradually-appoximant analog-digital converter system according to claim 1, is characterized in that, by K signal period, realizes the convergence of described mismatch parameter matrix, wherein, and each signal period corresponding input analog signal, described K >=20.
9. gradually-appoximant analog-digital converter system according to any one of claim 1 to 8, is characterized in that, also comprise:
Output circuit and control module, be connected to the rear end of LMS bank of filters, works exactly in order for control SARADC array and LMS bank of filters, and export the final digital signal of gradually-appoximant analog-digital converter system.
10. gradually-appoximant analog-digital converter system according to any one of claim 1 to 8, is characterized in that, described register cell is arranged separately, or is arranged in described gradually-appoximant analog-digital converter array or LMS bank of filters.
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| CN116318142B (en) * | 2023-02-08 | 2024-05-03 | 北京士模微电子有限责任公司 | Analog-to-digital converter calibration method and analog-to-digital converter |
| CN117439604A (en) * | 2023-12-18 | 2024-01-23 | 杭州晶华微电子股份有限公司 | Analog-to-digital converter, fully differential analog-to-digital converter and sensor measurement system |
| CN117439604B (en) * | 2023-12-18 | 2024-04-09 | 杭州晶华微电子股份有限公司 | Analog-to-digital converter, fully differential analog-to-digital converter and sensor measurement system |
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