CN101977058B - Sequential approximation analog to digital converter with digital correction and processing method thereof - Google Patents

Abstract

The invention discloses a sequential approximation analog to digital converter with digital correction and a processing method thereof aiming at the defect of difficult composition manufacture of a coupling capacitor in the traditional sequential approximation analog to digital converter. The sequential approximation analog to digital converter comprises a main DAC (Digital Analogue Converter), a calibration DAC, a comparer, a control circuit and a storage. The sequential approximation analog to digital converter is characterized in that the main DAC comprises a high-K-bit CDAC (Capacitance Digital Analogue Converter) and a low-N-bit CDAC. Introduced system errors and capacitance matching errors are digitally corrected and eliminated, error voltages corresponding to capacitors in the high-K-bit CDAC are quantized and stored in the storage, and two-digit 0 are added behind the tail of the quantized residual error voltage digital code and participate in the calculation of the error voltages. When normal conversion is carried out, the error voltage digital codes are accumulated and then last two digits are discarded, the remain digital codes are used as the input of the calibration DAC, thus the accuracy of the analog to digital converter is improved.

Description

Gradually-appoximant analog-digital converter and processing method thereof with figure adjustment

Technical field

The invention belongs to analog digital switch technology field, particularly a kind of analog to digital converter and processing method thereof.

Background technology

The precision of approaching one by one modulus (A/D, Analog/Digital) transducer is higher, and power consumption is very low, although conversion speed is partially slow, but in the occasion that does not much need high-speed transitions, in touch screen control circuit, gradually-appoximant analog-digital converter has become a kind of selection commonly used.

Traditional A/D converter that approaches one by one adopts the mode of segmentation to realize usually, generally has several like this: switched capacitor array is adopted in (1) high K position, and resistance string is adopted in low N position; (2) high K position employing resistance string, switched capacitor array is adopted in low N position; (3) switched capacitor array is all adopted in high K position and low N position.

If adopt single resistance string structure, meeting if adopt single Kind of Switched Capacitor Array, then can occur the very large electric capacity of capacitance so that the number of resistance is too much, these consequences not only can so that chip area becomes very large, also can worsen the matching degree between resistance or the electric capacity simultaneously.The sub-DAC that resistance string consists of can guarantee the monotonicity of circuit, but the matching degree of resistance is not so good as electric capacity, so precision is relatively relatively poor; The sub-DAC that the ratio of precision resistance string of the sub-DAC that switched capacitor array consists of consists of is high, but this structure may make circuit nonmonotonicity or short in size occur.In addition, be 12 or the higher A/D converter that approaches one by one for precision, even minutes two sections also can so that the number of resistance too much or the value of electric capacity excessive, be difficult to realize the circuit of low-cost and high-precision.

If occurred described two high K seat DAC and the low N seat DAC that consisted of by switched capacitor array of above-mentioned (3) kind situation in the A/D converter approaching one by one, between these two sub-DAC, needed an electric capacity to be coupled so.Ideally, this coupling capacitance C _sNot the integral multiple of specific capacitance C, but a fractional value electric capacity, for example

But when layout design, under the prerequisite that guarantees the matching degree between the electric capacity, fractional value electric capacity is difficult to realize.Here need specific capacitance and fractional value electric capacity are described: the value of most electric capacity all is the integral multiple of certain capacitor C, such as C, and 2C, 4C, 8C, 16C, here " C " just is called a specific capacitance, and the value of specific capacitance can be decided by the designer, usually in 100fF～1pF; For fractional value electric capacity, its value is not the integral multiple of specific capacitance just, but minute several times.

Summary of the invention

The objective of the invention is to have proposed a kind of gradually-appoximant analog-digital converter with figure adjustment in order to overcome the shortcoming of coupling capacitance composing making difficulty in the existing gradually-appoximant analog-digital converter.

To achieve these goals, technical scheme of the present invention is:

A kind of gradually-appoximant analog-digital converter with figure adjustment, comprise main DAC, calibration DAC, comparator, control circuit, memory, the positive input termination common-mode voltage of comparator, the output of negative input termination master DAC, it is characterized in that, described main DAC comprises the high K position CDAC of switched capacitor array formation and the low N position CDAC that switched capacitor array consists of, and be coupled by a specific capacitance between high K position CDAC and the low N position CDAC, be coupled by a coupling capacitance between the output of calibration DAC and the output of main DAC.

As the further improvement of such scheme, for the precision that improves analog to digital converter and guarantee certain monotonicity, main DAC also comprises the middle M position RDAC that is made of resistance string.

Another aspect of the present invention is in order to adapt to the improvement of above-mentioned gradually-appoximant analog-digital converter structure, has proposed a kind of with it processing method of supporting gradually-appoximant analog-digital converter with figure adjustment, and the method specifically comprises the steps:

Step 1: after circuit powers on, first the residual error voltage of high K position each electric capacity of CDAC quantized successively by the order from a high position to the low level, corresponding electric capacity first ground connection under the control of clock connects reference voltage again, than all low electric capacity of this electric capacity figure place, all electric capacity that comprise low N position CDAC, then connect first again ground connection of reference voltage, and than high all electric capacity one of this electric capacity figure place directly, the output of comparator is controlled the SAR in the control circuit, and the output of SAR connects the input of calibration DAC, when quantizing to finish, the output voltage of calibration DAC is exactly the residual error voltage of corresponding electric capacity with the difference of common-mode voltage;

Step 2: error voltage corresponding to highest order equals residual error voltage corresponding to highest order divided by 2;

The residual error voltage that every corresponding error voltage in the high K position except highest order equals this deducts than this high every error voltage sum again divided by 2;

Error voltage corresponding to N position (or the M+N position in the above-mentioned improvement project) equals error voltage corresponding to N+1 position (or the M+N+1 position in the above-mentioned improvement project) and deducts residual error voltage corresponding to N+1 position (or the M+N+1 position in the above-mentioned improvement project) again divided by 2;

(or the M+N-1 position the above-mentioned improvement project) everybody error voltage equals than this high one error voltage divided by 2 from the 1st to the N-1 position.

Conversion from residual error voltage to error voltage is to carry out in the mode of numeral, and participates in together computing two of the residual error voltage digital code end of calibration DAC output back, position increases, and these two all are preset as 0;

Step 3: when carrying out normal conversion, be defined as 1 every corresponding error voltage digital code by SAR and added up and give up again last two, with the input as calibration DAC.

Beneficial effect of the present invention: the designed main DAC of the present invention is divided into two sections or three sections realizations, so that also can avoid using too much resistance or excessive electric capacity when higher approaching one by one the A/D converter precision; High-order CDAC and the coupling capacitance between the low level CDAC of two switched capacitor array formations change a specific capacitance into by desirable mark electric capacity, have avoided the making of fractional value electric capacity, have improved the matching degree of whole capacitor array domain; The be coupled systematic error introduced and the matching error between the high-order CDAC electric capacity of applying unit electric capacity all can be eliminated by the figure adjustment technology; Back, position, residual error voltage digital code end in calibration DAC output increases by two zero calculating that participate in again error voltage, has reduced the error that binary number brings in calculating process.

Description of drawings

Fig. 1 is gradually-appoximant analog-digital converter system block diagram of the present invention.

Fig. 2 is the main DAC of minute two sections realizations, the structural representation of calibration DAC and comparator.

Fig. 3 is for quantizing capacitor C ₈Corresponding residual error voltage V _S8The process schematic diagram.

Fig. 4 is to the structural representation of input during analog signal sampling in the circuit embodiments one.

Fig. 5 is the structural representation when carrying out normal conversion in the circuit embodiments one.

Fig. 6 is the main DAC of minute three sections realizations, the structural representation of calibration DAC and comparator.

Fig. 7 is to the structural representation of input during analog signal sampling in the circuit embodiments two.

Fig. 8 is the structural representation when carrying out normal conversion in the circuit embodiments two.

Fig. 9 is the simulation result of DNL and INL during with self calibration.

The simulation result of Figure 10 DNL and INL for not with self calibration the time.

Figure 11 is the simulation result with self calibration SNR and ENOB with not with self calibration the time.

Embodiment

Below in conjunction with accompanying drawing, provide specific embodiments of the invention.Need to prove: the parameter among the embodiment does not affect generality of the present invention.

A kind of gradually-appoximant analog-digital converter system block diagram with figure adjustment of the present invention as shown in Figure 1, comprise main DAC, calibration DAC, comparator, control circuit, memory and data output stage, the positive input termination common-mode voltage of comparator, the output of negative input termination master DAC, main DAC comprises the high K position CDAC of switched capacitor array formation and the low N position CDAC that switched capacitor array consists of, and be coupled by a specific capacitance between high K position CDAC and the low N position CDAC, be coupled by a coupling capacitance between the output of calibration DAC and the output of main DAC.

Be specifically described below in conjunction with two embodiment.

Embodiment one: suppose that two sections of low 4 CDAC that high 5 CDAC that main DAC is made of capacitor array and capacitor array consist of form.

Fig. 2 is the main DAC of minute two sections realizations, and the structural representation of calibration DAC and comparator comprises CDAC high 5 among the main DAC 101, low 4 CDAC 103, and 9 calibration DAC 104 and comparator 105.Be coupled by specific capacitance Cs between high-order CDAC 101 and the low level CDAC 103, be coupled by capacitor C c between the output of calibration DAC 104 and the output of main DAC.

Each electric capacity of supposing high-order CDAC 101 is respectively:

C ₈=(2 ⁴+ Δ C ₈) C, C ₇=(2 ³+ Δ C ₇) C, C ₆=(2 ²+ Δ C ₆) C, C ₅=(2+ Δ C ₅) C, C ₄=(1+ Δ C ₄) C, wherein Δ C _iBe the error of each electric capacity, C is specific capacitance.

Each electric capacity of supposing low level CDAC 103 is respectively: C ₃=2 ³C, C ₂=2 ²C, C ₁=2C, C ₀=C ' ₀=C.

Suppose that the coupling capacitance between calibration DAC 104 and the main DAC is: C _C=KC, wherein K is a positive integer.

In above hypothesis, each electric capacity of low level CDAC 103 all is desirable, does not have error.This is because the matching error of electric capacity is only the whole principal element of approaching one by one the A/D converter precision of impact among the high-order CDAC 101, therefore only needs to proofread and correct the matching error of electric capacity among the high-order CDAC 101.

Except above hypothesis, definition C ' ₄=C _S|| C _LSB=C _S|| 16C=(1+ Δ C ' ₄) C, wherein C _LSBBe the summation of low level CDAC 103 electric capacity, " || " expression is in parallel.Ideally, C _S|| C _LSBValue should equal a specific capacitance C, but because C _SItself be exactly a specific capacitance, so C _S|| C _LSBValue can depart from a specific capacitance, this error is with Δ C ' ₄Expression.In addition, define again Δ C _Tol=Δ C ' ₄+ Δ C ₄+ Δ C ₅+ Δ C ₆+ Δ C ₇+ Δ C ₈

After circuit powers on, at first carry out self calibration, this step is for the corresponding residual error voltage of each electric capacity of high-order CDAC 101 is all quantized out, again by certain computing obtain everybody error voltage and be stored in the memory, the memory here can be random asccess memory (RAM, Random AccessMemory).

The highest order C of self-correcting from high-order CDAC 101 ₈Beginning, Fig. 3 is for quantizing C ₈Residual error voltage V _R8The process schematic diagram, V wherein _RefReference voltage, V _CmCommon-mode voltage, Under preceding state, C ₈Ground connection, all the other all electric capacity meet V _Ref, the in-phase input end of comparator 105 and inverting input all meet V _Cm, the output of calibrating simultaneously DAC 104 also is V _Cm, the electric charge on comparator 105 inverting inputs is at this moment

Q＝V _cmC ₈+(V _cm-V _ref)(C′ ₄+C ₄+…+C ₇)

；

＝V _cm(2 ⁴+ΔC ₈)C+(V _cm-V _ref)(2 ⁴+ΔC′ ₄+ΔC ₄+…+ΔC ₇)C

At next state, C ₈Meet V _Ref, all the other all capacity earths, calibration DAC 104 is output as V _Cal8,

The voltage of comparator 105 inverting inputs is V _X, the electric charge on comparator 105 inverting inputs is at this moment

Q′＝(V _X-V _ref)C ₈+V _X(C′ ₄+C ₄+…+C ₇)+(V _X-V _cal)C _C

；

＝(V _X-V _ref)(2 ⁴+ΔC ₈)C+V _X(2 ⁴+ΔC′ ₄+ΔC ₄+…+ΔC ₇)C+(V _X-V _cal8)KC

Because charge conservation, Q=Q ' can obtain thus

$(2^5+K+{\mathrm{\ΔC}}_{\mathrm{tol}})(V_{\mathrm{cm}}-V_X)=K[V_{\mathrm{cm}}+\frac{V_{\mathrm{ref}}}{K}({\mathrm{\ΔC}}_4^{\′}+{\mathrm{\ΔC}}_4+...+{\mathrm{\ΔC}}_7-{\mathrm{\ΔC}}_8)-V_{\mathrm{cal}8}]$

Utilize one in the control circuit 9 successive approximation register of in calibration cycle, working (SAR, Successive Approximation), adopt the mode of approaching one by one, can be with C ₈Corresponding residual error voltage quantizes.When quantizing to finish, V _Cm≈ V _X, so

$V_{\mathrm{cal}8}=V_{\mathrm{cm}}+\frac{V_{\mathrm{ref}}}{K}({\mathrm{\ΔC}}_4^{\′}+...+{\mathrm{\ΔC}}_7-{\mathrm{\ΔC}}_8)$

C ₈Residual error voltage be exactly V _Cal8With V _CmPoor, namely With it divided by 2 with regard to the error voltage that obtains highest order be again

Above two steps operation all is to finish with the mode of numeral.But relate to the computing divided by 2 in the superincumbent computing, a binary number is equivalent to it is moved to right one divided by 2, this can bring certain error.Such as, the binary number 011 of decimal number 3 correspondences is obtained 001 after 2, and the decimal number of 001 correspondence is 1.That is to say, carry out 3 divided by after 2 the computing with the mode of numeral, the result who obtains is 1, so just produced error.The error of bringing when reducing the digital code computing is mended two in the back, position, residual error voltage digital code end of calibration DAC 104 outputs and is participated in together computing, and these two all are preset as 0.Like this, certain binary number is retained divided by the information that may lose in 2 o'clock to a certain extent, thereby has improved the precision of computing.Residual error voltage and error voltage are all expressed and computing with complement code.

Utilize identical method, can obtain successively C ₇, C ₆, C ₅, C ₄Corresponding residual error voltage and error voltage.When needs quantized the residual error voltage of certain electric capacity, this electric capacity is first ground connection under former and later two states, meets V again _RefAll electric capacity that figure place is lower than this electric capacity (comprise C ' ₄) then meet first V _Ref, ground connection again; And figure place than high all electric capacity of this electric capacity former and later two states next directly.Below be C ₇, C ₆, C ₅, C ₄Expression formula Deng four corresponding error voltages of electric capacity:

$V_{e7}=\frac{V_{r7}-V_{e8}}{2}=\frac{V_{\mathrm{ref}}}{4K}({\mathrm{\ΔC}}_4^{\′}+...+{\mathrm{\ΔC}}_6-{3\mathrm{\ΔC}}_7+{\mathrm{\ΔC}}_8);$

${\mathrm{<figure-callout\; id="6"\; label="V\; e"\; filenames="HDA0000029924630000051.png"\; state="\{\{state\}\}">V</figure-callout>}}_e=\frac{V_{r6}-V_{e7}-V_{e8}}{2}=\frac{V_{\mathrm{ref}}}{8K}({\mathrm{\&Delta;C}}_4^{\&prime;}+...+{\mathrm{\&Delta;C}}_5-7{\mathrm{\&Delta;<figure-callout\; id="6"\; label="C"\; filenames="HDA0000029924630000051.png"\; state="\{\{state\}\}">C</figure-callout>}}_6+{\mathrm{\&Delta;C}}_7+{\mathrm{\&Delta;C}}_8);$

$V_{e5}=\frac{V_{r5}-V_{e6}-V_{e7}-V_{e8}}{2}=\frac{V_{\mathrm{ref}}}{16K}({\mathrm{\&Delta;C}}_4^{\&prime;}+{\mathrm{\&Delta;C}}_4-15{\mathrm{\&Delta;C}}_5+{\mathrm{\&Delta;<figure-callout\; id="6"\; label="C"\; filenames="HDA0000029924630000051.png"\; state="\{\{state\}\}">C</figure-callout>}}_6+...+{\mathrm{\&Delta;C}}_8);$

$V_{e4}=\frac{V_{r4}-V_{e5}-V_{e6}-V_{e7}-V_{e8}}{2}=\frac{V_{\mathrm{ref}}}{32K}({\mathrm{\&Delta;C}}_4^{\&prime;}-31{\mathrm{\&Delta;C}}_4+{\mathrm{\&Delta;C}}_5+...+{\mathrm{\&Delta;C}}_8).$

Can find out from top expression formula, corresponding 5 error voltages of high 5 CDAC had both comprised the matching error between each electric capacity, i.e. Δ C among the high-order CDAC 101 ₄～Δ C ₈, comprised again the systematic error that high-order CDAC 101 and low level CDAC 103 is coupled and introduces with specific capacitance, i.e. Δ C ' ₄Matching error and systematic error also can exert an influence to low level except meeting exerts an influence to a high position.In bearing calibration proposed by the invention, the computational methods of the error voltage of low level also are provided, formula is as follows:

${\mathrm{<figure-callout\; id="3"\; label="V\; e"\; filenames="HDA0000029924630000012.png"\; state="\{\{state\}\}">V</figure-callout>}}_e=\frac{V_{e4}-V_{r4}}{2},$ $V_{\mathrm{ei}}=\frac{1}{2}{V}_{e(i+1)},i=\mathrm{0,1,2}$

Like this, all 9 corresponding error voltages have been obtained.But, only have front 6 error voltage to be stored among the RAM, because rear 3 error voltage all equals the error voltage of last position divided by 2, as long as therefore known V _C3, the error voltage that the back is several just can both obtain.

After calibration cycle finished, circuit entered the dormancy wait state.After enabling signal arrived, circuit began to enter the normal change-over period.At first, need to be to the input analog signal sampling, during sampling, all electric capacity of main DAC all meet input signal V _In, the in-phase input end of comparator 105 meets V _Cm, inverting input is output as V with output short circuit, calibration DAC 104 _Cm, the top crown of low level CDAC 103 all electric capacity is also received V among the main DAC _Cm, as shown in Figure 4.At this moment, the electric charge on X point and the Y point is respectively among the figure:

Q _X＝(V _cm-V _in)(C ₄+…+C ₈)＝(V _cm-V _in)(2 ⁵-1+ΔC ₄+…+ΔC ₈)C；

Q _Y＝(V _cm-V _in)(C′ ₀+…+C ₃)＝(V _cm-V _in)2 ⁴C。

Next, a SAR of 9 who enables in cycle in normal conversion in the control circuit starts working, and according to the output of this SAR, each electric capacity among the main DAC is connected on the different current potentials.For each electric capacity of low level CDAC 103, if corresponding position is 1, then this electric capacity is received V _Ref, otherwise it is received ground; For each electric capacity of high-order CDAC 101, if corresponding position is 1, then this electric capacity is received V _Ref, otherwise it is received ground.Simultaneously, error voltage V corresponding to calibration DAC 104 outputs _eWith V _CmAnd, the in-phase input end of comparator 105 meets V _CmAs shown in Figure 5, this figure is an example, a kind of situation that indication circuit may occur when normal conversion.

At this moment, the electric charge on the Y point becomes: (following formula V _YAnd V _XRespectively the voltage that Y point and X are ordered)

Q′ _Y＝(V _Y-V _ref)(D ₀C+…+D ₃2 ³C)+V _Y[(1-D ₀)C+…+(1-D ₃)2 ³C]

；

+V _YC+(V _Y-V _X)C _S

Since charge conservation, Q _Y=Q ' _Y, can obtain thus:

$V_Y=\frac{15-{\mathrm{\&Delta;C}}_4^{\&prime;}}{16}[V_{\mathrm{cm}}-V_{\mathrm{in}}+V_{\mathrm{ref}}(\frac{{\mathrm{<figure-callout\; id="3"\; label="D"\; filenames="HDA0000029924630000012.png"\; state="\{\{state\}\}">D</figure-callout>}}_3}{2}+...+\frac{{\mathrm{<figure-callout\; id="0"\; label="D"\; filenames="HDA0000029924630000042.png,HDA0000029924630000051.png"\; state="\{\{state\}\}">D</figure-callout>}}_0}{2^4})]+\frac{1+{\mathrm{\&Delta;C}}_4^{\&prime;}}{16}{V}_X$

Electric charge on the X point then becomes:

Q′ _X＝(V _X-V _ref)(D ₄C ₄+…+D ₈C ₈)+V _X[(1-D ₄)C ₄+…+(1-D ₈)C ₈]

；

+(V _X-V _Y)C _S+(V _X-V _cm-V _e)C _C

Since charge conservation, Q _X=Q ' _X, again with V _YThe expression formula substitution after can obtain:

$\begin{array}{c}{V}_{\mathrm{in}}-\frac{V_{\mathrm{ref}}[D_4(1+{\mathrm{\&Delta;C}}_4)+...+D_8(2^4+{\mathrm{\&Delta;C}}_8)+(1+{\mathrm{\&Delta;C}}_4^{\&prime;})(\frac{{\mathrm{<figure-callout\; id="3"\; label="D"\; filenames="HDA0000029924630000012.png"\; state="\{\{state\}\}">D</figure-callout>}}_3}{2}+...+\frac{{\mathrm{<figure-callout\; id="0"\; label="D"\; filenames="HDA0000029924630000042.png,HDA0000029924630000051.png"\; state="\{\{state\}\}">D</figure-callout>}}_0}{2^4})]+{\mathrm{KV}}_e}{2^5+{\mathrm{\&Delta;C}}_{\mathrm{tol}}}\\ =\frac{2^5+K+{\mathrm{\&Delta;C}}_{\mathrm{tol}}}{2^5+{\mathrm{\&Delta;C}}_{\mathrm{tol}}}(V_{\mathrm{cm}}-V_X)\end{array}$

And in the following formula

D _iBeing a certain value of 9 SAR output, namely is which position is 1, and just the error voltage with which correspondence adds up.In the practical work process of circuit, after being added up, the error voltage digital code needs to give up again last two.With V _EiExpression formula generation enter, just can obtain:

This shows, through after the self-correcting, the final so that output voltage of input voltage and 9 DAC of an ideal compares, if input voltage greater than the output voltage of desirable DAC, comparator 105 is exported high level so, on the contrary comparator 105 output low levels.And the matching error between high-order CDAC 101 electric capacity and the coupling capacitance C of unit _SThe systematic error of introducing all has been eliminated.

In addition, it can also be seen that the coupling capacitance C between calibration DAC 104 and the main DAC from above derivation _CSize do not affect the realization of algorithm.C _CLarger, namely K is larger, can be so that the scope of the matching error that circuit can be processed increase, but can reduce simultaneously the equivalent precision of calibration DAC.Can get C _CEqual the size of a specific capacitance, i.e. K=1.

Embodiment two: for the precision that improves analog to digital converter and guarantee certain monotonicity, main DAC can also comprise the middle M position RDAC that is made of resistance string, its structural representation as shown in Figure 6, comprise CDAC high 5 among the main DAC 101, middle 3 RDAC 102, hang down 4 CDAC 103, and 9 are calibrated DAC 104 and comparator 105.

In RDAC 102, V _RiThe closely voltage of current potential one end of certain resistance in the resistance string (determined by 3-8Decoder A, the input signal of 3-8DecoderA is D4, D5, D6), V _Ri+1That certain resistance in the resistance string (determined by 3-8Decoder B, the input signal of 3-8Decoder B is D4, D5, D6) is near V _RefThe voltage of one end.Therefore, V _RiAnd V _Ri+1Be respectively:

$V_{\mathrm{Ri}}=V_{\mathrm{ref}}(\frac{{\mathrm{<figure-callout\; id="6"\; label="D"\; filenames="HDA0000029924630000051.png"\; state="\{\{state\}\}">D</figure-callout>}}_6}{2}+\frac{D_5}{4}+\frac{D_4}{8}),V_{\mathrm{Ri}+1}=V_{\mathrm{Ri}}+\frac{V_{\mathrm{ref}}}{2^3}.$

The scheme of dividing three sections realizations for main DAC, the operation principle of circuit are identical when dividing two sections to realize with process with main DAC.Each electric capacity of supposing high-order CDAC 101 is respectively:

C ₁₁=(2 ⁴+ Δ C ₁₁) C, C ₁₀=(2 ³+ Δ C ₁₀) C, C ₉=(2 ²+ Δ C ₉) C, C ₈=(2+ Δ C ₈) C, C ₇=(1+ Δ C ₇) C, wherein Δ C _iBe the error of each electric capacity, C is specific capacitance.

Each electric capacity of supposing low level CDAC 103 is respectively: C ₃=2 ³C, C ₂=2 ²C, C ₁=2C, C ₀=C ' ₀=C.

Suppose that the coupling capacitance between calibration DAC 104 and the main DAC is: C _C=KC, wherein K is a constant.

Except above hypothesis, definition C ' ₇=C _S|| C _LSB=C _S|| 16C=(1+ Δ C ' ₇) C, wherein C _LSBIt is the summation of low level CDAC 103 electric capacity.Ideally, C _S|| C _LSBValue should equal a specific capacitance C, but because C _SItself be exactly a specific capacitance, so C _S|| C _LSBValue can depart from a specific capacitance, this error is with Δ C ' ₇Expression.In addition, define again Δ C _Tol=Δ C ' ₇+ Δ C ₇+ Δ C ₈+ Δ C ₉+ Δ C ₁₀+ Δ C ₁₁

After the self calibration stage finishes, obtain everybody corresponding error voltage and be respectively:

$V_{e11}=\frac{V_{r11}}{2}=\frac{V_{\mathrm{ref}}}{2K}({\mathrm{\&Delta;C}}_7^{\&prime;}+...+{\mathrm{\&Delta;C}}_{10}-{\mathrm{\&Delta;C}}_{11});$

${\mathrm{<figure-callout\; id="10"\; label="V\; e"\; filenames="HDA0000029924630000051.png"\; state="\{\{state\}\}">V</figure-callout>}}_e=\frac{V_{r10}-V_{e11}}{2}=\frac{V_{\mathrm{ref}}}{4K}({\mathrm{\&Delta;C}}_7^{\&prime;}+...+{\mathrm{\&Delta;C}}_9-3{\mathrm{\&Delta;<figure-callout\; id="10"\; label="C"\; filenames="HDA0000029924630000051.png"\; state="\{\{state\}\}">C</figure-callout>}}_{10}+{\mathrm{\&Delta;C}}_{11});$

$V_{e9}=\frac{V_{r9}-V_{e10}-V_{e11}}{2}=\frac{V_{\mathrm{ref}}}{8K}({\mathrm{\&Delta;C}}_7^{\&prime;}+...+{\mathrm{\&Delta;C}}_8-7{\mathrm{\&Delta;C}}_9+{\mathrm{\&Delta;<figure-callout\; id="10"\; label="C"\; filenames="HDA0000029924630000051.png"\; state="\{\{state\}\}">C</figure-callout>}}_{10}+{\mathrm{\&Delta;C}}_{11});$

$V_{e8}=\frac{V_{r8}-V_{e9}-V_{e10}-V_{e11}}{2}=\frac{V_{\mathrm{ref}}}{16K}({\mathrm{\&Delta;C}}_7^{\&prime;}+{\mathrm{\&Delta;C}}_7-15{\mathrm{\&Delta;C}}_8+{\mathrm{\&Delta;C}}_9+...+{\mathrm{\&Delta;C}}_{11});$

$V_{e7}=\frac{V_{r7}-V_{e8}-V_{e9}-V_{e10}-V_{e11}}{2}=\frac{V_{\mathrm{ref}}}{32K}({\mathrm{\&Delta;C}}_7^{\&prime;}-31{\mathrm{\&Delta;C}}_7+{\mathrm{\&Delta;C}}_8+...+{\mathrm{\&Delta;C}}_{11});$

${\mathrm{<figure-callout\; id="6"\; label="V\; e"\; filenames="HDA0000029924630000051.png"\; state="\{\{state\}\}">V</figure-callout>}}_e=\frac{V_{e7}-V_{r7}}{2};$

$V_{\mathrm{ei}}=\frac{1}{2}{V}_{e(i+1)},$ i＝0，1，2，3，4，5。

Enter normal conversion after the stage, at first input signal is sampled, during sampling, all electric capacity of main DAC all meet input signal V _In, the in-phase input end of comparator 105 meets V _Cm, inverting input is output as V with output short circuit, calibration DAC 104 _Cm, the top crown of low level CDAC 103 all electric capacity is also received V among the main DAC _Cm, as shown in Figure 7.At this moment, the electric charge on X point and the Y point is respectively among the figure:

Q _X＝(V _cm-V _in)(C ₇+…+C ₁₁)＝(V _cm-V _in)(2 ⁵-1+ΔC ₇+…+ΔC ₁₁)C；

Q _Y＝(V _cm-V _in)(C′ ₀+…+C ₃)＝(V _cm-V _in)2 ⁴C。

Next, a successive approximation register of 12 that enables in the cycle in normal conversion is started working, and according to the output of this SAR, each electric capacity among the main DAC is connected on the different current potentials.For each electric capacity of low level CDAC 103, if corresponding position is 1, then this electric capacity is received V _Ri+1, otherwise it is received V _RiFor each electric capacity of high-order CDAC 101, if corresponding position is 1, then this electric capacity is received V _Ref, otherwise it is received ground.Simultaneously, error voltage V corresponding to calibration DAC 104 outputs _eWith V _CmAnd, the in-phase input end of comparator 105 meets V _Cm, as shown in Figure 8.

At this moment, the electric charge on the Y point becomes: (following formula V _YAnd V _XRespectively the voltage that Y point and X are ordered)

Q′ _Y＝(V _Y-V _Ri+1)(D ₀C+…+D ₃2 ³C)+(V _Y-V _Ri)[(1-D ₀)C+…+(1-D ₃)2 ³C]

；

+(V _Y-V _Ri)C+(V _Y-V _X)C _S

Since charge conservation, Q _Y=Q ' _Y, can obtain thus:

$V_Y=\frac{15-{\mathrm{\&Delta;C}}_7^{\&prime;}}{16}[V_{\mathrm{cm}}-V_{\mathrm{in}}+V_{\mathrm{ref}}(\frac{{\mathrm{<figure-callout\; id="6"\; label="D"\; filenames="HDA0000029924630000051.png"\; state="\{\{state\}\}">D</figure-callout>}}_6}{2}+...+\frac{{\mathrm{<figure-callout\; id="0"\; label="D"\; filenames="HDA0000029924630000042.png,HDA0000029924630000051.png"\; state="\{\{state\}\}">D</figure-callout>}}_0}{2^7})]+\frac{1+{\mathrm{\&Delta;C}}_7^{\&prime;}}{16}{V}_X$

Electric charge on the X point then becomes:

Q′ _X＝(V _X-V _ref)(D ₇C ₇+…+D ₁₁C ₁₁)+V _X[(1-D ₇)C ₇+…+(1-D ₁₁)C ₁₁]

；

+(V _X-V _Y)C _S+(V _X-V _cm-V _e)C _C

Since charge conservation, Q _X=Q ' _X, again with V _YThe expression formula substitution after can obtain:

$V_{\mathrm{in}}-\frac{V_{\mathrm{ref}}[D_7(1+{\mathrm{\&Delta;C}}_7)+...+D_{11}(2^4+{\mathrm{\&Delta;C}}_{11})+(1+{\mathrm{\&Delta;C}}_7^{\&prime;})(\frac{{\mathrm{<figure-callout\; id="6"\; label="D"\; filenames="HDA0000029924630000051.png"\; state="\{\{state\}\}">D</figure-callout>}}_6}{2}+...+\frac{{\mathrm{<figure-callout\; id="0"\; label="D"\; filenames="HDA0000029924630000042.png,HDA0000029924630000051.png"\; state="\{\{state\}\}">D</figure-callout>}}_0}{2^7})]-{\mathrm{KV}}_e}{2^5+{\mathrm{\&Delta;C}}_{\mathrm{tol}}}$

$=\frac{2^5+K+{\mathrm{\&Delta;C}}_{\mathrm{tol}}}{2^5+{\mathrm{\&Delta;C}}_{\mathrm{tol}}}(V_{\mathrm{cm}}-V_X)$

In the following formula

D _iBeing a certain value of 12 SAR output, namely is which position is 1, and just the error voltage with which correspondence adds up.In the practical work process of circuit, after being added up, the error voltage digital code needs to give up again last two.With V _EiExpression formula generation enter, just can obtain:

$V_{\mathrm{in}}-V_{\mathrm{ref}}(\frac{D_{11}}{2}+...+\frac{{\mathrm{<figure-callout\; id="0"\; label="D"\; filenames="HDA0000029924630000042.png,HDA0000029924630000051.png"\; state="\{\{state\}\}">D</figure-callout>}}_0}{2^{12}})=\frac{2^5+K+{\mathrm{\&Delta;C}}_{\mathrm{tol}}}{2^5+{\mathrm{\&Delta;C}}_{\mathrm{tol}}}(V_{\mathrm{cm}}-V_X).$

This shows, through after the self-correcting, the final so that output voltage of input voltage and 12 DAC of an ideal compares, if input voltage greater than the output voltage of desirable DAC, comparator 105 is exported high level so, on the contrary comparator 105 output low levels.And the matching error between high-order CDAC 101 electric capacity and the coupling capacitance C of unit _SThe systematic error of introducing all has been eliminated.

Circuit for the main DAC that comprises the middle M position RDAC that is made of resistance string carries out emulation, obtain with self calibration with not with when calibration circuit differential nonlinearity DNL (Differential Nonlinearity) and the simulation result of integral nonlinearity INL (Integral Nonlinearity) and signal to noise ratio snr (Signal to NoiseRatio) and number of significant digit ENOB (Effective Number of Bits), such as Fig. 9, Figure 10, shown in Figure 11.

In emulation, each electric capacity of the high-order CDAC 101 of main DAC is respectively: C ₁₁=2 ⁴(1+mis), C ₁₀=2 ³(1-mis), C ₉=2 ²(1-mis), C ₈=2 (1-mis), C ₇=1-mis.The mis here represents the error of electric capacity.

Each electric capacity of low level CDAC 103 is respectively: C ₃=2 ³(1+mis), C ₂=2 ²(1-mis), C ₁=2 (1-mis), C ₀=C ' ₀=1-mis.

Coupling capacitance between high-order CDAC 101 and the low level CDAC 103 is: C _S=1-mis.

When DNL and INL were carried out emulation, mis=13 ‰, and during the band self calibration, DNL and INL all in ± 0.5LSB, illustrate that the precision of circuit is enough to meet the demands; If do not carry out self calibration, then DNL and INL respectively up to 60LSB and ± 30LSB, at this moment circuit complete failure.When SNR and ENOB were carried out emulation, mis changed to 13 ‰ by 0, and during the band self calibration, all more than 73.4dB, corresponding ENOB is all more than 11.9bit for SNR; If do not carry out self calibration, then SNR and ENOB can sharply reduce along with the increase of mismatch, and when mis=13 ‰, SNR and ENOB only have respectively 41.6dB and 6.6bit.

Above example only is preferred example of the present invention, and use of the present invention is not limited to this example, and is within the spirit and principles in the present invention all, any modification of making, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (2)

1. the processing method with the gradually-appoximant analog-digital converter of figure adjustment is characterized in that, comprises the steps:

Step 1: after circuit powers on, first the residual error voltage of high K position each electric capacity of CDAC quantized successively by the order from a high position to the low level, corresponding electric capacity first ground connection under the control of clock connects reference voltage again, than all low electric capacity of this electric capacity figure place, all electric capacity that comprise low N position CDAC, then connect first again ground connection of reference voltage, and than high all electric capacity one of this electric capacity figure place directly, the output of comparator is controlled the SAR in the control circuit, and the output of SAR connects the input of calibration DAC, when quantizing to finish, the output voltage of calibration DAC is exactly the residual error voltage of corresponding electric capacity with the difference of common-mode voltage;

Step 2: the error voltage of highest order equals the residual error voltage of highest order divided by 2;

The residual error voltage that every corresponding error voltage in the high K position except highest order equals this deducts than this high every error voltage sum again divided by 2;

The error voltage that the error voltage of N position equals the N+1 position deducts the residual error voltage of N+1 position again divided by 2;

Equal than this high one error voltage divided by 2 from the 1st error voltage every to the N-1 position;

Conversion from residual error voltage to error voltage is to carry out in the mode of numeral, and participates in together computing two of the residual error voltage digital code end of calibration DAC output back, position increases, and these two all are preset as 0;

Step 3: when carrying out normal conversion, equal 1 every corresponding error voltage digital code and added up and give up again last two, as the input of calibration DAC;

Described gradually-appoximant analog-digital converter comprises main DAC, calibration DAC, comparator, control circuit and memory, the positive input termination common-mode voltage of comparator, the output of negative input termination master DAC, it is characterized in that, described main DAC comprises the high K position CDAC of capacitor array formation and the low N position CDAC that capacitor array consists of, and be coupled by a specific capacitance between high K position CDAC and the low N position CDAC, be coupled by a coupling capacitance between the output of calibration DAC and the output of main DAC.

2. the processing method with the gradually-appoximant analog-digital converter of figure adjustment is characterized in that, comprises the steps:

Step 1: after circuit powers on, first the residual error voltage of high K position each electric capacity of CDAC quantized successively by the order from a high position to the low level, corresponding electric capacity first ground connection under the control of clock connects reference voltage again, than all low electric capacity of this electric capacity figure place, all electric capacity that comprise low N position CDAC, then connect first again ground connection of reference voltage, and than high all electric capacity one of this electric capacity figure place directly, the output of comparator is controlled the SAR in the control circuit, and the output of SAR connects the input of calibration DAC, when quantizing to finish, the output voltage of calibration DAC is exactly the residual error voltage of corresponding electric capacity with the difference of common-mode voltage;

Step 2: the error voltage of highest order equals the residual error voltage of highest order divided by 2;

The residual error voltage that every corresponding error voltage in the high K position except highest order equals this deducts than this high every error voltage sum again divided by 2;

The error voltage that the error voltage of M+N position equals the M+N+1 position deducts the residual error voltage of M+N+1 position again divided by 2;

Equal than this high one error voltage divided by 2 from the 1st error voltage every to the M+N-1 position;

Conversion from residual error voltage to error voltage is to carry out in the mode of numeral, and participates in together computing two of the residual error voltage digital code end of calibration DAC output back, position increases, and these two all are preset as 0;

Step 3: when carrying out normal conversion, equal 1 every corresponding error voltage digital code and added up and give up again last two, as the input of calibration DAC;

Described gradually-appoximant analog-digital converter comprises main DAC, calibration DAC, comparator, control circuit and memory, the positive input termination common-mode voltage of comparator, the output of negative input termination master DAC, it is characterized in that, described main DAC comprises the high K position CDAC of capacitor array formation and the low N position CDAC that capacitor array consists of, and be coupled by a specific capacitance between high K position CDAC and the low N position CDAC, be coupled by a coupling capacitance between the output of calibration DAC and the output of main DAC;

Described main DAC also comprises the middle M position RDAC that is made of resistance string.

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