WO2016127824A1

WO2016127824A1 - Binary capacitor array applied to single-terminal sar adc and redundancy calibrating method therefor

Info

Publication number: WO2016127824A1
Application number: PCT/CN2016/072559
Authority: WO
Inventors: 吴建辉; 林志伦; 杜媛; 陈超; 黄成�; 李红; 张萌
Original assignee: 东南大学
Priority date: 2015-02-10
Filing date: 2016-01-28
Publication date: 2016-08-18
Also published as: CN104639164A; CN104639164B

Abstract

Disclosed is a redundancy calibrating method for a binary capacitor array applied to a single-terminal SAR ADC. The method can be used for calibrating a dynamic error of the binary capacitor array caused by incomplete establishment. The method comprises a redundantly calibrated binary capacitor array, a comparer, an SAR logical control module and an output code computation module. The redundantly calibrated binary capacitor array comprises a binary capacitor array and an addition redundancy capacitor and a subtraction redundancy capacitor. According to the calibration method, a redundancy capacitor is inserted on the basis of a binary capacitor DAC array to realize that multiple digital codes correspond to one ADC analog input; whether an error exists is detected during redundant bit conversion; the addition redundancy capacitor or the subtraction redundancy capacitor is operated according to corresponding situations to compensate for the generated error.

Description

Binary capacitor array for single-ended SAR ADC and its redundancy calibration method

Technical field

The invention relates to a binary capacitor array redundancy calibration method applied to a single-ended SAR ADC, belonging to a SAR ADC calibration technique.

Background technique

High-precision SAR ADCs (Serial Approximation Register Type Analog-to-Digital Converters) require a large unit capacitance due to their thermal noise-to-performance limitations, and the equivalent capacitance at the comparator input is large. The establishment time is thus limited and difficult to improve. And because the large capacitance is prone to incomplete establishment, the comparator is misjudged to generate dynamic error, which affects the overall linearity of the SAR ADC.

Although traditional non-binary capacitor arrays can achieve redundant calibration, allowing the establishment of dynamic errors caused by incompleteness, increasing the speed of SAR ADCs, but requiring an additional number of conversion cycles, and non-binary capacitor arrays require ROM to record each bit. The weight, and the complex calculation of the final output code, greatly increases the complexity of the system, and the non-binary capacitor array is difficult to achieve matching design on the layout. In recent years, a binary-capacitor array redundancy algorithm with fully differential structure has been proposed, but its operation cannot be applied to a single-ended SAR ADC.

Summary of the invention

OBJECT OF THE INVENTION In order to overcome the deficiencies in the prior art, the present invention provides a single-ended SAR ADC binary capacitor array and a redundancy calibration method thereof, which combines the small complexity and small area advantages of SAR ADC single-ended operation, and Redundant calibration improves its accuracy and linearity performance.

Technical Solution: To achieve the above object, the technical solution adopted by the present invention is: a binary capacitor array applied to a single-ended SAR ADC, including an addition redundancy calibration capacitor and a subtraction redundancy calibration capacitor; the addition redundancy calibration capacitor and subtraction redundancy The remaining calibration capacitor is inserted after a certain bit Ci of the binary capacitor array, and the capacitance values of the two are the same as the Ci capacitor value, and the calibration range is the same as the voltage weight represented by Ci, which is:

Where: Vref is the reference power supply voltage; N is the total number of bits of the binary capacitor array; i is the number of bits of a certain Ci of the inserted binary capacitor array, i = (N-1) ~ 0; The number of bits of Ci is the number of bits when the addition redundancy calibration capacitor and the subtraction redundancy calibration capacitor are not considered;

The addition redundant calibration capacitor reference level reset state is connected in the same manner as the Ci reference level reset state, and the subtraction redundancy calibration capacitor reference level reset state connection mode and the addition redundancy calibration capacitance reference level reset The connection mode of the state is reversed, that is, the gnd of the subtractive redundancy calibration capacitor corresponds to the Vref of the addition redundancy calibration capacitor, and the subtraction method The Vref of the redundant calibration capacitor corresponds to the gnd of the additive redundancy calibration capacitor, and the subtraction operation is implemented by the opposite reference level operation.

The invention also provides a redundancy calibration method implemented by a binary capacitor array applied to a single-ended SAR ADC, and the specific steps are as follows:

Step 1: resetting the addition redundancy capacitor and the subtraction redundancy capacitor, that is, the lower plate of the addition redundancy capacitor is connected to the switch of the gnd, and the lower plate of the subtraction redundancy capacitor is connected to the switch of the Vref; Sampling of binary capacitors other than redundant capacitors and subtractive redundant capacitors;

Step 2: Convert the capacitance of the binary capacitor array in order from the high level to the low level. When converting to the i-th bit Ci where the calibration capacitor is located, if the output result of the Ci bit comparator is 1, the next conversion is switched to the addition redundancy calibration capacitor. , guess the additive redundant calibration capacitor, that is, the lower plate of the added redundant capacitor is connected from gnd to Vref, and the redundant calibration code bir can be obtained. If bir=1, the lower plate of the redundant capacitor is added. The connection is unchanged at Vref, and then the conversion of the i-1th bit is performed; if bir=0, the lower plate of the addition redundancy capacitor is connected to gnd, and then the i-1th bit is converted;

If the output of the i-th Ci comparator is 0, the Ci lower plate is connected to gnd, the next conversion is switched to the subtractive redundant calibration capacitor, and no operation is performed on the subtractive redundant calibration capacitor, and the redundancy calibration is directly obtained. The code biR, if biR=1, indicates that there is no error that needs to be subtracted, so there is no need to perform calibration, that is, the subtraction redundant calibration capacitor is connected at Vref, and then the i-1th bit is converted; if biR=0, There is an error that needs to be subtracted to eliminate, and thus the subtraction redundant calibration capacitor is decremented by one, and the lower plate of the subtractive redundant calibration capacitor is connected from Vref to gnd, and then the i-1th bit is converted;

Step 3: Converting the capacitors at the i-1th position and after;

Step 4. After all the conversion processes are finished, input the output of the comparator to the output code calculation module, perform calculation, and finally output the digital code of the ADC, where:

Di=bi+J;

Di is the total output result of the i-th Ci input to the output code calculation module, bi is the comparator output of the i-th Ci, and biR is the comparison of the addition redundant calibration capacitor and the subtractive redundancy calibration capacitor inserted after Ci The output of the device, J is the compensation coefficient of the Ci bit.

Further, the binary capacitors other than the addition redundant capacitor and the subtractive redundant capacitor are sampled as described in the first step, as follows: the switch of the capacitor upper board is closed, that is, the reference level Vcm connected to the comparator, which needs to be sampled. The lower plate of the capacitor is connected to the input signal Vin for sampling; after the sampling is finished, the upper plate switch connected to the capacitor of Vcm is turned off, and all the switches of the lower plate of the sampling capacitor are switched from the input signal Vin to gnd.

Further, the conversion method of the binary capacitor Ck other than the additive redundant capacitor and the subtractive redundant capacitor in the binary capacitor array is as follows:

(1) Obtain a digital code bk of Ck, k = (N-1) ~ 1;

(2) If bk=1, the Ck connection is unchanged at Vref; if bk=0, Ck is connected from Vref to gnd;

(3) Perform a "guess 1" operation on the next C(k-1), that is, connect the C(k-1) capacitor from gnd to Vref.

Advantageous Effects: The binary capacitor array redundancy calibration method applied to the single-ended SAR ADC provided by the present invention has the following advantages over the prior art:

1. Using the binary capacitor array redundancy calibration technology, compared with the traditional non-redundantly calibrated SAR ADC, it can calibrate the dynamic error caused by the incomplete DAC establishment during the conversion process, which is beneficial to improve the linearity of the SAR ADC. At the same time, the redundant calibration algorithm enables digital calibration of the capacitance mismatch without the need to introduce additional capacitance mismatch calibration capacitors.

2. Redundant calibration of capacitors using binary capacitor arrays saves conversions compared to traditional non-binary redundancy calibrations, and binary capacitor arrays are easy to match on the layout.

3, binary capacitor array redundancy calibration capacitor calibration algorithm, only need to add redundant calibration capacitors on the traditional SAR ADC, the corresponding control algorithm of the redundant calibration capacitor, and the output code calculation algorithm, the structural changes of the traditional SAR ADC are small, Easy to implement.

4. The single-ended binary capacitor array redundancy calibration algorithm proposed by the present invention combines the small complexity and small area advantages of SAR ADC single-ended operation, and improves the accuracy and linearity performance through redundant calibration. The calibration algorithm is also compatible. A pseudo differential structure SAR ADC to achieve a better supply voltage rejection ratio.

DRAWINGS

Figure 1 is a block diagram of a single-ended SAR ADC;

2 is a structural diagram of a 4-bit DAC redundant capacitor array applied to a single-ended SAR ADC according to the present invention;

Figure 3 is a 4-bit schematic diagram of a single-ended SAR ADC with no redundant calibration conversion process.

4 is a schematic diagram of a 4 bit diagram of a binary capacitor array redundancy calibration conversion process applied to a single-ended SAR ADC according to the present invention.

FIG. 5 is a flow chart of the binary capacitor array redundancy calibration operation applied to the single-ended SAR ADC of the present invention.

6 is a calculation diagram of a binary capacitor array redundancy calibration digital output applied to a single-ended SAR ADC according to the present invention.

FIG. 7 is a schematic diagram of a binary capacitor array redundancy calibration structure applied to a single-ended SAR ADC according to the present invention.

detailed description

The present invention will be further described below in conjunction with the accompanying drawings.

Figure 1. Block diagram of a single-ended SAR ADC, including sample-and-hold circuits, comparators, SAR logic, and DAC capacitor arrays. This structure is easy to understand and the following operating instructions will explain this structure. Where DAC is a binary capacitor array, its high and low reference The levels are Vref and Gnd.

2 is a structural diagram of a 4-bit DAC redundant capacitor array applied to a single-ended SAR ADC of the present invention, after adding a complementary redundancy calibration capacitor C1R+ and a subtractive redundancy calibration capacitor C1R- after a capacitor C1 of a 4-bit binary capacitor array.

Figure 3 is a 4-bit schematic diagram of a single-ended SAR ADC with no redundant calibration conversion process. The ordinate indicates the input analog signal of the comparator, the line corresponding to Vi is the input signal, that is, the positive input of the comparator, and the bent connecting line indicates the output signal of the DAC, that is, the negative end signal of the comparator. The abscissa represents the conversion process, the timeline. The bar represents the operation of the DAC capacitor for each conversion process. The black number below the abscissa indicates the output code of the comparator. The top of the ordinate represents the last digital output code.

Among them, (a) and (b) are the non-redundant calibration normal conversion when the highest bit <0 and the highest bit>0, respectively. (c) and (d) indicate an error conversion in which the highest-order comparator output is misjudged as 0, and an error conversion in which the highest-order comparator output is misjudged as 0. The conversion process of (a) to (d) is the same. Taking (a) as an example, the input signal is sampled and held at the beginning of the conversion process, and the DAC capacitor is reset. In the first conversion, the highest-order capacitor C3 is connected to Vref, so the DAC output is Vref/2 at this time, compared with the input signal, since Vi<Vdac(Vref/2), the comparator output is 0 at this time, the control is the highest. Bit capacitor C3 is connected back to Gnd, and the C2 capacitor is connected to Vref. At this time, the DAC output is Vref/4. For the comparator input Vi>Vdac(Vref/4), the comparator output is 1, keeping the C2 capacitor state, and C1 The capacitor is connected to Vref, the DAC output is Vref/4+Vref/8, for the comparator input Vi>Vdac(Vref/4+Vref/8), the comparator output is 1, the C1 capacitor state is maintained, and the C0 capacitor is connected to Vref. The DAC outputs Vref/4+Vref/8+Vref/16, the comparator input Vi>Vdac(Vref/4+Vref/8+Vref/16), and the comparator output 1 completes the conversion process. The digital output code is 0111. As can be seen from the figure, once the misjudgment is caused by the incomplete DAC establishment, the error will continue until the wrong digital code is output.

FIG. 7 is a schematic diagram of a binary capacitor array redundancy calibration structure applied to a single-ended SAR ADC according to the present invention, which is a schematic diagram of an algorithm for practical application. a redundant capacitor array, a comparator, a SAR logic control module, an output code calculation module, wherein the redundantly calibrated binary capacitor array includes an addition redundancy calibration capacitor CiR+ and a subtraction redundancy calibration capacitor CiR-; The remaining calibration capacitor CiR+ and the subtractive redundancy calibration capacitor CiR- are inserted after a certain bit Ci of the binary capacitor array, and the capacitance values of the two are the same as the Ci capacitance value, and the calibration range is the same as the voltage weight represented by Ci, which is:

The connection redundancy reset capacitor CiR+ reference level reset state is connected in the same manner as the Ci reference level reset state, and the subtraction redundancy calibration capacitor CiR-reference level reset state connection mode and the addition redundancy calibration capacitor CiR+ The reference level reset state is connected in the opposite way, that is, the gnd of the subtractive redundancy calibration capacitor CiR- corresponds to the Vref of the addition redundancy calibration capacitor CiR+, and the Vref of the subtraction redundancy calibration capacitor CiR- corresponds to the addition redundancy calibration capacitor CiR+ Gnd, through the opposite reference level operation to achieve the subtraction operation.

The redundancy calibration method implemented by the binary capacitor array applied to the single-ended SAR ADC is as follows:

Step 1. Reset the addition redundancy capacitor CiR+ and the subtraction redundancy capacitor CiR-, that is, the lower plate of the addition redundancy capacitor CiR+ is connected to the switch of gnd, and the lower plate of the subtraction redundancy capacitor CiR- is connected to the switch of Vref. Closing; sampling the binary capacitance except the addition redundancy capacitor CiR+ and the subtraction redundancy capacitor CiR-; closing the switch of the capacitor upper board, that is, the reference level Vcm connected to the comparator, the lower plate of the sampling capacitor is required Connected to the input signal Vin for sampling; after the sampling is finished, the upper plate switch connected to the Vcm capacitor is turned off, and all the switches of the lower plate of the sampling capacitor are switched from the input signal Vin to gnd.

Step 2: As shown in FIG. 5, the capacitance of the binary capacitor array is sequentially converted from the high level to the low level. When converting to the i-th bit Ci where the calibration capacitor is located, if the Ci bit comparator output result bi is 1, the next conversion Switch to the additive redundancy calibration capacitor CiR+ and “guess 1” the addition redundancy calibration capacitor CiR+, that is, connect the lower plate of the addition redundancy capacitor CiR+ from gnd to Vref to obtain the redundancy calibration code bir, if bir= 1, the lower plate of the addition redundancy capacitor CiR+ is connected to Vref and then the i-1th bit is converted; if bir=0, the lower plate of the addition redundancy capacitor CiR+ is connected to gnd, and then Perform the conversion of the i-1th bit;

If the output of the i-th Ci comparator is bi, the Ci lower plate is connected to gnd, the next conversion is switched to the subtractive redundant calibration capacitor CiR-, and the subtractive redundant calibration capacitor CiR- is not operated directly. The redundant calibration code biR is obtained. If biR=1, there is no error that needs to be subtracted, so there is no need to perform calibration. That is, the subtractive redundant calibration capacitor CiR- is connected to Vref and then the i-1th bit is converted. If biR=0, it indicates that there is an error that needs to be subtracted to eliminate, so the “reduce 1” operation is performed on the subtractive redundant calibration capacitor CiR-, and the lower plate of the subtractive redundant calibration capacitor CiR- is connected from Vref to gnd. Then perform the conversion of the i-1th bit;

Step 3: Converting the capacitors at the i-1th position and after;

Di=bi+J;

Di is the total output result of the i-th Ci input to the output code calculation module, bi is the comparator output of the i-th Ci, and biR is the addition redundancy calibration capacitor CiR+ and the subtractive redundancy calibration capacitor CiR inserted after Ci - Comparator output, J is the compensation coefficient of the Ci bit.

4 is a schematic diagram of a 4 bit diagram of a binary capacitor array redundancy calibration conversion process applied to a single-ended SAR ADC according to the present invention. Among them, (a) and (b) show that there is no misjudgment, and it can be seen that the input and the output correspond. (c) (d) The picture shows the case of misjudgment, and the input and output also correspond. The operation of the diagrams (a) to (d) needs to be combined with FIG. 5. FIG. 5 is a flow chart showing the operation of the present invention for redundant calibration of a binary capacitor array of a single-ended SAR ADC. Wherein: for this embodiment, i takes 1. In the figure, when the capacitor C1 is converted, if the comparator output b1=1 (as shown in (a) and (d)), the next conversion is switched to the addition redundancy calibration capacitor C1R+, and the addition redundancy calibration capacitor C1R+ is guessed. 1", the lower plate of the added redundant capacitor C1R+ is connected from gnd to Vref, and the redundant calibration code b1r can be obtained. If b1r=0 (as shown in (a)), the added redundant capacitor C1R+ The lower plate is connected to gnd, and then the 0th bit C0 is converted. In this case, no error is generated, so there is no need to compensate at the last output, and b1 and b0 are the correct ADC output codes. If b1r = 1 (as shown in (d)), the lower plate of the addition redundancy capacitor C1R+ is connected to Vref, and the conversion of the 0th bit C0 is performed. From (d), the benefits of redundant calibration can be seen. In (d) the situation shown in the figure is misjudged, and the final digital output can still be restored to the correct output. Since the DAC converted by the single-ended SAR ADC is actually performing the addition operation, when an error requiring addition compensation occurs, an additional detection phase is not required, and the ordinary SAR operation can automatically compensate the error.

When the error is the error that needs to be subtracted by the subtraction sampling, the operation of the ordinary single-ended SAR ADC does not meet the requirements, so an additional detection phase needs to be introduced to judge whether the error occurs. The error in which the addition or subtraction is cancelled can be easily distinguished by the comparator output code bi of the Ci bit.

(b) (c) shows the two conversion processes when b1=0. If b1=0, connect the C1 lower plate to gnd, the next conversion switches to the subtractive redundancy calibration capacitor C1R-, and does not perform any operation on the subtractive redundancy calibration capacitor C1R-, directly obtaining the redundant calibration code b1R, if b1R=1 (as shown in (b)), indicating that there is no error that needs to be subtracted, so there is no need to perform calibration, that is, the subtraction redundant calibration capacitor C1R- is connected to Vref, and then the 0th bit C0 is converted; If b1R=0 (as shown in Figure (c)), it indicates that there is an error that needs to be subtracted to eliminate it. Therefore, if the subtraction redundancy calibration capacitor C1R- is “minus 1”, the subtraction redundancy calibration capacitor C1R- will be The plate is connected from Vref to gnd, and then the 0th bit C0 is converted.

6 is a calculation diagram of a binary capacitor array redundancy calibration digital output applied to a single-ended SAR ADC according to the present invention. Due to the redundancy calibration, the output of the comparator is not equal to the final output. If you still look at the calculation according to the 4bit example, the compensation coefficient J is added to the output code b3, b2, b1, b0 of the comparator.

D1=b1+J, D1 is the total output result of the first C1 input to the output code calculation module, b1 is the comparator output of the first bit Ci, and b1R is the added redundancy calibration capacitor and subtraction after C1 The comparator output of the redundant calibration capacitor, J is the compensation factor of the C1 bit.

The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited to the above embodiments, but equivalent modifications or variations made by those skilled in the art according to the disclosure of the present invention should be incorporated. Within the scope of protection stated in the claims.

Claims

A binary capacitor array for a single-ended SAR ADC, comprising: an additive redundancy calibration capacitor (CiR+) and a subtractive redundancy calibration capacitor (CiR-); the addition redundancy calibration capacitor (CiR+) and a subtractive redundancy calibration The capacitor (CiR-) is inserted after a certain bit Ci of the binary capacitor array, and the capacitance values of the two are the same as the Ci capacitor value. The calibration range is the same as the voltage weight represented by Ci.

Where: Vref is the reference power supply voltage; N is the total number of bits of the binary capacitor array; i is the number of bits of a certain Ci of the inserted binary capacitor array, i = (N-1) ~ 0; The number of bits of Ci is the number of bits when the addition redundancy calibration capacitor and the subtraction redundancy calibration capacitor are not considered;

The connection redundancy reset capacitor (CiR+) reference level reset state is connected in the same manner as the Ci reference level reset state, and the subtraction redundancy calibration capacitor (CiR-) reference level reset state is connected and added. The remaining calibration capacitor (CiR+) reference level reset state is connected in the opposite way, that is, the gnd of the subtractive redundancy calibration capacitor (CiR-) corresponds to the Vref of the addition redundancy calibration capacitor (CiR+), and the subtraction redundancy calibration capacitor (CiR- The Vref corresponds to the gnd of the additive redundancy calibration capacitor (CiR+), and the subtraction operation is implemented by the opposite reference level operation.
A redundancy calibration method implemented by a binary capacitor array applied to a single-ended SAR ADC according to claim 1, wherein the specific steps are as follows:

Step 1: Reset the addition redundancy capacitor (CiR+) and the subtraction redundancy capacitor (CiR-), that is, the lower plate of the addition redundancy capacitor (CiR+) is connected to the gnd switch to close, and the subtractive redundancy capacitor (CiR-) The lower plate is connected to the switch of Vref to be closed; and the binary capacitance other than the added redundant capacitor (CiR+) and the subtractive redundant capacitor (CiR-) is sampled;

Step 2: Convert the capacitance of the binary capacitor array in order from the high level to the low level. When converting to the i-th bit Ci where the calibration capacitor is located, if the output result (bi) of the Ci bit comparator is 1, the next conversion is switched to the addition redundancy. The remaining calibration capacitor (CiR+), guess the additive redundant calibration capacitor (CiR+), that is, the lower plate of the additive redundant capacitor (CiR+) is connected from gnd to Vref, and the redundant calibration code bir can be obtained, if bir= 1, the lower plate of the additive redundant capacitor (CiR+) is connected to Vref and then the i-1th bit is converted; if bir=0, the lower plate of the added redundant capacitor (CiR+) is connected. Go to gnd and then convert the i-1th bit;

If the output of the i-th Ci comparator (bi) is 0, the Ci lower plate is connected to gnd, the next conversion is switched to the subtractive redundancy calibration capacitor (CiR-), and the subtractive redundancy calibration capacitor (CiR-) Without any operation, the redundant calibration code biR is directly obtained. If biR=1, there is no error that needs to be subtracted, so there is no need to perform calibration, that is, the subtractive redundant calibration capacitor (CiR-) is connected at Vref, and then Perform the conversion of the i-1th bit; if biR=0, it indicates that there is an error that needs to be subtracted to eliminate, so if the subtraction redundant calibration capacitor (CiR-) is decremented by 1, the subtractive redundant calibration capacitor (CiR-) The lower plate is connected from Vref to gnd, and then the i-1th bit is converted;

Step 3: Converting the capacitors at the i-1th position and after;

Step 4. After all the conversion processes are finished, input the output of the comparator to the output code calculation module, perform calculation, and finally output the digital code of the ADC, where:

Di=bi+J;

Di is the total output of the i-th Ci input to the output code calculation module, bi is the comparator output of the i-th Ci, biR is the additive redundant calibration capacitor (CiR+) and the subtractive redundancy calibration after Ci The comparator output of the capacitor (CiR-), J is the compensation coefficient of the Ci bit.
The binary capacitor array redundancy calibration method applied to a single-ended SAR ADC according to claim 2, wherein in step 1, the addition redundant capacitor (CiR+) and the subtractive redundancy capacitor (CiR-) are used. The binary capacitor sampling is as follows: the switch of the capacitor upper board is closed, that is, the reference level Vcm connected to the comparator, and the lower plate of the sampling capacitor is connected to the input signal Vin for sampling; after the sampling is finished, the connection is made. The upper plate switch to the capacitor of Vcm is disconnected, and all the switches of the lower plate of the sampling capacitor are switched from the input signal Vin to gnd.
A binary capacitor array redundancy calibration method for a single-ended SAR ADC according to claim 2, wherein the binary capacitor array has a binary other than the addition redundancy capacitor (CiR+) and the subtraction redundancy capacitor (CiR-) The conversion method of the capacitor Ck is as follows:

(1) Obtain a digital code bk of Ck, k = (N-1) ~ 1;

(2) If bk=1, the Ck connection is unchanged at Vref; if bk=0, Ck is connected from Vref to gnd;

(3) Perform a "guess 1" operation on the next C(k-1), that is, connect the C(k-1) capacitor from gnd to Vref.