CN110572158B

CN110572158B - Successive approximation ADC (analog to digital converter) capacitor array circuit and capacitor switch control method thereof

Info

Publication number: CN110572158B
Application number: CN201910984729.XA
Authority: CN
Inventors: 张俊; 邓红辉; 陈尚存; 尹勇生; 陈红梅
Original assignee: Hefei University of Technology
Current assignee: Hefei University of Technology
Priority date: 2019-10-16
Filing date: 2019-10-16
Publication date: 2022-08-30
Anticipated expiration: 2039-10-16
Also published as: CN110572158A

Abstract

The invention discloses a capacitor array circuit of a successive approximation ADC and a capacitor switch control method thereof. The invention can effectively reduce the dynamic power consumption of the capacitor array circuit and the establishment time of the capacitor in the switching process of the capacitor switch, thereby realizing high-speed and low-power consumption analog-to-digital conversion.

Description

Successive approximation ADC (analog to digital converter) capacitor array circuit and capacitor switch control method thereof

Technical Field

The invention belongs to the field of successive approximation type ADCs (analog to digital converters) in mixed signal circuit design, and particularly relates to a capacitor array circuit applied to the successive approximation type ADCs and a capacitor switch control method thereof.

Background

In modern information technology, an Analog-to-Digital Converter (ADC) is used as an important bridge for connecting an Analog signal and a Digital signal, and the performance of the ADC directly affects the performance of the whole signal processing system. Currently, with the rise of 5G mobile communication and the wide application of wearable devices, higher requirements are put on performances such as conversion speed and overall power consumption of the ADC. Therefore, the research on the ADC with high speed and low power consumption has great significance and value.

The successive approximation ADC has a simple overall structure, only contains a small number of analog modules compared with other types of ADCs, can well match the progress of the process and is suitable for occasions with low power consumption, and therefore the successive approximation ADC is widely concerned. However, the conversion speed of the conventional successive approximation ADC is not high due to the conventional binary conversion algorithm. In addition, in the successive approximation ADC, the power consumption of the capacitor array circuit and the comparator occupies most of the overall power consumption of the ADC, and cannot be reduced as the process advances. The two-bit per-cycle quantization structure can theoretically improve the conversion speed of the traditional successive approximation type ADC by two times, but at the same time, the power consumption of the whole ADC is increased, and the speed improvement is seriously limited in turn.

Disclosure of Invention

Aiming at the defects of low conversion speed and high power consumption of a capacitor array circuit of the traditional successive approximation ADC, the invention designs the capacitor array circuit of the successive approximation ADC and a capacitor switch control method thereof, so as to reduce the dynamic power consumption in the switching process of a capacitor switch by reasonably designing the weight of each capacitor in a capacitor array while effectively improving the overall conversion speed, thereby achieving the purpose of reducing the power consumption of the whole ADC.

The invention adopts the following technical scheme for solving the technical problems:

the invention relates to a capacitor array circuit of a successive approximation ADC (analog to digital converter), which is characterized by consisting of a capacitor array module and a capacitor switch module;

the capacitor array module comprises two capacitor arrays, namely a first capacitor array and a second capacitor array, wherein each capacitor array is composed of a positive end and a negative end, the two capacitor arrays are connected with three external comparators, the positive ends of the two capacitor arrays are respectively connected with the positive input ends of the first external comparator and the third external comparator, the negative ends of the two capacitor arrays are respectively connected with the negative input ends of the first external comparator and the third external comparator, the positive input end of the second external comparator is connected with the positive input end of the first external comparator, and the negative input end of the second comparator is connected with the negative input end of the third external comparator;

the capacitance switch module is composed of 4m capacitance switches, one end of each capacitance switch is a free end, the other end of each capacitance switch is a fixed end, wherein m is 2N-2, N is the resolution digit of the ADC and is an even number;

the positive end and the negative end of each capacitor array are respectively composed of m capacitors with weights, and the weights of the m capacitors are respectively (3 multiplied by 2) ⁰ )C、(1×2 ⁰ )C、(4×2 ⁰ )C、(4×2 ⁰ )C、(3×2 ² )C、(1×2 ² )C、(4×2 ² )C、(4×2 ² )C、…、(3×2 ⁱ )C、(1×2 ⁱ )C、(4×2 ⁱ )C、(4×2 ⁱ )C、…、(3×2 ^N-6 )C、(1×2 ^N-6 )C、(4×2 ^N-6 )C、(4×2 ^N-6 )C、(3×2 ^N ^-4 )C、(1×2 ^N-4 )C、(4×2 ^N-4 )C、(4×2 ^N-4 ) C, 3C, 1C, wherein C is a unit capacitance, i ═ 0, 2, 4, 6, 8, …, N-6, N-4;

one ends of m capacitors in the positive end are connected with a positive input end of an external comparator and a common-mode voltage end, and the other ends of the m capacitors are correspondingly connected with fixed ends of m capacitor switches respectively;

one ends of m capacitors in the negative end are connected with a negative input end of an external comparator and a common-mode voltage end, and the other ends of the m capacitors are correspondingly connected with fixed ends of m capacitor switches respectively;

taking a polar plate at one end of each capacitor connected with the external comparator as a top polar plate, and taking one end connected with the fixed end of the capacitor switch as a bottom polar plate;

the free ends of the capacitance switches corresponding to the capacitances with the weights of 3C and 1C are switched between the analog input signal end and the reference voltage end or switched between the analog input signal end and the ground end;

the free ends of the capacitance switches corresponding to the other m-2 capacitances are switched among the analog input signal end, the reference voltage end and the ground end;

under the control of different digital output signals of an external comparator, the capacitance switch module switches the connection state of the free end of the corresponding capacitance switch, so that the bottom plate of the capacitor is connected to different voltages.

The invention relates to a capacitance switch control method of a capacitance array circuit of a successive approximation ADC, which is characterized by comprising the following steps of:

step 1, connecting bottom plates of all capacitors in a capacitor array module with an analog input signal end, connecting a top plate with a common mode voltage end, and completing sampling of analog input signals by the bottom plates of the capacitors;

step 2, in a first quantization period, firstly disconnecting the positive and negative ends of the two capacitor arrays from the common-mode voltage end, and carrying out switching operation aiming at all the capacitor switches, wherein the operation comprises the following steps: the weights in the positive terminals of the first capacitor array are respectively (1 multiplied by 2) ⁰ )C、(4×2 ⁰ )C、(4×2 ⁰ )C、(1×2 ² )C、(4×2 ² )C、(4×2 ² )C、…、(1×2 ⁱ )C、(4×2 ⁱ )C、(4×2 ⁱ )C、…、(1×2 ^N-6 )C、(4×2 ^N-6 )C、(4×2 ^N-6 )C、(1×2 ^N-4 )C、(4×2 ^N-4 )C、(4×2 ^N-4 ) The bottom plates of the capacitors C and 3C are all connected with a reference voltage end, and the bottom plates of the other capacitors are all connected with a ground end, wherein i is 0, 2, 4, 6, 8, …, N-6 and N-4;

the weights of the negative terminals of the first capacitor array are (1 × 2) ⁰ )C、(4×2 ⁰ )C、(4×2 ⁰ )C、(1×2 ² )C、(4×2 ² )C、(4×2 ² )C、…、(1×2 ⁱ )C、(4×2 ⁱ )C、(4×2 ⁱ )C、…、(1×2 ^N-6 )C、(4×2 ^N-6 )C、(4×2 ^N-6 )C、(1×2 ^N-4 )C、(4×2 ^N-4 )C、(4×2 ^N-4 )C、The bottom plate of the capacitor of 3C is all grounded, and the bottom plates of the other capacitors are all connected with a reference voltage end, wherein i is 0, 2, 4, 6, 8, …, N-6 and N-4;

the weights in the positive terminals of the second capacitor arrays are respectively (3 multiplied by 2) ⁰ )C、(3×2 ² )C、…、(3×2 ⁱ )C、…、(3×2 ^N ^-6 )C、(3×2 ^N-4 ) The bottom plates of the capacitors C and 1C are all connected with a reference voltage end, and the bottom plates of the other capacitors are all connected with a ground end, wherein i is 0, 2, 4, 6, 8, …, N-6 and N-4;

the weights of the negative terminals of the second capacitor array are (3 x 2) ⁰ )C、(3×2 ² )C、…、(3×2 ⁱ )C、…、(3×2 ^N ^-6 )C、(3×2 ^N-4 ) The bottom plates of the capacitors C and 1C are all grounded, and the bottom plates of the other capacitors are all connected with a reference voltage end, wherein i is 0, 2, 4, 6, 8, …, N-6 and N-4;

and 3, after the switching is finished, utilizing three external comparators to respectively compare the voltage of the capacitor top plate with the quantization threshold generated in the first quantization period so as to generate and output two groups of complementary three-bit thermometer codes in the first quantization period, wherein the complementary outputs of the three external comparators are respectively CP ₂ /CN ₂ 、CP ₁ /CN ₁ 、CP ₀ /CN ₀ ；

Step 4, in the second quantization period, aiming at the weight of (3 multiplied by 2) ^N-4 )C、(1×2 ^N-4 )C、(4×2 ^N-4 )C、(4×2 ^N-4 ) C, the capacitance switch corresponding to the capacitor is switched, and the capacitance switch module is controlled according to four possible situations of the generated three-position thermometer code in the first quantization period;

step 4.1, if the three-digit thermometer code CP generated in step 4 ₂ CP ₁ CP ₀ To "000", an output CP of the first external comparator is used ₂ The weight in the positive end of the first capacitor array is controlled to be (3 multiplied by 2) ^N-4 ) C capacitor, making its bottom plate connected with reference voltage end and using another output CN of first external comparator ₂ Controlling the first capacitanceThe weight in the negative end of the array is (3 × 2) ^N-4 ) The bottom pole plate of the capacitor switch corresponding to the capacitor C is connected with the ground end;

using a set of outputs CP of three comparators simultaneously ₂ 、CP ₁ 、CP ₀ Respectively controlling the weight of the positive end of the second capacitor array to be (1 multiplied by 2) ^N-4 )C、(4×2 ^N-4 )C、(4×2 ^N-4 ) The capacitor switch corresponding to the capacitor C has its bottom plate connected to the reference voltage terminal and the other group of three comparators outputs CN ₂ 、CN ₁ 、CN ₀ Respectively controlling the weight of the negative terminal of the second capacitor array to be (1 x 2) ^N-4 )C、(4×2 ^N-4 )C、(4×2 ^N-4 ) The bottom pole plate of the capacitor switch corresponding to the capacitor C is connected with the ground end; and the connection state of the bottom plates of the other capacitors is kept unchanged;

step 4.2, if the three-digit thermometer code CP generated in step 4 ₂ CP ₁ CP ₀ To "100", an output CP of the first external comparator is used ₂ The weight in the positive end of the first capacitor array is controlled to be (1 multiplied by 2) ^N-4 ) C capacitor, the bottom plate of which is connected to ground, and the other output CN of the first external comparator ₂ The weight of the negative terminal of the first capacitor array is controlled to be (1 multiplied by 2) ^N-4 ) C, the capacitor switch corresponding to the capacitor makes the bottom plate connected with the reference voltage end;

using a set of outputs CP of second and third external comparators simultaneously ₁ 、CP ₀ Respectively controlling the weight of the positive end of the second capacitor array to be (1 multiplied by 2) ^N-4 )C、(4×2 ^N-4 ) The capacitor switch corresponding to the capacitor C has its bottom plate connected to the reference voltage terminal and the other group of the second and third external comparators outputs CN ₁ 、CN ₀ Respectively controlling the weight of the negative terminal of the second capacitor array to be (1 x 2) ^N-4 )C、(4×2 ^N-4 ) The bottom pole plate of the capacitor switch corresponding to the capacitor C is connected with the ground end; and the connection state of the bottom plates of the rest capacitors is kept unchanged;

step 4.3, if the three-digit thermometer code CP generated in the step 4 ₂ CP ₁ CP ₀ To "110", the first and the second are usedSet of outputs CP of two external comparators ₂ 、CP ₁ Respectively controlling the weight of the positive end of the first capacitor array to be (1 multiplied by 2) ^N-4 )C、(4×2 ^N-4 ) The capacitor switch corresponding to the capacitor C has its bottom plate connected to ground and the other group of the first and second external comparators outputs CN ₂ 、CN ₁ Respectively controlling the weight of the negative terminal of the first capacitor array to be (1 x 2) ^N-4 )C、(4×2 ^N-4 ) C, the capacitor switch corresponding to the capacitor makes the bottom plate connected with the reference voltage end;

using simultaneously an output CP of a third external comparator ₀ The weight in the positive end of the second capacitor array is controlled to be (1 multiplied by 2) ^N ^-4 ) The capacitor switch corresponding to the capacitor C has its bottom plate connected to the reference voltage terminal and the other output CN of the third external comparator ₀ The weight of the negative terminal of the second capacitor array is controlled to be (1 multiplied by 2) ^N-4 ) C, the capacitor switch corresponding to the capacitor makes the bottom plate connected with the ground end; and the connection state of the bottom plates of the rest capacitors is kept unchanged;

step 4.4, if the three-digit thermometer code CP generated in step 4 ₂ CP ₁ CP ₀ To "111", a set of outputs CP of three external comparators is used ₂ 、CP ₁ 、CP ₀ Respectively controlling the weight of the positive end of the first capacitor array to be (1 multiplied by 2) ^N-4 )C、(4×2 ^N-4 )C、(4×2 ^N-4 ) The capacitor switch corresponding to the capacitor C has its bottom plate connected to ground and the other group of three external comparators outputs CN ₂ 、CN ₁ 、CN ₀ Respectively controlling the weight of the negative terminal of the first capacitor array to be (1 x 2) ^N-4 )C、(4×2 ^N-4 )C、(4×2 ^N-4 ) C, the capacitor switch corresponding to the capacitor makes the bottom plate connected with the reference voltage end;

using simultaneously an output CP of a third external comparator ₀ The weight in the positive end of the second capacitor array is controlled to be (3 multiplied by 2) ^N ^-4 ) C capacitor, the bottom plate of which is connected to ground, and the other output CN of the third external comparator ₀ The weight of the negative terminal of the second capacitor array is controlled to be (3 multiplied by 2) ^N-4 ) C electricityThe capacitor switch corresponding to the capacitor is accommodated, and the bottom pole plate of the capacitor switch is connected with a reference voltage end; and the connection state of the bottom plates of the other capacitors is kept unchanged;

step 5, after the switching is finished, comparing the voltage of the capacitor top plate with a quantization threshold value generated in a second quantization period by using three external comparators respectively, so as to generate and output two groups of complementary three-position thermometer codes in the second quantization period;

and 6, in the third quantization period and each subsequent quantization period, the relation between the capacitor switch subjected to the switching operation and the capacitor switch subjected to the switching operation in the previous quantization period is as follows: the weights of the capacitances corresponding to the capacitance switches which are switched in the current quantization period are 1/4 of the weights of the capacitances corresponding to the capacitance switches which are switched in the previous quantization period, and the connection states of the capacitance switches which are switched in all quantization periods before the current quantization period are kept unchanged;

and then according to four possible situations of the generated three-position thermometer code in the previous quantization period, continuously controlling other capacitance switches in the capacitance switch module according to the modes from the step 4.1 to the step 4.4 until the switching operation of the capacitance switch in the Nth/2 th quantization period is completed.

Compared with the prior art, the invention has the beneficial effects that:

1. based on the principle of quantizing two bits per cycle, the invention adopts the structure of split capacitors, achieves the purpose of improving the conversion speed of successive approximation ADC by reasonably designing the weight of each capacitor in the capacitor array module and combining the designed capacitor switch control method, and simultaneously reduces the dynamic power consumption in the capacitor array circuit and improves the performance of the whole ADC.

2. The capacitor array circuit and the capacitor switch control method designed by the invention meet the actual requirement of quantizing two bits per cycle, and greatly improve the overall conversion speed of the ADC compared with the traditional structure.

3. The invention adopts the structure of the split capacitor, realizes the direct control of the capacitor switch module through the output of the comparator, avoids redundant operation, simplifies the design of a control logic circuit, further improves the overall conversion speed and reduces the power consumption of the ADC.

Drawings

FIG. 1 is a schematic diagram of a capacitor array circuit of the present invention with a resolution of 6 bits;

FIG. 2a is a schematic illustration of a sampling phase of the present invention;

FIG. 2b is a schematic diagram of the present invention during a first quantization period;

FIG. 2c shows the CP in the first quantization period according to the present invention ₂ CP ₁ CP ₀ At "000", during the second quantization period;

FIG. 2d illustrates the CP in the first quantization period of the present invention ₂ CP ₁ CP ₀ At "100", during the second quantization period;

FIG. 2e shows the CP in the first quantization period according to the present invention ₂ CP ₁ CP ₀ A plot during the second quantization period at "110";

FIG. 2f shows the CP in the first quantization period according to the present invention ₂ CP ₁ CP ₀ A plot during the second quantization period at "111";

FIG. 3 shows the present invention when the CP is in the first and second quantization periods ₂ CP ₁ CP ₀ All of which are "000", the third quantization period is the capacitance switch diagram requiring the switching operation.

Detailed Description

In this embodiment, as shown in fig. 1, a successive approximation ADC capacitor array circuit is characterized by comprising a capacitor array module and a capacitor switch module;

the capacitor array module comprises two capacitor arrays, namely a first capacitor array (a capacitor array 1) and a second capacitor array (a capacitor array 2), wherein each capacitor array is composed of a positive end and a negative end, the two capacitor arrays are connected with three external comparators (a comparator 1, a comparator 2 and a comparator 3), the positive ends of the two capacitor arrays are respectively connected with the positive input ends of the first external comparator (the comparator 1) and the third external comparator (the comparator 3), the negative ends of the two capacitor arrays are respectively connected with the negative input ends of the first external comparator and the third external comparator, the positive input end of the second external comparator (the comparator 2) is connected with the positive input end of the first external comparator, and the negative input end of the second comparator is connected with the negative input end of the third external comparator;

the capacitance switch module is composed of 4m capacitance switches, one end of each capacitance switch is a free end, and the other end of each capacitance switch is a fixed end, wherein m is 2N-2, N is the resolution digit of the ADC and is an even number, in this embodiment, N is 6, and m is 10;

the positive end and the negative end of each capacitor array are respectively composed of m capacitors with weights, and the weights of the m capacitors are respectively (3 multiplied by 2) ⁰ )C、(1×2 ⁰ )C、(4×2 ⁰ )C、(4×2 ⁰ )C、(3×2 ² )C、(1×2 ² )C、(4×2 ² )C、(4×2 ² )C、…、(3×2 ⁱ )C、(1×2 ⁱ )C、(4×2 ⁱ )C、(4×2 ⁱ )C、…、(3×2 ^N-6 )C、(1×2 ^N-6 )C、(4×2 ^N-6 )C、(4×2 ^N-6 )C、(3×2 ^N ^-4 )C、(1×2 ^N-4 )C、(4×2 ^N-4 )C、(4×2 ^N-4 ) C, 3C, and 1C, where C is a unit capacitance, i is 0, 2, 4, 6, 8, …, N-6, and N-4, and the weight of each capacitor in this embodiment is 3C, 1C, 4C, 12C, 4C, 16C, 3C, and 1C;

one end of each of m capacitors in the positive terminal is connected with the positive input end of the external comparator and the common mode voltage terminal, and the other end is correspondingly connected with the fixed ends of the m capacitor switches, wherein the common mode voltage terminal is V in the embodiment _cm A terminal;

one ends of m capacitors in the negative end are connected with the negative input end of the external comparator and the common-mode voltage end, and the other ends of the m capacitors are correspondingly connected with the fixed ends of the m capacitor switches respectively;

free end of capacitance switch corresponding to capacitance with weight of 3C and 1CSwitching between analog input signal terminal and reference voltage terminal, or switching between analog input signal terminal and ground terminal, in this embodiment, the analog input signal terminal is a differential signal V _ip Terminal and V _in Terminal, reference voltage terminal is V _ref A terminal;

under the control of different digital output signals (CP2/CN2, CP1/CN1, CP0/CN0) of an external comparator, the capacitance switch module switches the connection state of the free end of the corresponding capacitance switch, so that the bottom plate of the capacitance is connected to different voltages.

In this embodiment, as shown in fig. 2a to fig. 2f, the method for controlling a capacitance switch of a capacitor array circuit of a successive approximation ADC according to the present invention is illustrated with a resolution of 6 bits, and the method for controlling a capacitance switch of a capacitor array circuit of a successive approximation ADC is performed as follows:

step 1, as shown in fig. 2a, connecting the bottom plates of all capacitors in the capacitor array module to an analog input signal end, connecting the top plate to a common mode voltage end, and completing sampling of the analog input signal by the bottom plates of the capacitors;

step 2, as shown in fig. 2b, in the first quantization period, first disconnecting the positive and negative terminals of the two capacitor arrays from the common mode voltage terminal, and performing a switching operation for all the capacitor switches, including: the weights in the positive terminals of the first capacitor array are respectively (1 multiplied by 2) ⁰ )C、(4×2 ⁰ )C、(4×2 ⁰ )C、(1×2 ² )C、(4×2 ² )C、(4×2 ² )C、…、(1×2 ⁱ )C、(4×2 ⁱ )C、(4×2 ⁱ )C、…、(1×2 ^N-6 )C、(4×2 ^N-6 )C、(4×2 ^N-6 )C、(1×2 ^N-4 )C、(4×2 ^N-4 )C、(4×2 ^N-4 ) The bottom plates of the capacitors C and 3C are all connected to the reference voltage terminal, and the bottom plates of the other capacitors are all connected to the ground terminal, where i is 0, 2, 4, 6, 8, …, N-6, and N-4, and the weights of the capacitors in this embodiment are 1C, 4C, 16C, and 3C, respectively;

the weights in the negative terminal of the first capacitor array are (1)×2 ⁰ )C、(4×2 ⁰ )C、(4×2 ⁰ )C、(1×2 ² )C、(4×2 ² )C、(4×2 ² )C、…、(1×2 ⁱ )C、(4×2 ⁱ )C、(4×2 ⁱ )C、…、(1×2 ^N-6 )C、(4×2 ^N-6 )C、(4×2 ^N-6 )C、(1×2 ^N-4 )C、(4×2 ^N-4 )C、(4×2 ^N-4 ) All the bottom plates of the capacitors of C and 3C are grounded, and all the bottom plates of the other capacitors are connected to a reference voltage terminal, where i is 0, 2, 4, 6, 8, …, N-6, and N-4, and the weights of the capacitors in this embodiment are 1C, 4C, 16C, and 3C, respectively;

the weights in the positive terminals of the second capacitor arrays are respectively (3 multiplied by 2) ⁰ )C、(3×2 ² )C、…、(3×2 ⁱ )C、…、(3×2 ^N ^-6 )C、(3×2 ^N-4 ) The bottom plates of the capacitors C and 1C are all connected to the reference voltage terminal, and the bottom plates of the other capacitors are all connected to the ground terminal, where i is 0, 2, 4, 6, 8, …, N-6, and N-4, and the weights of the capacitors in this embodiment are 3C, 12C, and 1C, respectively;

the negative terminal of the second capacitor array is weighted to be (3 x 2) ⁰ )C、(3×2 ² )C、…、(3×2 ⁱ )C、…、(3×2 ^N ^-6 )C、(3×2 ^N-4 ) All the bottom plates of the capacitors of C and 1C are grounded, and all the bottom plates of the other capacitors are grounded, wherein i is 0, 2, 4, 6, 8, …, N-6, and N-4, and the weights of the capacitors are 3C, 12C, and 1C, respectively;

and 3, after the switching is finished, comparing the voltage of the capacitor top plate with the quantization threshold value generated in the first quantization period by using three external comparators respectively, so as to generate and output two groups of complementary three-position thermometer codes in the first quantization period, wherein the complementary outputs of the three external comparators are respectively CP ₂ /CN ₂ 、CP ₁ /CN ₁ 、CP ₀ /CN ₀ ；

Step 4, in the second quantization period, aiming at the weight of (3 multiplied by 2) ^N-4 )C、(1×2 ^N-4 )C、(4×2 ^N-4 )C、(4×2 ^N-4 ) C, the capacitance switch corresponding to the capacitance of C performs switching operationAnd controlling the capacitance switch module according to four possible situations of a three-bit thermometer code generated in a first quantization period, wherein the weights of the capacitors are respectively 12C, 4C, 16C and 16C;

step 4.1, as shown in the dashed box of FIG. 2c, if the three-digit thermometer code CP generated in step 4 ₂ CP ₁ CP ₀ To "000", an output CP of the first external comparator is used ₂ The weight in the positive end of the first capacitor array is controlled to be (3 multiplied by 2) ^N-4 ) The capacitor switch corresponding to the capacitor C has its bottom plate connected to the reference voltage terminal and the other output CN of the first external comparator ₂ The weight of the negative terminal of the first capacitor array is controlled to be (3 multiplied by 2) ^N-4 ) The capacitor switch corresponding to the capacitor C has its bottom plate connected to ground, and the weight of the capacitor is 12C in this embodiment;

using a set of outputs CP of three comparators simultaneously ₂ 、CP ₁ 、CP ₀ Respectively controlling the weight of the positive end of the second capacitor array to be (1 multiplied by 2) ^N-4 )C、(4×2 ^N-4 )C、(4×2 ^N-4 ) The capacitor switch corresponding to the capacitor C has its bottom plate connected to the reference voltage terminal and the other group of three comparators outputs CN ₂ 、CN ₁ 、CN ₀ Respectively controlling the weight of the negative terminal of the second capacitor array to be (1 x 2) ^N-4 )C、(4×2 ^N-4 )C、(4×2 ^N-4 ) C, the capacitor switch corresponding to the capacitor makes the bottom plate connected with the ground end; the connection state of the bottom plates of the other capacitors is kept unchanged, and the weights of the capacitors are respectively 4C, 16C and 16C in the embodiment;

step 4.2, shown in the dashed box of FIG. 2d, if the three-digit thermometer code CP generated in step 4 is present ₂ CP ₁ CP ₀ To "100", an output CP of the first external comparator is used ₂ The weight in the positive end of the first capacitor array is controlled to be (1 multiplied by 2) ^N-4 ) The capacitor switch corresponding to the capacitor C has its bottom plate connected to ground and the other output CN of the first external comparator ₂ The weight of the negative terminal of the first capacitor array is controlled to be (1 multiplied by 2) ^N-4 ) The bottom plate of the capacitor switch corresponding to the capacitor C is connected with a reference voltage endIn this embodiment, the capacitance weight is 4C;

using a set of outputs CP of second and third external comparators simultaneously ₁ 、CP ₀ Respectively controlling the weight of the positive end of the second capacitor array to be (1 multiplied by 2) ^N-4 )C、(4×2 ^N-4 ) C capacitor, connecting its bottom plate to reference voltage end, and using another group of second and third external comparators to output CN ₁ 、CN ₀ Respectively controlling the weight of the negative terminal of the second capacitor array to be (1 x 2) ^N-4 )C、(4×2 ^N-4 ) The bottom pole plate of the capacitor switch corresponding to the capacitor C is connected with the ground end; the connection state of the bottom plates of the other capacitors is kept unchanged, and the weights of the capacitors are respectively 4C and 16C in the embodiment;

step 4.3, as shown in the dashed box of FIG. 2e, if the three-digit thermometer code CP generated in step 4 ₂ CP ₁ CP ₀ To "110", a set of outputs CP of the first and second external comparators is used ₂ 、CP ₁ Respectively controlling the weight of the positive end of the first capacitor array to be (1 multiplied by 2) ^N-4 )C、(4×2 ^N-4 ) The capacitor switch corresponding to the capacitor C has its bottom plate connected to ground and the other group of the first and second external comparators outputs CN ₂ 、CN ₁ Respectively controlling the weight of the negative terminal of the first capacitor array to be (1 x 2) ^N-4 )C、(4×2 ^N-4 ) The capacitor switch corresponding to the capacitor of C has its bottom plate connected to the reference voltage terminal, and the weights of the capacitors are 4C and 16C, respectively;

using simultaneously an output CP of a third external comparator ₀ The weight in the positive end of the second capacitor array is controlled to be (1 multiplied by 2) ^N ^-4 ) The capacitor switch corresponding to the capacitor C has its bottom plate connected to the reference voltage terminal and the other output CN of the third external comparator ₀ The weight of the negative terminal of the second capacitor array is controlled to be (1 multiplied by 2) ^N-4 ) The bottom pole plate of the capacitor switch corresponding to the capacitor C is connected with the ground end; the connection state of the bottom plates of the other capacitors is kept unchanged, and the weight of the capacitor is 4C in the embodiment;

step 4.4, as shown in the dashed box of FIG. 2f, if step4 generated three-digit thermometer code CP ₂ CP ₁ CP ₀ To "111", a set of outputs CP of three external comparators is used ₂ 、CP ₁ 、CP ₀ Respectively controlling the weight of the positive end of the first capacitor array to be (1 multiplied by 2) ^N-4 )C、(4×2 ^N-4 )C、(4×2 ^N-4 ) The capacitor switch corresponding to the capacitor C has its bottom plate connected to ground and the other group of three external comparators outputs CN ₂ 、CN ₁ 、CN ₀ Respectively controlling the weight of the negative terminal of the first capacitor array to be (1 x 2) ^N-4 )C、(4×2 ^N-4 )C、(4×2 ^N-4 ) The capacitor switch corresponding to the capacitor of C has its bottom plate connected to the reference voltage terminal, and the weights of the capacitors are 4C, 16C, and 16C, respectively;

using simultaneously an output CP of a third external comparator ₀ The weight in the positive end of the second capacitor array is controlled to be (3 multiplied by 2) ^N ^-4 ) The bottom plate of the capacitor switch corresponding to the capacitor C is connected with the ground end, and the other output CN of the third external comparator is used ₀ The weight of the negative terminal of the second capacitor array is controlled to be (3 multiplied by 2) ^N-4 ) C, a capacitor switch corresponding to the capacitor, wherein the bottom plate of the capacitor switch is connected with a reference voltage end; the connection state of the bottom plates of the other capacitors is kept unchanged, and the weight of the capacitor is 12C in the embodiment;

step 6, in the third quantization period and each subsequent quantization period, the relationship between the capacitor switch performing the switching operation and the capacitor switch performing the switching operation in the previous quantization period is as follows: the weights of the capacitances corresponding to the capacitance switches performing the switching operation in the current quantization period are 1/4 of the weights of the capacitances corresponding to the capacitance switches performing the switching operation in the previous quantization period, that is, in order: (3X 2) ^N-6 )C、(1×2 ^N-6 )C、(4×2 ^N-6 )C、(4×2 ^N-6 )C，(3×2 ^N-8 )C、(1×2 ^N-8 )C、(4×2 ^N-8 )C、(4×2 ^N-8 )C，(3×2 ^N-10 )C、(1×2 ^N-10 )C、(4×2 ^N-10 )C、(4×2 ^N-10 )C，…，(3×2 ^N-j )C、(1×2 ^N-j )C、(4×2 ^N-j )C、(4×2 ^N-j )C，…，(3×2 ⁰ )C、(1×2 ⁰ )C、(4×2 ⁰ )C、(4×2 ⁰ ) C, wherein j is 6, 8, 10, 12, …, N-2, N; simultaneously keeping the connection state of the capacitance switches which are switched in all the quantization periods before the current quantization period unchanged; in this embodiment, the three-bit thermometer code CP is generated during the first and second quantization periods ₂ CP ₁ CP ₀ When the values are all "000", the capacitance weights corresponding to the capacitance switches which need to be switched in the third quantization period are (3 × 2) ^N-6 )C、(1×2 ^N-6 )C、(4×2 ^N-6 )C、(4×2 ^N-6 ) C, i.e., 3C, 1C, 4C, as shown in the dashed box of fig. 3.

And then according to four possible conditions of the three-bit thermometer code generated in the previous quantization period, continuously controlling other capacitance switches in the capacitance switch module according to the modes from step 4.1 to step 4.4 until the switching operation of the capacitance switch in the N/2 th quantization period is completed.

Claims

1. A capacitor array circuit of successive approximation ADC is characterized by comprising a capacitor array module and a capacitor switch module;

the positive end and the negative end of each capacitor array are respectively composed of m capacitors with weights, and the weights of the m capacitors are respectively (3 multiplied by 2) ⁰ )C、(1×2 ⁰ )C、(4×2 ⁰ )C、(4×2 ⁰ )C、(3×2 ² )C、(1×2 ² )C、(4×2 ² )C、(4×2 ² )C、…、(3×2 ⁱ )C、(1×2 ⁱ )C、(4×2 ⁱ )C、(4×2 ⁱ )C、…、(3×2 ^N-6 )C、(1×2 ^N-6 )C、(4×2 ^N-6 )C、(4×2 ^N-6 )C、(3×2 ^N-4 )C、(1×2 ^N-4 )C、(4×2 ^N-4 )C、(4×2 ^N-4 ) C, 3C, 1C, wherein C is a unit capacitance, i ═ 0, 2, 4, 6, 8, …, N-6, N-4;

2. The method of claim 1, comprising the steps of:

the weights of the negative terminals of the first capacitor array are (1 × 2) ⁰ )C、(4×2 ⁰ )C、(4×2 ⁰ )C、(1×2 ² )C、(4×2 ² )C、(4×2 ² )C、…、(1×2 ⁱ )C、(4×2 ⁱ )C、(4×2 ⁱ )C、…、(1×2 ^N-6 )C、(4×2 ^N-6 )C、(4×2 ^N-6 )C、(1×2 ^N ^-4 )C、(4×2 ^N-4 )C、(4×2 ^N-4 ) The bottom plates of the capacitors C and 3C are all grounded, and the bottom plates of the other capacitors are all connected with a reference voltage end, wherein i is 0, 2, 4, 6, 8, …, N-6 and N-4;

the weights in the positive ends of the second capacitor arrays are respectively (3 multiplied by 2) ⁰ )C、(3×2 ² )C、…、(3×2 ⁱ )C、…、(3×2 ^N-6 )C、(3×2 ^N-4 ) The bottom plates of the capacitors C and 1C are all connected with a reference voltage end, the bottom plates of the other capacitors are all connected with a ground end, wherein i is 0、2、4、6、8、…、N-6、N-4；

The weights of the negative terminals of the second capacitor array are (3 x 2) ⁰ )C、(3×2 ² )C、…、(3×2 ⁱ )C、…、(3×2 ^N-6 )C、(3×2 ^N-4 ) The bottom plates of the capacitors C and 1C are all grounded, and the bottom plates of the other capacitors are all connected with a reference voltage end, wherein i is 0, 2, 4, 6, 8, …, N-6 and N-4;

Step 4, in the second quantization period, aiming at the weight of (3 multiplied by 2) ^N-4 )C、(1×2 ^N-4 )C、(4×2 ^N-4 )C、(4×2 ^N-4 ) C, the capacitor switch corresponding to the capacitor is switched, and the capacitor switch module is controlled according to four possible conditions of the three-bit thermometer code generated in the first quantization period;

step 4.1, if the three-digit thermometer code CP generated in step 4 ₂ CP ₁ CP ₀ To "000", an output CP of the first external comparator is used ₂ The weight in the positive end of the first capacitor array is controlled to be (3 multiplied by 2) ^N-4 ) The capacitor switch corresponding to the capacitor C has its bottom plate connected to the reference voltage terminal and the other output CN of the first external comparator ₂ The weight of the negative terminal of the first capacitor array is controlled to be (3 multiplied by 2) ^N-4 ) C, the capacitor switch corresponding to the capacitor makes the bottom plate connected with the ground end;

using a set of outputs CP of three comparators simultaneously ₂ 、CP ₁ 、CP ₀ Respectively controlling the weight of the positive end of the second capacitor array to be (1 x 2) ^N-4 )C、(4×2 ^N-4 )C、(4×2 ^N-4 ) The capacitor switch corresponding to the capacitor C has its bottom plate connected to the reference voltage terminal and the other group of three comparators outputs CN ₂ 、CN ₁ 、CN ₀ Respectively controlling the weight of the negative terminal of the second capacitor array to be (1 x 2) ^N-4 )C、(4×2 ^N-4 )C、(4×2 ^N-4 ) The bottom pole plate of the capacitor switch corresponding to the capacitor C is connected with the ground end; and the connection state of the bottom plates of the rest capacitors is kept unchanged;

step 4.2, if the three-digit thermometer code CP generated in step 4 ₂ CP ₁ CP ₀ To "100", an output CP of the first external comparator is used ₂ The weight in the positive end of the first capacitor array is controlled to be (1 multiplied by 2) ^N-4 ) The capacitor switch corresponding to the capacitor C has its bottom plate connected to ground and the other output CN of the first external comparator ₂ The weight of the negative terminal of the first capacitor array is controlled to be (1 multiplied by 2) ^N-4 ) C, the capacitor switch corresponding to the capacitor makes the bottom plate connected with the reference voltage end;

using a set of outputs CP of second and third external comparators simultaneously ₁ 、CP ₀ Respectively controlling the weight of the positive end of the second capacitor array to be (1 multiplied by 2) ^N-4 )C、(4×2 ^N-4 ) The capacitor switch corresponding to the capacitor C has its bottom plate connected to the reference voltage terminal and the other group of the second and third external comparators outputs CN ₁ 、CN ₀ Respectively controlling the weight of the negative terminal of the second capacitor array to be (1 x 2) ^N-4 )C、(4×2 ^N-4 ) C, the capacitor switch corresponding to the capacitor makes the bottom plate connected with the ground end; and the connection state of the bottom plates of the other capacitors is kept unchanged;

step 4.3, if the three-digit thermometer code CP generated in the step 4 ₂ CP ₁ CP ₀ To "110", a set of outputs CP of the first and second external comparators is used ₂ 、CP ₁ Respectively controlling the weight of the positive end of the first capacitor array to be (1 multiplied by 2) ^N-4 )C、(4×2 ^N-4 ) The capacitor switch corresponding to the capacitor C has its bottom plate connected to ground and the other group of the first and second external comparators outputs CN ₂ 、CN ₁ Respectively controlling the weight of the negative terminal of the first capacitor array to be (1 x 2) ^N -4)C、(4×2 ^N-4 ) C, a capacitor switch corresponding to the capacitor, wherein the bottom plate of the capacitor switch is connected with a reference voltage end;

using simultaneously an output CP of a third external comparator ₀ The weight in the positive end of the second capacitor array is controlled to be (1 multiplied by 2) ^N-4 ) C capacitor, making its bottom plate connected with reference voltage end, and using another output CN of third external comparator ₀ The weight of the negative terminal of the second capacitor array is controlled to be (1 multiplied by 2) ^N-4 ) The bottom pole plate of the capacitor switch corresponding to the capacitor C is connected with the ground end; and the connection state of the bottom plates of the rest capacitors is kept unchanged;

using simultaneously an output CP of a third external comparator ₀ The weight in the positive end of the second capacitor array is controlled to be (3 multiplied by 2) ^N-4 ) The bottom plate of the capacitor switch corresponding to the capacitor C is connected with the ground end, and the other output CN of the third external comparator is used ₀ The weight of the negative terminal of the second capacitor array is controlled to be (3 multiplied by 2) ^N-4 ) C, the capacitor switch corresponding to the capacitor makes the bottom plate connected with the reference voltage end; and the connection state of the bottom plates of the other capacitors is kept unchanged;

and 6, in the third quantization period and each subsequent quantization period, the relation between the capacitor switch subjected to the switching operation and the capacitor switch subjected to the switching operation in the previous quantization period is as follows: the weights of the capacitances corresponding to the capacitance switches performing the switching operation in the current quantization period are 1/4 of the weights of the capacitances corresponding to the capacitance switches performing the switching operation in the previous quantization period, and the connection states of the capacitance switches performing the switching operation in all quantization periods before the current quantization period are kept unchanged;