WO2015154671A1 - Self-calibration method and device for pipeline successive approximation type analogue to digital convertor - Google Patents

Abstract

Disclosed are a self-calibration method and device for a pipeline successive approximation type analogue to digital convertor. The self-calibration device comprises: a first-level successive approximation type analogue to digital convertor which is used for completing data acquisition and analogue to digital conversion of an input signal, wherein a pseudorandom quantity with a known digital quantity is exerted on the first-level successive approximation type analogue to digital convertor; a second-level successive approximation type analogue to digital convertor; an operational amplifier used for amplifying a residual signal output by the first-level successive approximation type analogue to digital convertor and transmitting same to the second-level successive approximation type analogue to digital convertor to conduct analogue to digital conversion; and a digital calibration control logic circuit used for conducting a cyclic calibration according to the pseudorandom quantity and the output of the first-level successive approximation type analogue to digital convertor and the second-level successive approximation type analogue to digital convertor to control the gain of the operational amplifier and obtain data output. By means of the method, the present invention can adjust the gain of an operational amplifier in real time and calibrate the influence of factors such as calibration temperature and power source voltage on the gain, thereby improving the effective accuracy of an ADC.

Description

Self-calibration method and device for serially comparing analog-to-digital converters [Technical Field]

The present invention relates to the field of integrated circuit technology, and in particular, to a self-calibration method and apparatus for a pipeline sequential comparison analog-to-digital converter.

【Background technique】

As the microelectronics process enters the nanoscale process, the Pipeline Analog to Digital Convertor (Pipeline ADC) is becoming more and more difficult to implement under advanced nanoscale processes, and due to its huge power consumption, The area is becoming more and more unacceptable. In this context, a new technology that combines a Pipeline ADC with a Successive Approximation Register (SAR) ADC is proposed, which replaces the FLASH ADC in a single stage of the Pipeline ADC with a SAR ADC. Reduce power consumption and reduce area. Similar to the Pipeline ADC, the op amp is also present in the pipeline progressive analog-to-digital converter (Pipeline SAR ADC), and the gain of the op amp and the mismatch between the op amp and the comparator drift with the process temperature, affecting accuracy. Therefore, calibration is required by calibration to improve accuracy.

The existing Pipeline SAR ADC is divided into a closed-loop based Pipeline SAR ADC and an open-loop based Pipeline SAR ADC. Closed-loop-based Pipeline SAR ADCs rely on capacitive matching to achieve the accuracy of the op amp's gain, and with the associated calibration techniques can achieve higher accuracy, but its op amp speed requirements will be doubled, and will consume more work Consumption. For example, if the first stage capacitor is used as the feedback of the interstage op amp, the amplification ratio of the op amp depends on the ratio of the capacitance. Therefore, under the condition that the gain and bandwidth of the operational amplifier meet the requirements, the matching degree of the operational amplifier and the capacitance determines the gain of the operational amplifier, but it puts high requirements on the speed of the operational amplifier, that is, if the closed-loop amplification factor is 8, The bandwidth of the op amp needs to be 8 times the operating bandwidth of the closed loop, so it has high requirements on the operating bandwidth of the op amp, and it requires the op amp to operate at a higher bandwidth, which is difficult to achieve. Open-loop-based Pipeline SAR ADCs make it easier to achieve higher speeds, but the op amp's gain shifts with process angle and temperature and requires calibration.

[Summary of the Invention]

Embodiments of the present invention provide a self-calibration method and apparatus for a pipeline sequential comparison analog-to-digital converter, which can adjust the gain of the operational amplifier in real time in the background calibration, and can calibrate the temperature and the power supply voltage. Gain effects due to factors such as variations, thereby increasing the effective accuracy of the ADC.

In order to solve the above technical problem, a first aspect of the present invention provides a self-calibration device for a pipeline sequential comparison analog-to-digital converter, comprising:

a first-stage successive approximation analog-to-digital converter for performing data acquisition and analog-to-digital conversion of an input signal, wherein the first-stage successive approximation analog-to-digital converter is applied with a pseudo-random quantity of known digital quantity ;

Second-stage successive approximation analog-to-digital converter;

An operational amplifier connected between the first-stage successive approximation analog-to-digital converter and the second-order successive approximation analog-to-digital converter for amplifying and transmitting the residual signal outputted by the first-stage successive approximation analog-to-digital converter To a second-stage successive approximation analog-to-digital converter to drive a second-stage successive approximation analog-to-digital converter for analog-to-digital conversion;

Digital calibration control logic circuit coupled to a first-stage successive approximation analog-to-digital converter, a second-stage successive approximation analog-to-digital converter, and an operational amplifier for use in a first-stage successive approximation analog-to-digital converter and a second stage The output of the successive approximation analog-to-digital converter and the pseudo-random amount are cyclically calibrated to control the gain of the operational amplifier and obtain a data output.

In conjunction with the implementation of the first aspect, in a first possible implementation, the digital calibration control logic circuit includes:

a multiplier for multiplying an output of the first-stage successive approximation analog-to-digital converter by a weight of each of the first-order successive approximation analog-to-digital converters, wherein the weight includes gain gain information of the operational amplifier;

An adder for adding the output of the multiplier to the output of the second-stage successive approximation analog-to-digital converter;

a subtracter for subtracting a digital quantity of the pseudo random quantity from the output of the adder to obtain the calibrated data and outputting the calibrated data;

a re-quantization unit, configured to re-quantize the calibrated data application weights to obtain re-quantized first-level output and second-level output;

a correlator for correlating the re-quantized first-level output with a pseudo-random amount;

a redundancy correction unit for performing redundancy correction on the output of the correlator;

The operator is configured to perform a minimum mean square algorithm operation on the output of the redundancy correction unit to obtain a convergence weight, and the convergence weight of the multiplier output is multiplied by the output of the first-stage successive approximation analog-to-digital converter. The above process is repeated to perform cyclic calibration, control the gain of the operational amplifier, and obtain a data output. When the output of the redundancy correction unit is zero, the outputted calibration data is the output after the cycle calibration.

In combination with the first possible implementation manner of the first aspect, in the second possible implementation manner, the first-stage successive approximation analog-to-digital converter is a successive comparison analog-to-digital converter with a weight less than 2, when the redundancy correction unit When the output is zero, the weight converges to a specific value (W0), where the weight deviates from a certain value when the environmental conditions change, and cyclic calibration is required. The environmental conditions include temperature, process angle, and power.

In conjunction with the second possible implementation of the first aspect, in a third possible implementation, if the weight is less than a certain range (W0), the digital calibration control logic increases the gain of the operational amplifier; if the weight Above a certain range (W0), the digital calibration control logic reduces the gain of the operational amplifier, where a certain range is obtained by testing.

In conjunction with the implementation of the first aspect, in a fourth possible implementation, the operational amplifier is a programmable resistive operational amplifier or a capacitive operational amplifier.

In conjunction with the implementation of the first aspect, in a fifth possible implementation, the first-stage successive approximation analog-to-digital converter and the second-stage successive approximation analog-to-digital converter include:

The first capacitor array is composed of a plurality of capacitors, wherein the first ends of each capacitor are connected together, and the second end of each capacitor is respectively connected to the first input signal or the reference power through a corresponding control switch Flat, the reference level includes a common mode level, a first reference level, or a second reference level;

The second capacitor array is composed of a plurality of capacitors and has the same structure as the first capacitor array, wherein the first ends of each capacitor are connected together, and the second end of each capacitor is respectively passed through a corresponding control switch Connected to a second input signal or reference level;

a first successive approximation logic circuit (SAR logic) that connects each of the control switches and connects the second end of each of the first capacitor array and the second capacitor array to the first input signal by controlling each of the control switches, a second input signal or reference level;

a first comparator, wherein a first input of the first comparator is coupled to a first end of each capacitor in the first capacitor array, and a second input of the first comparator is coupled to each capacitor in the second capacitor array The first end of the first comparator, and the output of the first comparator is connected to the first successive approximation logic circuit;

Wherein, when sampling, the first end of each capacitor in the first capacitor array is connected to the first input signal, and the first end of each capacitor in the second capacitor array is connected to the second input signal for bottom plate sampling; after sampling a first terminal of each of the first capacitor array and the second capacitor array is connected to a common mode level, and the first comparator performs successive comparisons to remove the lowest capacitance from the first capacitor array and the second capacitor array. The second end of the other capacitor is selected to be connected to the first reference level or the second reference level, and the second end of the lowest capacitance in the first capacitor array and the second capacitor array is applied with a pseudo random amount.

In combination with the fifth possible implementation manner of the first aspect, in the sixth possible implementation manner, the first The first end of each capacitor in the first capacitor array of the successive-approximation analog-to-digital converter is further connected to the first end of the operational amplifier, and the first capacitor of the second capacitor array of the first-stage successive approximation analog-to-digital converter The first end is further connected to the second end of the operational amplifier, so that the operational amplifier amplifies and transmits the residual signal outputted by the first-stage successive approximation analog-to-digital converter to the second-stage successive approximation analog-to-digital converter.

In conjunction with the sixth possible implementation of the first aspect, in a seventh possible implementation, the first-stage successive approximation analog-to-digital converter is further configured to use the first capacitor array and the second capacitor array therein The first terminal of each capacitor is connected to a common mode level for sampling, comparing, and adjusting the mismatch of the first comparator until the second terminal of the most significant bit capacitor in the first capacitor array and the second capacitor array is connected to the first The probability of the reference level or the second reference level is 50%;

The second-stage successive approximation analog-to-digital converter is further configured to connect the first terminal of each of the first capacitor array and the second capacitor array to a common mode level for sampling, comparing, and adjusting the second The mismatch of the comparator, the probability that the second terminal of the most significant bit capacitance of the first capacitor array and the second capacitor array is connected to the first reference level or the second reference level is 50%;

The digital calibration controller is further configured to connect each of the first capacitor array and the second capacitor array in the first-stage successive approximation analog-to-digital converter to a common mode level, and adjust the gain of the operational amplifier to make the first The deviation of the output of the two outputs 011...1 and 100...0 of the successive approximation analog-to-digital converter via the operational amplifier and the second-stage successive approximation analog-to-digital converter reaches a preset value.

In order to solve the above technical problem, a second aspect of the present invention provides a self-calibration method for a pipeline sequential comparison analog-to-digital converter, comprising: performing data acquisition and analog-to-digital conversion of an input signal by a first-stage successive approximation analog-to-digital converter, Wherein the first-stage successive approximation analog-to-digital converter is applied with a pseudo-random amount of known digital quantity;

The residual signal output from the first-stage successive approximation analog-to-digital converter is amplified by an operational amplifier and transmitted to a second-stage successive approximation analog-to-digital converter to drive a second-stage successive approximation analog-to-digital converter for analog-to-digital conversion. ;

The loop is calibrated according to the output of the first-stage successive approximation analog-to-digital converter and the second-order successive approximation analog-to-digital converter and the pseudo-random amount to control the gain of the operational amplifier.

In combination with the implementation of the second aspect, in the first possible implementation, the cyclic calibration is performed according to the output of the first-stage successive approximation analog-to-digital converter and the second-order successive approximation analog-to-digital converter, and a pseudo-random quantity, The steps to control the gain of the operational amplifier and obtain the data output include:

Multiplying the output of the first-stage successive approximation analog-to-digital converter by the weight of each of the first-order successive approximation analog-to-digital converters and adding the output of the second-order successive approximation analog-to-digital converter, where Right The value includes gain deviation information of the operational amplifier;

Subtracting the obtained output from the digital quantity of the pseudo-random amount to obtain the calibrated data and outputting the calibrated data;

Recalibrating the calibrated data application weights to obtain requantized first stage outputs and second level outputs;

Correlating the re-quantized first-stage output with a pseudo-random quantity and performing redundancy correction, performing a least mean square algorithm operation on the redundantly corrected output to obtain a convergence weight, and the convergence weight is further compared with the first level Multiplying the output of the successive approximation analog-to-digital converter, repeating the above process for cyclic calibration, controlling the gain of the operational amplifier, and obtaining a data output, wherein when the output after the redundant calibration is zero, the output is calibrated The data is the output after cyclic calibration.

In combination with the first possible implementation manner of the second aspect, in the second possible implementation manner, the first-stage successive approximation analog-to-digital converter is a successive comparison analog-to-digital converter with a weight less than 2, after redundancy correction When the output is zero, the weight converges to a specific value (W0), where the weight deviates from a certain value when the environmental conditions change, and cyclic calibration is required. The environmental conditions include temperature, process angle, and power.

In conjunction with the second possible implementation of the second aspect, in a third possible implementation, if the weight is less than a certain range (W0), the gain of the operational amplifier is increased; if the weight is greater than a specific value (W0) A certain range reduces the gain of the op amp, where a certain range is obtained by testing.

In conjunction with the implementation of the second aspect, in a fourth possible implementation, the operational amplifier is a programmable resistive operational amplifier or a capacitive operational amplifier.

Through the above solution, the beneficial effects of the present invention are: the present invention completes data acquisition and analog-to-digital conversion of an input signal by a first-stage successive approximation analog-to-digital converter, wherein a first-stage successive approximation analog-to-digital converter is applied a pseudo-random quantity of known digital quantity; the residual signal output by the first-stage successive approximation analog-to-digital converter is amplified by an operational amplifier and transmitted to a second-stage successive approximation analog-to-digital converter to drive the second-order successive approximation The analog-to-digital converter performs analog-to-digital conversion; the digital calibration control logic circuit performs cyclic calibration according to the output of the first-stage successive approximation analog-to-digital converter and the second-order successive approximation analog-to-digital converter, and pseudo-random quantity to control the operation The gain of the amplifier and the data output. The cycle calibration includes foreground calibration and background calibration. The gain of the op amp can be adjusted in real time in the background calibration. The gain effect of temperature, power supply voltage variation and other factors can be calibrated to improve the efficiency of the ADC. Precision.

[Description of the Drawings]

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following description will be made on the embodiments. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in the drawings The drawings obtain other figures. among them:

1 is a schematic structural view of a self-calibration device of a pipeline successive comparison analog-to-digital converter according to a first embodiment of the present invention;

2 is a timing chart showing the operation of the pipeline successive comparison analog-to-digital converter according to the first embodiment of the present invention;

3 is a schematic structural diagram of a first-stage successive approximation analog-to-digital converter according to a first embodiment of the present invention;

4 is a schematic diagram of successive comparison analog-to-digital conversion of a second-stage successive approximation analog-to-digital converter according to a first embodiment of the present invention;

5 is a schematic structural diagram of a digital calibration control logic circuit according to a first embodiment of the present invention;

6 is a schematic diagram of cyclic calibration of a digital calibration control logic circuit according to a first embodiment of the present invention;

7 is a schematic structural diagram of a self-calibration device of a pipeline successive comparison analog-to-digital converter according to a second embodiment of the present invention;

8 is a flow chart showing a self-calibration method of a pipeline successive comparison analog-to-digital converter according to a first embodiment of the present invention;

9 is a schematic diagram of a method of background calibration of a pipeline successive comparison analog-to-digital converter according to a first embodiment of the present invention.

【detailed description】

The invention will now be described in detail in conjunction with the drawings and embodiments.

Referring to FIG. 1, FIG. 1 is a schematic structural diagram of a self-calibration device of a pipeline successive comparison analog-to-digital converter according to a first embodiment of the present invention. As shown in FIG. 1, the pipeline self-calibration device 10 for sequentially comparing analog-to-digital converters includes: a first-stage successive approximation analog-to-digital converter 11, a second-stage successive approximation analog-to-digital converter 12, an operational amplifier 13, and a digital calibration. Control logic circuit 14. Dout1 is an analog-to-digital conversion output of the first-order successive approximation analog-to-digital converter 11, and Dout2 is an analog-to-digital conversion output of the second-order successive approximation analog-to-digital converter 12. The operational amplifier 13 is a programmable resistive operational amplifier.

In the embodiment of the present invention, the first-stage successive approximation analog-to-digital converter 11 is configured to perform data acquisition of the input signal V _in and analog-to-digital conversion of a portion of the input signal Vin. The operational amplifier 13 is connected between the first-stage successive approximation analog-to-digital converter 11 and the second-order successive approximation analog-to-digital converter 12 for performing the residual signal output by the first-stage successive approximation analog-to-digital converter 11. Amplifying and transmitting to the second-stage successive approximation analog-to-digital converter 12 to drive the second-stage successive approximation analog-to-digital converter 12 to perform analog-to-digital conversion on the residual signal output by the first-stage successive approximation analog-to-digital converter 11. . The first-stage successive approximation analog-to-digital converter 11 is applied with a pseudo-random amount PN*Ta of a known digital quantity. The digital calibration control logic circuit 14 is connected to the first-stage successive approximation analog-to-digital converter 11, the second-stage successive approximation analog-to-digital converter 12, and the operational amplifier 13, for the successive approximation analog-to-digital converter 11 according to the first stage. The output of the second-stage successive approximation analog-to-digital converter 12 and the pseudo-random amount PN*Ta are cyclically calibrated to control the gain of the operational amplifier 13 and to obtain a data output. The cyclic calibration performed by the digital calibration control logic circuit 14 of the present invention includes foreground calibration and background calibration, and real-time adjustment of the gain of the operational amplifier in the background calibration, which can calibrate the gain effect caused by factors such as temperature and power supply voltage variation, thereby improving the ADC. Effective precision.

Specifically, the operation timing of the first-stage successive approximation analog-to-digital converter 11 and the second-stage successive approximation analog-to-digital converter 12 is as shown in FIG. 2, where T represents one cycle. As shown in FIG. 2, in the first 1/4T, the first-stage successive approximation analog-to-digital converter 11 performs sampling, and in the subsequent 1/2T, the first-stage successive approximation analog-to-digital converter 11 performs successive comparisons to perform Analog-to-digital conversion, and in the last 1/4T, the operational amplifier 13 transmits the residual signal sampled by the first-stage successive approximation analog-to-digital converter 11 to the second-order successive approximation analog-to-digital converter 12, which is equivalent to The second-order successive approximation analog-to-digital converter 12 performs a sampling operation. In the next cycle, in the first 3/4T, the second-stage successive approximation analog-to-digital converter 12 performs analog-to-digital conversion on the signal sampled in the previous cycle, and so on.

In the embodiment of the present invention, as shown in FIG. 3, the first-stage successive approximation analog-to-digital converter 11 includes: a first successive approximation logic circuit (SAR logic) 111, a first comparator 112, and a first capacitor array 113. And a second capacitor array 114. The first capacitor array 113 is composed of a plurality of capacitors, such as capacitors C ₀ , C ₁ , . . . , C _MSB , where C _MSB is the highest capacitance and C ₀ is the lowest capacitance. A first end of each capacitor connected to a first terminal of a first comparator 112 and to ground through switch S1, and the second end of each capacitor are connected to a first input signal V _in, or by a corresponding control switch a reference level, wherein the reference level comprises a common mode level _Vcm , a first reference level +V _R , or a second reference level -V _R . The second capacitor array 114 is composed of a plurality of capacitors and has the same structure as the first capacitor array 113. The first end of each capacitor is coupled to the second end of the first comparator 112 and is also coupled to ground via switch S2, and the second end of each capacitor is also coupled to the second input signal V _ip via a respective control switch Or the reference level; in addition, the first end of each capacitor of the first capacitor array 113 is also respectively connected to the first end of the operational amplifier 13, and the first end of each capacitor of the second capacitor array 114 is also respectively connected To the second end of the operational amplifier 13. The output of the first comparator 112 is coupled to the first successive approximation logic circuit 111, and the first successive approximation logic circuit 111 is coupled to each of the control switches and controls the first capacitor array 113 and the second capacitor by controlling each of the control switches. array 114 of the second end of each capacitor selectively connected to a first input signal V _in, V _ip or second input signal level with reference to any one of.

In the embodiment of the present invention, the first-stage successive approximation analog-to-digital converter 11 adopts a capacitance flip mode based on a common mode level, that is, sampling is performed using a bottom plate. When the first-stage successive approximation analog-to-digital converter 11 performs sampling, the switch S1 and the switch S2 are closed. At this time, the second end of each capacitor in the first capacitor array 113 is connected to the first input signal V _in , and The second end of each of the two capacitor arrays 114 is coupled to a second input signal V _ip for bottom plate sampling. After sampling, switch S1 and switch S2 are open, and the second end of each of the first capacitor array 113 and the second capacitor array 114 is connected to a common mode level _Vcm . The first comparator 112 in the first-stage successive approximation analog-to-digital converter 11 performs successive comparisons, that is, the first capacitor array 113 and the second capacitor array 114 are compared bit by bit from the highest bit capacitance C _MSB to the lower capacitance C ₁ . Determining, by the comparison result, whether the second end of each of the first capacitor array 113 and the second capacitor array 114 is flipped to the first reference level +V _R or to the second reference level -V _R The inverting direction of the second end of each of the first capacitor array 113 and the second capacitor array 114 is exactly opposite, that is, if the second end of the capacitor in the first capacitor array 113 is the first A reference level + V _R flips, and the second end of the capacitance of the corresponding bit in the second capacitor array 114 is flipped toward the second reference level -V _R . This is constantly being compared until the last one. When compared, other low-level capacitors that are not compared are first connected to the common-mode level V _cm . The lowest bit capacitance C ₀ is not connected to the input signal at the time of sampling, but is connected to the first reference level +V _R or the second reference level -V _R , which is controlled by the pseudo random signal PN, so that the signal The input end is injected with a pseudo random signal PN of LSB (Least Significant Bit).

Therefore, after the comparison is completed, the second ends of the capacitors other than the lowest bit capacitance C ₀ of the first capacitor array 113 and the second capacitor array 114 are selectively connected to the first reference level +V _R or the second reference, respectively. Level -V _R , and a pseudo random signal PN is applied to the second end of the lowest capacitance C ₀ of the first capacitor array 113 and the second capacitor array 114. This completes the analog to digital conversion of the input signal. Further, the residual signal of the first-stage successive approximation analog-to-digital converter 11 that has not undergone analog-to-digital conversion is transmitted to the second-stage successive approximation analog-to-digital converter 12 through the operational amplifier 13.

The second-stage successive approximation analog-to-digital converter 12 is similar in structure to the first-stage successive approximation analog-to-digital converter 11, and also includes various components as shown in FIG. 3, and adopts a first-order successive approximation mode. The digital converter 11 performs the associated analog-to-digital conversion on the amplified residual signal output from the operational amplifier 13 in the same manner. 4 is a state of the second-stage successive approximation analog-to-digital converter 12 at a certain moment. Figure.

Among them, the leftmost part of the two capacitor arrays is the Most Significant Bit (MSB). The capacitor _Catt is an attenuating capacitor for weight matching and adjusting the magnitude of the common mode level and the total capacitance in the capacitor array. After the sampling of the second-stage successive approximation analog-to-digital converter 12 is completed, the first comparison is performed: when MSB=0, that is, V _ip <V _in , the most significant bit of the capacitor array at the positive input terminal of the comparator 122 is connected to the Vref level. The most significant bit of the capacitor array at the negative input of comparator 122 is connected to the 0 level. When MSB=1, that is, V _ip >V _in , the most significant bit of the positive input terminal of the comparator 122 is connected to the 0 level, and the most significant bit of the capacitor array of the negative input terminal of the comparator 122 is connected to the Vref level. Thus, the capacitance array at the positive input of comparator 122 and the most significant bit capacitance of the capacitor array at the negative input of comparator 122 are flipped in opposite directions. Thereafter, the above process is continuously repeated until the lowest position. It can be seen that in the embodiment of the present invention, the analog-to-digital conversion can be realized only by using the comparison logic, so that a large digital area is not consumed.

In the embodiment of the present invention, the mismatch of the first comparator 112 and the comparator 122 in the operational amplifier 13 and the first-stage successive approximation analog-to-digital converter 11 and the second-stage successive approximation analog-to-digital converter 12 is solved. , calibration is required, including foreground calibration and background calibration. In the foreground calibration, the first-stage successive approximation analog-to-digital converter 11 connects the second end of each of the first capacitor array 113 and the second capacitor array 114 to a common mode level _Vcm , that is, the first stage successively The input signal of the approximation analog-to-digital converter 11 is 0 to perform sampling, comparison, and adjustment of the mismatch of the first comparator 112. Specifically, the input signal is continuously sampled and compared, and the second most significant bit capacitance is counted. The probability of the first reference level +V _R or the second reference level -V _R being connected, continuously adjusting the size and direction of the mismatch calibration of the first comparator 112 until the first capacitor array 113 and the second capacitor array 114 The probability that the second terminal of the most significant bit capacitor is connected to the first reference level +V _R or the second reference level -V _R is 50%, and the calibration of the first stage mode converter 11 is completed. Similarly, the second-stage successive approximation analog-to-digital converter 12 connects the second end of each of the two capacitor arrays at the positive and negative input terminals of the comparator 122 to a common mode level V _cm , that is, a second-order successive approximation type. The input signal of the analog-to-digital converter 12 is 0 for sampling and comparison, and the mismatch of the second comparator is adjusted until the second end of the most significant bit capacitor of the two capacitor arrays at the positive and negative input terminals of the comparator 122 is connected to the first The probability of the reference level +V _R or the second reference level -V _R is 50%. Then, the digital calibration control logic circuit 14 connects each of the first capacitor array 113 and the second capacitor array 114 to a common mode level _Vcm , that is, the input signal is 0, and adjusts the gain of the operational amplifier 13 to make the first The stage successive approximation analog-to-digital converter 11 has two outputs 011...1 and 100...0, and the deviation of the output after the operational amplifier 13 and the second-stage successive approximation analog-to-digital converter 12 reaches a preset value. Wherein, 011...1 indicates that the output of the first-stage successive approximation analog-to-digital converter is '-0', and 100...0 indicates that the output of the first-stage successive approximation analog-to-digital converter is '+0'. This completes the front-end calibration, which helps to improve the effective accuracy of the ADC, and only uses the comparison logic in the foreground calibration.

For background calibration, please refer to FIG. 1 and FIG. 5 together, wherein FIG. 5 depicts the specific structure of the digital calibration control logic circuit 14 shown in FIG. 1. As shown in FIG. 5, the digital calibration control logic circuit 14 includes a multiplier 140, an adder 141, a subtractor 142, a requantization unit 143, a correlator 144, a redundancy correcting unit 145, and an arithmetic unit 146.

In the background calibration, the multiplier 140 is configured to multiply the output Dout1 of the first-stage successive approximation analog-to-digital converter 11 by the weight W of each bit of the first-stage successive approximation analog-to-digital converter 11, wherein the weight W includes an operational amplifier 13 gain deviation information and so on. The adder 141 connects the multiplier 140 and the output Dout2 of the second-stage analog-to-digital converter 12 for adding the output of the multiplier 140 to the output Dout2 of the second-stage successive approximation analog-to-digital converter 12. The subtracter 142 is connected to the adder 141 and receives the digital quantity PN*Td of the pseudo random quantity PN*Ta for subtracting the digital quantity PN*Td of the pseudo random quantity PN*Ta from the output of the adder 141, and then obtaining the calibration The data is output and the calibrated data is output. The calibrated data is the output of the restored first-stage successive approximation analog-to-digital converter 11 after the injected pseudo-random amount PN*Ta is taken out. The requantization unit 143 is connected to the subtractor 142 and the arithmetic unit 146 for applying the weight W to the calibrated data for re-quantization to obtain the re-quantized first-stage output Dout1' and the second-stage output Dout2'. The correlator 144 receives the re-quantized first-stage output Dout1' output from the re-quantization unit 143, and correlates the re-quantized first-stage output Dout1' with the pseudo-random signal PN. The redundancy correction unit 145 is coupled to the correlator 144 to perform redundancy correction on the output of the correlator 144. The operator 146 is connected to the redundancy correcting unit 145 to perform a minimum mean square algorithm operation on the output of the redundancy correcting unit 145 to obtain a convergent weight W, and the multiplier 140 successively approximates the converged weight W with the first level. The output of the analog-to-digital converter 11 is multiplied. The above process is repeated for cyclic calibration to control the gain of the operational amplifier 13 and to obtain a data output. Wherein, the weight W includes the gain deviation information of the operational amplifier 13, and when the output of the redundancy correcting unit 145 is zero, the right of convergence obtained by the operator 146 after performing the least mean square arithmetic operation on the output of the redundancy correcting unit 145 The value is the specific value W0, and the output of the calibrated data is the output after the cycle calibration.

In the embodiment of the present invention, the first-stage successive approximation analog-to-digital converter 11 is a successive comparison analog-to-digital converter with a weight less than 2, and the first-stage successive approximation analog-to-digital converter 11 converges the right of each bit after cyclic calibration. value. The second stage successive approximation analog to digital converter 12 employs a standard binary weight. When the output of the redundancy correcting unit 145 is zero, the weight W of each bit of the first-stage successive approximation analog-to-digital converter 11 converges to a specific value W0. Wherein, the weight W of different bits in the first-order successive approximation analog-to-digital converter 11 converges The specific value W0 is not necessarily the same. When the weight W deviates from the specific value W0 when the environmental conditions change, the weight W needs to be cyclically calibrated, and the environmental conditions include temperature, process angle, power supply, and the like. As shown in FIG. 6, if the weight W is smaller than the specific value W0 to a certain range q, that is, the weight W is smaller than W0-q, the digital calibration control logic circuit 14 increases the gain of the operational amplifier 13. On the other hand, if the weight W is greater than the specific value W0 to a certain range q, that is, the weight W is greater than W0+q, the digital calibration control logic circuit 14 reduces the gain of the operational amplifier 13, wherein a certain range q is obtained by testing. By adjusting the gain of the operational amplifier 13 in real time, the gain effect due to factors such as temperature and power supply voltage variation can be calibrated, thereby improving the effective accuracy of the ADC.

In summary, in the embodiment of the present invention, data acquisition and analog-to-digital conversion of the input signal are completed by the first-stage successive approximation analog-to-digital converter 11, wherein the first-stage successive approximation analog-to-digital converter 11 is applied. There is a pseudo-random quantity whose digital quantity is known, and the residual signal outputted by the first-stage successive approximation analog-to-digital converter 11 is amplified by the operational amplifier 13 and transmitted to the second-stage successive approximation analog-to-digital converter 12, digital calibration control The logic circuit 14 performs cyclic calibration based on the outputs of the first-stage successive approximation analog-to-digital converter 11 and the second-stage successive approximation analog-to-digital converter 12 and a pseudo-random amount to control the gain of the operational amplifier 13 and obtain a data output. Cyclic calibration includes foreground calibration and background calibration, and adjusts the gain of the operational amplifier 13 in real time in the background calibration. It can calibrate the gain effects caused by factors such as temperature and power supply voltage variation, thereby improving the effective accuracy of the ADC.

Figure 7 is a block diagram showing the structure of a self-calibrating apparatus for a pipeline successive comparison analog-to-digital converter according to a second embodiment of the present invention. As shown in FIG. 7, the self-calibration device 20 of the pipeline successively compares the analog-to-digital converter includes a first analog-to-digital converter 21, a second analog-to-digital converter 22, an operational amplifier 23, and a digital calibration control logic circuit 24, and the specific working process. The same as FIG. 1 and will not be described again. The operational amplifier 23 can be a capacitive operational amplifier, that is, a dynamic operational amplifier that uses capacitance programming to perform related programmable calibration.

Referring to FIG. 8, FIG. 8 is a schematic flowchart diagram of a self-calibration method of a pipeline successive analog-to-digital converter according to a first embodiment of the present invention. As shown in FIG. 8, the self-calibration method of the pipeline successively comparing analog-to-digital converters includes:

S10: performing data acquisition and analog-to-digital conversion of an input signal by a first-stage successive approximation analog-to-digital converter, wherein the first-stage successive approximation analog-to-digital converter is applied with a pseudo-random quantity with a known digital quantity .

S11: amplifying the residual signal outputted by the first-stage successive approximation analog-to-digital converter by an operational amplifier and transmitting it to a second-stage successive approximation analog-to-digital converter to drive the second-stage successive approximation analog-to-digital converter to perform the modulo Number conversion.

In the embodiment of the present invention, the input signal is sampled by the first-stage successive approximation analog-to-digital converter in the first quarter period, and is performed by the first-stage successive approximation analog-to-digital converter in the next 1/2 period. Compare successively for analog-to-digital conversion, and transfer the residual signal of the first-stage successive approximation analog-to-digital converter to the second-stage successive approximation analog-to-digital converter through the operational amplifier in the last 1/4 cycle, that is, through the second stage successively The approximation analog-to-digital converter samples the residual signal of the first-order successive approximation analog-to-digital converter. In the next cycle, the signal sampled in the previous cycle is analog-to-digital converted by the second-stage successive approximation analog-to-digital converter in the first 3/4 cycle. Among them, the operational amplifier is a programmable resistive operational amplifier or a capacitive operational amplifier.

S12: Perform cycle calibration according to the output of the first-stage successive approximation analog-to-digital converter and the second-order successive approximation analog-to-digital converter and the pseudo-random quantity to control the gain of the operational amplifier and obtain data output.

In the embodiment of the present invention, the second-stage successive approximation analog-to-digital converter of the first-stage successive approximation analog-to-digital converter includes a comparator internally, and the two input ends of the comparator are respectively connected to a capacitor array of the same structure. There is a mismatch in the comparators in the first-order successive approximation analog-to-digital converter and the second-stage successive approximation analog-to-digital converter. There are also mismatches in the op amp, which requires calibration. Calibration includes foreground calibration and background calibration. Among them, the calibration process of the foreground calibration and the analog-to-digital conversion cannot be performed at the same time, and the error caused by the environmental change cannot be calibrated, while the background calibration can calibrate the error caused by the environmental change.

In S12, as shown in FIG. 10, the background calibration includes:

S123: Multiplying the output of the first-stage successive approximation analog-to-digital converter by the weight of each of the first-order successive approximation analog-to-digital converters and adding the output of the second-stage successive approximation analog-to-digital converter, wherein The weight includes the gain deviation information of the operational amplifier.

In the embodiment of the present invention, the first-stage successive approximation analog-to-digital converter is a successive comparison analog-to-digital converter with a weight less than 2, and the first-stage successive approximation analog-to-digital converter after the cyclic calibration converges the weight of each bit. The second-order successive approximation analog-to-digital converter uses standard binary weights.

S124: Subtract the output obtained by the addition by the digital quantity of the pseudo random quantity to obtain the calibrated data and output the calibrated data.

The calibrated data is the output of the first-stage successive approximation analog-to-digital converter restored after the injected pseudo-random amount is taken out.

S125: Re-quantize the calibrated data application weights to obtain re-quantized first-level output and second-level output.

S126: Correlate the re-quantized first-stage output with a pseudo-random quantity and perform redundancy correction, and perform a least mean square algorithm operation on the redundantly corrected output to obtain a convergence weight, and the convergence weight is further Multiplying the output of the first-order successive approximation analog-to-digital converter, repeating the above process for cyclic calibration, controlling the gain of the operational amplifier, and obtaining the data output; wherein, when the redundantly corrected output is zero, the output is calibrated The subsequent data is the output after cyclic calibration.

In S126, the weight deviates from a specific value when the environmental conditions change, and cyclic calibration is required. The environmental conditions include temperature, process angle, and power supply. When the output of the redundancy correction is zero, the weights of the bits of the first-order successive approximation analog-to-digital converter converge to a specific value W0. Of course, the specific value W0 of the convergence of the different bits is not necessarily the same. If the weight W is smaller than the specific value W0 by a certain range, the gain of the operational amplifier 13 is increased. If the weight is greater than a certain range of the specific value W0, the gain of the operational amplifier 13 is reduced, wherein a certain range is obtained by the test. By adjusting the gain of the operational amplifier in real time, the gain effects of factors such as temperature and supply voltage variation can be calibrated, thereby improving the effective accuracy of the ADC.

In summary, the present invention performs data acquisition and analog-to-digital conversion of an input signal by a first-stage successive approximation analog-to-digital converter, wherein the first-stage successive approximation analog-to-digital converter is applied with a digital quantity known. Pseudo-random quantity; an operational amplifier connected between the first-stage successive approximation analog-to-digital converter and the second-order successive approximation analog-to-digital converter amplifies the residual signal output by the first-stage successive approximation analog-to-digital converter Transmitting to a second-stage successive approximation analog-to-digital converter to drive a second-stage successive approximation analog-to-digital converter for analog-to-digital conversion; the digital calibration control logic circuit is based on a first-stage successive approximation analog-to-digital converter and a second stage The output of the successive approximation analog-to-digital converter and the pseudo-random amount are cyclically calibrated to control the gain of the operational amplifier 13, and the data output is obtained. The cyclic calibration includes foreground calibration and background calibration, and the gain of the operational amplifier is adjusted in real time, and the temperature can be calibrated. The gain effect caused by factors such as the change of the power supply voltage, thereby improving the effective accuracy of the ADC.

The above is only the embodiment of the present invention, and is not intended to limit the scope of the invention, and the equivalent structure or equivalent process transformation of the present invention and the contents of the drawings may be directly or indirectly applied to other related technologies. The fields are all included in the scope of patent protection of the present invention.

Claims (13)

1. A self-calibrating device for sequentially comparing analog-to-digital converters, wherein the device comprises:

   a first-stage successive approximation analog-to-digital converter for performing data acquisition and analog-to-digital conversion of an input signal, wherein the first-stage successive approximation analog-to-digital converter is applied with a pseudo-random quantity of known digital quantity ;

   Second-stage successive approximation analog-to-digital converter;

   An operational amplifier coupled between the first-stage successive approximation analog-to-digital converter and the second-stage successive approximation analog-to-digital converter for outputting the first-stage successive approximation analog-to-digital converter Residing signals are amplified and transmitted to the second-stage successive approximation analog-to-digital converter to drive the second-stage successive approximation analog-to-digital converter for analog-to-digital conversion; wherein the first-stage successive approximation mode The number converter is applied with a pseudo-random quantity of known digital quantity;

   a digital calibration control logic circuit coupled to the first stage successive approximation analog to digital converter, the second stage successive approximation analog to digital converter, and the operational amplifier for use in accordance with the first stage successive approximation An output of the analog to digital converter and the second stage successive approximation analog to digital converter and the pseudo random amount are cyclically calibrated to control the gain of the operational amplifier and to obtain a data output.
2. The self-calibrating apparatus according to claim 1, wherein said digital calibration control logic circuit comprises:

   a multiplier for multiplying an output of the first-stage successive approximation analog-to-digital converter by a weight of each of the first-stage successive approximation analog-to-digital converters, wherein the weight includes the operational amplifier Gain deviation information;

   An adder for adding an output of the multiplier to an output of the second-stage successive approximation analog-to-digital converter;

   a subtracter for subtracting the digital quantity of the pseudo random quantity from the output of the adder to obtain calibrated data and outputting the calibrated data;

   a re-quantization unit, configured to apply the weighted data to the calibrated data for re-quantization to obtain a re-quantized first-level output and a second-level output;

   a correlator configured to correlate the first level output of the requantization unit with the pseudo random amount;

   a redundancy correction unit for performing redundancy correction on an output of the correlator;

   An operator for performing a least mean square algorithm operation on the output of the redundancy correction unit Converging the weight, and the weight of the convergence of the multiplier output is multiplied by the output of the first-stage successive approximation analog-to-digital converter, repeating the above process to perform cyclic calibration, and controlling the operation The gain of the amplifier, and the data output is obtained, wherein when the output of the redundancy correction unit is zero, the outputted calibration data is the output after the loop calibration.
3. The apparatus according to claim 2, wherein said first-stage successive approximation analog-to-digital converter is a successive comparison analog-to-digital converter having a weight less than 2, when the output of said redundant correction unit is zero The weight converges to a particular value (W0), wherein the weight deviates from the particular value as the environmental condition changes, requiring cyclic calibration, including ambient temperature, process angle, and power.
4. The apparatus according to claim 3, wherein said digital calibration control logic increases a gain of said operational amplifier if said weight is less than said specific value (W0); if said weight The value is greater than a certain range (W0) for a certain range, then the digital calibration control logic reduces the gain of the operational amplifier, wherein the certain range is obtained by testing.
5. The apparatus of claim 1 wherein said operational amplifier is a programmable resistive operational amplifier or a capacitive operational amplifier.
6. The self-calibration device according to claim 1, wherein the first-stage successive approximation analog-to-digital converter and the second-order successive approximation analog-to-digital converter respectively comprise:

   The first capacitor array is composed of a plurality of capacitors, wherein the first ends of each capacitor are connected together, and the second end of each capacitor is respectively connected to the first input signal or the reference power through a corresponding control switch Flat, the reference level includes a common mode level, a first reference level, or a second reference level;

   The second capacitor array is composed of a plurality of capacitors and has the same structure as the first capacitor array, wherein the first ends of each capacitor are connected together, and the second ends of each capacitor respectively pass through a corresponding one Controlling a switch connected to the second input signal or the reference level;

   a first successive approximation logic circuit (SAR logic) connecting each of the control switches and connecting the second ends of each of the first capacitor array and the second capacitor array by controlling each of the control switches To the first input signal, the second input signal, or the reference level;

   a first comparator, wherein a first input of the first comparator is coupled to a first end of each of the first capacitor arrays, and a second input of the first comparator is coupled to the first a first end of each capacitor in the array of capacitors, and an output of the first comparator is coupled to the first successive approximation logic circuit;

   Wherein, when sampling is performed, a first end of each capacitor in the first capacitor array is connected to a first input signal, and a first end of each capacitor in the second capacitor array is connected to a second input signal to perform a bottom plate Pick After sampling, the first terminal of each of the first capacitor array and the second capacitor array is connected to a common mode level, and the first comparator performs successive comparisons to make the first capacitor array and a second end of the second capacitor array other than the lowest bit capacitor is selected to be connected to the first reference level or the second reference level, the first capacitor array and the second capacitor array The pseudo-random amount is applied to the second end of the lowest bit capacitance.
7. The self-calibration apparatus according to claim 6, wherein a first end of each of said first capacitor arrays of said first-stage successive approximation analog-to-digital converter is further connected to said operational amplifier And at one end, a first end of each of the capacitors in the second capacitor array of the first-stage successive approximation analog-to-digital converter is further connected to a second end of the operational amplifier, so that the operational amplifier The residual signal output by the first-stage successive approximation analog-to-digital converter is amplified and transmitted to the second-stage successive approximation analog-to-digital converter.
8. The device of claim 7 wherein:

   The first stage successive approximation analog-to-digital converter is further configured to connect a first common terminal level of each of the first capacitor array and the second capacitor array in the internal to a common mode level for sampling And comparing, adjusting a mismatch of the first comparator until a second end of the most significant bit capacitance of the first capacitor array and the second capacitor array is connected to the first reference level or the second The probability of the reference level is 50%;

   The second stage successive approximation analog-to-digital converter is further configured to connect a first common terminal level of each of the first capacitor array and the second capacitor array in the internal to a common mode level for sampling Comparing, adjusting a mismatch of the second comparator, the second end of the most significant bit capacitance of the first capacitor array and the second capacitor array being connected to the first reference level or the second reference The probability of the level is 50%;

   The digital calibration controller is further configured to connect each of the first capacitor array and the second capacitor array in the first-stage successive approximation analog-to-digital converter to a common mode level, and adjust a gain of the operational amplifier such that the two outputs 011...1 and 100...0 of the first stage successive approximation analog-to-digital converter are successively approximated by the operational amplifier and the second stage The deviation of the output after the digital converter reaches the preset value.
9. A pipeline self-calibration method for sequentially comparing analog-to-digital converters, characterized in that the method comprises:

   Data acquisition and analog-to-digital conversion of the input signal are performed by a first-stage successive approximation analog-to-digital converter, wherein the first-stage successive approximation analog-to-digital converter is applied with a pseudo-random quantity of a digital quantity known;

   Performing residual signals output by the first-stage successive approximation analog-to-digital converter through an operational amplifier Amplifying and transmitting to a second-stage successive approximation analog-to-digital converter to drive the second-stage successive approximation analog-to-digital converter for analog-to-digital conversion;

   Performing cyclic calibration according to outputs of the first-stage successive approximation analog-to-digital converter and the second-stage successive approximation analog-to-digital converter and the pseudo-random amount to control gain of the operational amplifier and obtain data Output.
10. The self-calibration method according to claim 9, wherein said output according to said first-stage successive approximation analog-to-digital converter and said second-order successive approximation analog-to-digital converter and said pseudo-random The steps of performing cyclic calibration to control the gain of the operational amplifier and obtaining data output include:

    Multiplying an output of the first-stage successive approximation analog-to-digital converter by a weight of each of the first-stage successive approximation analog-to-digital converters and with an output of the second-stage successive approximation analog-to-digital converter Adding, wherein the weight includes gain deviation information of the operational amplifier;

    Subtracting the obtained output from the digital quantity of the pseudo random amount to obtain calibrated data and outputting the calibrated data;

    Applying the weighted data to the calibrated value for re-quantization to obtain a re-quantized first-level output and a second-level output;

    Correlating the re-quantized first-stage output with the pseudo-random quantity and performing redundancy calibration, performing a least mean square algorithm operation on the redundantly calibrated output to obtain the converged weight, and the convergence The weight is further multiplied by the output of the first-stage successive approximation analog-to-digital converter, the above process is repeated to perform cyclic calibration, the gain of the operational amplifier is controlled, and a data output is obtained, wherein When the output after the redundancy calibration is zero, the output of the calibrated data is the output after the cycle calibration.
11. The method according to claim 10, wherein said first-stage successive approximation analog-to-digital converter is a successive comparison analog-to-digital converter having a weight less than 2, when said redundantly calibrated output is zero The weight converges to a particular value (W0), wherein the weight deviates from the particular value as the environmental condition changes, requiring cyclic calibration, including ambient temperature, process angle, and power.
12. The method according to claim 11, wherein if the weight is less than the specific value (W0) by a certain range, the gain of the operational amplifier is increased; if the weight is greater than a specific value (W0) Within a certain range, the gain of the operational amplifier is reduced, wherein the certain range is obtained by testing.
13. The self-calibration method according to claim 9, wherein the operational amplifier is a programmable resistive operational amplifier or a capacitive operational amplifier.

Images