CN102324940B - Multiplication-type A/D (Analog/Digital) converter capable of correcting limited gain error - Google Patents
Multiplication-type A/D (Analog/Digital) converter capable of correcting limited gain error Download PDFInfo
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- CN102324940B CN102324940B CN2011101780897A CN201110178089A CN102324940B CN 102324940 B CN102324940 B CN 102324940B CN 2011101780897 A CN2011101780897 A CN 2011101780897A CN 201110178089 A CN201110178089 A CN 201110178089A CN 102324940 B CN102324940 B CN 102324940B
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Abstract
The invention relates to a multiplication-type A/D (Analog/Digital) converter capable of correcting a limited gain error, which comprises an amplifying circuit unit and a limited gain error correcting circuit unit. According to the invention, two compensation capacitors and an amplifier constitute the limited gain error correcting circuit unit, part of output quantity is adjustably compensated into the input end of an operation amplifier, nonzero /virtual earth/ is adjusted, and the limited gain error is greatly reduced; after the adoption of the limited gain error correcting circuit unit, the limited gain error of the whole streamlined A/D converter is reduced by one order of magnitude; and in the invention, gain of the amplifier is adjustable, and therefore the limited gain error caused by temperature and process changes is effectively offset. According to the invention, the limited gain error correcting circuit has the characteristics of small limited gain error, low power consumption and high reliability and is suitable for the fields of high-speed, high-precision, low power-consumption streamlined A/D converters.
Description
Technical field
The present invention relates to a kind of multiplication type digital to analog converter of recoverable finite gain error, its direct application is high-speed, high precision, low-power consumption assembly line A/D converter.
Background technology
Multiplication type digital to analog converter is the sub level core cell of pipeline a/d converter, and Fig. 1 has provided the basic structure of a fully differential multiplication type digital to analog converter.The advantage of this structure is to have utilized feedback principle, makes gain equal sampling capacitance C
sWith feedback capacity C
fRatio, improved precision and the linearity of gain.But the gain error of this structure is too big, and main source has two places: 1) sampling capacitance C
sWith feedback capacity C
fPrecision and matching degree limited, make its ratio can not accurately equal the circuit design value, cause the inter-stage gain error.2) the direct current finite gain of operational amplifier A makes that " virtual earth " equivalence of amplifier input is imperfect, causes the inter-stage gain error.
For above two source of errors, first mainly is subjected to the influence of manufacturing process; Second error source, originally can solve by the DC current gain that improves operational amplifier, but be for the multiplication pattern number converter that the low-power consumption demand is arranged, the DC current gain of operational amplifier will be limited, can not do very greatly, representative value is about about 60dB, so the finite gain error of low-power consumption multiplication type digital to analog converter is difficult to reduce.
Summary of the invention
Technical problem to be solved by this invention is to invent a kind of multiplication type digital to analog converter of recoverable finite gain error, reduces its finite gain error, realizes the low-power consumption of circuit simultaneously.
For achieving the above object, the present invention solves the problems of the technologies described above the multiplication type digital to analog converter that the technical scheme of taking is recoverable finite gain error of the present invention and contains:
An amplifier circuit unit comprises: operational amplifier A 2, sampling capacitance C
S1+And C
S1-, feedback capacity C
F1+And C
F1-, interconnection box S
S1+And S
S1-, interconnection box S
R1+And S
R1-, interconnection box S
F1+And S
F1-, wherein,
C
S1+An end pass through S
S1+Connect forward input signal V
In+And pass through S
R1+Connect reference voltage, C
S1+The negative input end of another termination A2, C
F1+An end pass through S
S2+Connect forward input signal V
In+And pass through S
F1+The positive output end that connects A2, C
F1+The other end be connected C with the negative input end of A2
S1-An end pass through S
S1-Connect negative sense input signal V
In-And pass through S
R1-Connect reference voltage, C
S1-The other end be connected C with the positive input terminal of A2
F1-An end pass through S
S2-Connect negative sense input signal V
In-And pass through S
F1-The negative output terminal that connects A2, C
F1-The other end be connected with the positive input terminal of A2; With
A finite gain error correction circuit unit comprises: variable gain amplifier A3, building-out capacitor C
Cal+And C
Cal-, interconnection box S
1+And S
1-, interconnection box S
2+And S
2-, wherein,
C
Cal+An end pass through S
1+The positive input terminal that connects A2, C
Cal+The other end connect the positive output end of A3, the negative input end of A3 passes through S
2+Be connected C with the negative output terminal of A2
Cal-An end pass through S
1-The negative input end that connects A2, C
Cal-The other end connect the negative output terminal of A3, the positive input terminal of A3 passes through S
2-Be connected with the positive output end of A2.
Described interconnection box S
S1+And S
S1-, interconnection box S
R1+And S
R1-, interconnection box S
F1+And S
F1-, interconnection box S
1+And S
1-, interconnection box S
2+And S
2-Be conventional cmos switch.
Described sampling capacitance C
S1+And C
S1-, feedback capacity C
F1+And C
F1-Be conventional metal capacitance, capacitance is 1～2pF.
Described operational amplifier A 2 is conventional operational amplifier, and its gain is 40～60dB.
Described building-out capacitor C
Cal+And C
Cal-Be the metal capacitance of routine, capacitance is 10～50fF.
Described amplifier A3 is conventional variable gain amplifier, by adjusting the gain G of A3
A3, to offset the error that manufacturing process and variations in temperature are brought.
Beneficial effect:
Compare with the multiplication type digital to analog converter of routine, the multiplication type digital to analog converter of recoverable finite gain error of the present invention has the following advantages:
1. the present invention is by two building-out capacitor C
Cal+, C
Cal-With an amplifier A3, form correcting circuit, part output variable adjustable ground is compensated to the input of operational amplifier A 2, adjust " virtual earth " is non-vanishing, greatly reduced the finite gain error.Contrast the graph of relation of operational amplifier gain and inter-stage gain error in circuit of the present invention and the conventional multiplication type digital to analog converter, be comparison diagram 4 and Fig. 3, be that 65dB is example with the gain, their gain error is respectively 0.11% and 0.01%, as can be known, after adopting circuit of the present invention, 1 order of magnitude of the finite gain error of whole pipeline a/d converter decline.
2. the present invention adopts finite gain error correction circuit unit, has reduced the gain error of custom circuit, has reduced the DC current gain requirement of operational amplifier, thereby has reduced the power consumption of pipeline a/d converter.Operational amplifier unit in the conventional 12 bit stream waterline A/D converters 85dB that need gain, power consumption is about 16～18mW.After adopting circuit of the present invention, the operational amplifier unit in the 12 bit stream waterline A/D converters only needs the 62dB that gains, and just can satisfy 12 required precisions, and its power consumption is about 6～8mW, and power consumption reduces 50%.
3. in the circuit of the present invention, the gain of amplifier A3 is adjustable, has effectively offset the finite gain error that temperature and technique change are brought, and makes the reliability height of circuit of the present invention.
Description of drawings
Fig. 1 is the circuit diagram of the multiplication type digital to analog converter of routine;
Fig. 2 is the circuit diagram of multiplication type digital to analog converter of the present invention;
Fig. 3 is the graph of relation of operational amplifier gain and inter-stage gain error in the conventional multiplication type digital to analog converter;
Fig. 4 is the operational amplifier gain of multiplication type digital to analog converter of the present invention and the graph of relation of inter-stage gain error.
Embodiment
The specific embodiment of the present invention is not limited only to following description, is now further specified by reference to the accompanying drawings.
The circuit diagram of multiplication type digital to analog converter of the present invention as shown in Figure 2.Its basic composition comprises an amplifier circuit unit and a finite gain error correction circuit unit.Amplifier circuit unit comprises: operational amplifier A 2, sampling capacitance C
S1+And C
S1-, feedback capacity C
F1+And C
F1-, interconnection box S
S1+And S
S1-, interconnection box S
R1+And S
R1-, interconnection box S
F1+And S
F1-Finite gain error correction circuit unit comprises: variable gain amplifier A3, building-out capacitor C
Cal+And C
Cal-, interconnection box S
1+And S
1-, interconnection box S
2+And S
2-
Concrete annexation among Fig. 2, interactively are identical with the summary of the invention part of this specification, no longer repeat herein.Its operation principle is as follows:
When circuit is in sample phase, switch S
S1+And S
S1-, S
S2+And S
S2-Closure, switch S
F1+And S
F1-, S
R1+And S
R1-, S
1+And S
1-, S
2+And S
2-Disconnect, input signal is saved on sampling capacitance and the feedback capacity.At this moment, not working in finite gain error correction circuit unit, is in cleared condition.
When circuit is in amplification stage, switch S
S1+And S
S1-, S
S2+And S
S2-Disconnect switch S
F1+And S
F1-, S
R1+And S
R1-, S
1+And S
1-, S
2+And S
2-Closure, sampling capacitance connects reference voltage, and feedback capacity is connected operational amplifier A 2 input and output two ends.By charge conservation, input signal is amplified to the output of operational amplifier A 2.At this moment, the finite gain error correction circuit is started working, and its input and output two ends are connected the input/output terminal of operational amplifier A 2, part output variable adjustable ground is compensated to the input of operational amplifier A 2, adjust " virtual earth " is non-vanishing, greatly reduced the finite gain error.At this moment, the inter-stage gain expressions is:
Wherein, C
s=C
S1+=C
S1-, C
f=C
F1+=C
F1-, C
Cal=C
Cal+=C
Cal-, G
A2, G
A3The DC current gain of representing operational amplifier A 2, A3 respectively.
From (1) formula as can be seen, if do not introduce finite gain error correction circuit unit, i.e. G
A3, C
CalTwo is zero, and when the DC current gain of operational amplifier A 2 has in limited time, the inter-stage gain is not equal to the ratio between sampling capacitance and the feedback capacity, has gain error;
After introducing finite gain error correction circuit unit, even operational amplifier A 2 DC current gain are limited, if in the denominator second and third, four sums are zero, then multiplication type digital to analog converter still can keep desirable inter-stage gain.Therefore, by selecting the gain of suitable capacitance and operational amplifier, satisfy expression formula (2), can reach the purpose of the finite gain error of proofreading and correct multiplication type digital to analog converter.
For offsetting the margin of error that manufacturing process and variations in temperature are brought, the gain of amplifier A3 is adjustable, by adjusting the yield value G of A3
A3, guarantee expression formula (2) establishment all the time.
Described interconnection box S
S1+And S
S1-, interconnection box S
R1+And S
R1-, interconnection box S
F1+And S
F1-, interconnection box S
1+And S
1-, interconnection box S
2+And S
2-Be conventional cmos switch.
Described sampling capacitance C
S1+And C
S1-, feedback capacity C
F1+And C
F1-Be conventional metal capacitance, capacitance is 1～2pF.
Described amplifier A2 is conventional operational amplifier, and its gain is 40～60dB.
Described building-out capacitor C
Cal+And C
Cal-Be the metal capacitance of routine, capacitance is 10～50fF.
Described amplifier A3 is conventional variable gain amplifier, by adjusting the gain G of A3
A3, to offset the error that manufacturing process and variations in temperature are brought.
Claims (6)
1. the multiplication type digital to analog converter of a recoverable finite gain error is characterized in that containing:
An amplifier circuit unit comprises: operational amplifier A 2, sampling capacitance C
S1+And C
S1-, feedback capacity C
F1+And C
F1-, interconnection box S
S1+And S
S1-, interconnection box S
R1+And S
R1-, interconnection box S
F1+And S
F1-, wherein,
C
S1+An end pass through S
S1+Connect forward input signal V
In+And pass through S
R1+Connect reference voltage, C
S1+The negative input end of another termination A2, C
F1+An end pass through S
S2+Connect forward input signal V
In+And pass through S
F1+The positive output end that connects A2, C
F1+The other end be connected C with the negative input end of A2
S1-An end pass through S
S1-Connect negative sense input signal V
In-And pass through S
R1-Connect reference voltage, C
S1-The other end be connected C with the positive input terminal of A2
F1-An end pass through S
S2-Connect negative sense input signal V
In-And pass through S
F1-The negative output terminal that connects A2, C
F1-The other end be connected with the positive input terminal of A2; With
A finite gain error correction circuit unit comprises: variable gain amplifier A3, building-out capacitor C
Cal+And C
Cal-, interconnection box S
1+And S
1-, interconnection box S
2+And S
2-, wherein,
C
Cal+An end pass through S
1+The positive input terminal that connects A2, C
Cal+The other end connect the positive output end of A3, the negative input end of A3 passes through S
2+Be connected C with the negative output terminal of A2
Cal-An end pass through S
1-The negative input end that connects A2, C
Cal-The other end connect the negative output terminal of A3, the positive input terminal of A3 passes through S
2-Be connected with the positive output end of A2.
2. the multiplication type digital to analog converter of recoverable finite gain error according to claim 1 is characterized in that described interconnection box S
S1+And S
S1-, interconnection box S
R1+And S
R1-, interconnection box S
F1+And S
F1-, interconnection box S
1+And S
1-, interconnection box S
2+And S
2-Be conventional cmos switch.
3. the multiplication type digital to analog converter of recoverable finite gain error according to claim 1 is characterized in that described sampling capacitance C
S1+And C
S1-, feedback capacity C
F1+And C
F1-Be conventional metal capacitance, capacitance is 1～2pF.
4. the multiplication type digital to analog converter of recoverable finite gain error according to claim 1 is characterized in that described operational amplifier A 2 is conventional operational amplifier, and its gain is 40～60dB.
5. the multiplication type digital to analog converter of recoverable finite gain error according to claim 1 is characterized in that described building-out capacitor C
Cal+And C
Cal-Be the metal capacitance of routine, capacitance is 10～50fF.
6. the multiplication type digital to analog converter of recoverable finite gain error according to claim 1 is characterized in that described amplifier A3 is conventional variable gain amplifier, by adjusting the gain G of A3
A3, to offset the error that manufacturing process and variations in temperature are brought.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101780897A CN102324940B (en) | 2011-06-29 | 2011-06-29 | Multiplication-type A/D (Analog/Digital) converter capable of correcting limited gain error |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101780897A CN102324940B (en) | 2011-06-29 | 2011-06-29 | Multiplication-type A/D (Analog/Digital) converter capable of correcting limited gain error |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102324940A CN102324940A (en) | 2012-01-18 |
| CN102324940B true CN102324940B (en) | 2013-08-07 |
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|---|---|---|---|
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| CN103067013B (en) * | 2012-12-18 | 2014-06-25 | 天津大学 | Craft imbalance non-sensitive cyclic analog-digital converter and conversion method |
| CN103888141B (en) * | 2014-04-09 | 2017-10-27 | 华为技术有限公司 | Streamline gradually compares the method for self-calibrating and device of analog-digital converter |
| CN111211785B (en) * | 2018-11-22 | 2023-04-07 | 瑞昱半导体股份有限公司 | Correction method applied to digital-to-analog converter and related circuit |
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| US7199654B1 (en) * | 2005-06-17 | 2007-04-03 | Ess Technology, Inc. | Multi-stage amplifier with switching circuitry |
| US7911370B2 (en) * | 2009-06-25 | 2011-03-22 | Mediatek Inc. | Pipeline analog-to-digital converter with programmable gain function |
| US7969334B2 (en) * | 2009-10-30 | 2011-06-28 | Texas Instruments Incorporated | Apparatus for correcting setting error in an MDAC amplifier |
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Effective date of registration: 20220802 Address after: No.23 Xiyong Avenue, Shapingba District, Chongqing 401332 Patentee after: CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION CHONGQING ACOUSTIC-OPTIC-ELECTRONIC CO.,LTD. Address before: 400060 Chongqing Nanping Nan'an District No. 14 Huayuan Road Patentee before: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY Group Corp. |
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Address after: No.23 Xiyong Avenue, Shapingba District, Chongqing 401332 Patentee after: CETC Chip Technology (Group) Co.,Ltd. Address before: No.23 Xiyong Avenue, Shapingba District, Chongqing 401332 Patentee before: CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION CHONGQING ACOUSTIC-OPTIC-ELECTRONIC CO.,LTD. |
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Effective date of registration: 20230410 Address after: Room 2-2, No. 2, Linxie Family Courtyard Group, Zaojeshu Village, Fenghuang Town, Shapingba District, Chongqing, 401334 Patentee after: Chongqing Jixin Technology Co.,Ltd. Address before: No.23 Xiyong Avenue, Shapingba District, Chongqing 401332 Patentee before: CETC Chip Technology (Group) Co.,Ltd. |