JP2020188454A - Successive approximation ad converter and pipeline ad converter - Google Patents

Abstract

To provide a successive approximation AD converter and a pipeline AD converter that are not delayed by sample hold.SOLUTION: A successive approximation AD converter 1 includes: reception circuits 107 and 117 that output an analog input signal AinO corresponding to a received analog input signal Ain; subtractors 108a and 118a that calculate a differential signal between the analog input signal AinO at each of n sequential conversions and a comparison signal obtained by AD-converting control values DA0 and DA1 with DA converters 109 and 119; comparators 104 and 114 that determine a high-low relation of voltage of the differential signal with respect to reference voltage VC; a control circuit 101 that updates the control values DA0 and DA1 so that the comparison signal approaches the analog input signal AinO based on comparison results; and an output register 102 that outputs a digital output signal Vout based on the comparison results of the comparators 104 and 114.SELECTED DRAWING: Figure 1

Description

The present invention relates to a successive approximation type AD converter (AD converter) and a pipeline type AD converter.

Conventionally, in the active noise canceling (ANC) system of headphones, first, external noise is AD-converted. Next, the sound that cancels the noise component that reaches the ear among the AD-converted noise is calculated by the DSP (Digital Signal Processor). Then, by DA-converting this calculation result and outputting it from the headphones, the noise reaching the ears is canceled. At this time, if the AD conversion takes a long time, the signal for canceling the noise cannot catch up with the noise coming from the outside, and the noise cannot be completely canceled. Therefore, in such a system, an AD converter with a small conversion delay is desired. As an AD converter with less delay, for example, the pipeline type A / D converter described in Patent Documents 1 and 2 is known. Further, as an AD converter, a sequential comparison type A / D converter described in Patent Document 3 is known.

Japanese Unexamined Patent Publication No. 2003-163597 U.S. Pat. No. 8643529 Japanese Unexamined Patent Publication No. 2011-114577

An object of the present invention is to provide a sequential comparison type A / D converter and a pipeline type A / D converter without delay due to sample hold.

In order to achieve the above object, the sequential comparison type A / D converter according to the embodiment of the present invention receives the first analog input signal and outputs the second analog input signal corresponding to the first analog input signal. A receiving circuit that outputs continuously, and a difference signal calculation circuit that calculates the difference signal between the second analog input signal and the analog reference signal at each of n times (n is a natural number of 2 or more, the same applies hereinafter). Based on the determination circuit for determining whether or not the voltage of the difference signal is higher than the reference voltage and the determination result of the determination circuit, the reference value so that the analog reference signal approaches the second analog input signal. A reference value calculation circuit for updating the above, a DA converter for converting the reference value into the analog reference signal, and an output circuit for outputting a digital output signal based on the determination result of the determination circuit are provided.

Further, in order to achieve the above object, the pipeline type AD converter according to the embodiment of the present invention is a pipeline type AD converter having a plurality of stages connected in cascade and a final stage. Each of the plurality of stages outputs an analog output of a first sequential comparison type sub-AD converter that converts an analog input signal into a digital output signal and the digital output signal output by the first sequential comparison type sub-AD converter. It has a DA converter that converts a signal, and an amplification circuit that amplifies a signal that is the difference between the analog input signal and the analog output signal. In addition, the final stage has a second successive approximation type sub-AD converter that converts the difference signal output by the final stage of the plurality of stages into a digital output signal. The first and second sequential comparison type sub-AD converters are composed of the sequential comparison type AD converter.

According to the present invention, the difference signal between the second analog input signal and the analog reference signal corresponding to the first analog input signal received by the receiving circuit at the time of the determination timing in the determination unit can be sequentially determined. It is possible. This makes it possible to perform AD conversion processing on an analog input signal that changes in real time, instead of a fixed analog input signal that is sample-held. As a result, it is possible to eliminate the delay due to the sample hold as compared with the configuration in which the fixed analog input signal sample-held is subjected to AD conversion processing, and the conversion speed can be improved.

It is a figure which shows the basic structure of the sequential comparison type AD converter which concerns on 1st Embodiment, FIG. 1 (a) is a figure which shows the basic structure of a single-ended structure, and FIG. 1 (b) is a figure which shows the differential structure. It is a figure which shows the basic structure of. It is a figure which shows the specific structure of the sequential comparison type AD converter of the single-ended structure which concerns on 1st Embodiment. It is a figure which shows the correspondence relationship of the control value NEG, D1, D2, D3, DA0 and the value of the 2nd term of the equation (4) when "n = 4" is set. It is a block diagram which showed the switched capacitor circuit for comparison by the block for each function. It is a figure which shows an example of the relationship between the analog input signal Ain and the digital output signal Vout of the sequential comparison type AD converter which concerns on 1st Embodiment. It is a figure which shows an example of the relationship between the comparison voltage at the time of the comparison operation of the sequential comparison type AD converter which concerns on 1st Embodiment, and the number of comparison operations. It is a figure which shows an example of the relationship between the comparative voltage and the analog input voltage when the analog input voltage of the sequential comparison type AD converter which concerns on 1st Embodiment changes. It is a figure which shows an example of the relationship between the comparison voltage and the number of comparison operations at the time of the comparison operation of the sequential comparison type AD converter of the related technology. It is a figure which shows an example of the relationship between the comparative voltage and the analog input voltage when the analog input voltage of the sequential comparison type AD converter of the related art changes. FIG. 10 (a) is a diagram showing an example of an analog input signal waveform, a comparison voltage, a clock signal waveform, a comparison result, and a time change of a digital output code during a comparison operation of the sequential comparison type AD converter according to the first embodiment. ) Is a diagram for explaining a configuration in which a 5-bit output can be obtained, and FIG. 10 (b) is a diagram for explaining a configuration in which a 6-bit output can be obtained. It is a figure which shows the basic structure of the sequential comparison type AD converter of the single-ended structure which concerns on 2nd Embodiment. It is a figure which shows the specific structure of the sequential comparison type AD converter of the single-ended structure which concerns on 2nd Embodiment. It is a figure which shows the specific structure of the sequential comparison type AD converter of the 3rd Embodiment. It is a block diagram which shows the structural example of the pipeline type AD converter which concerns on 4th Embodiment. It is a block diagram which shows the specific structural example of the unit block which concerns on 4th Embodiment. It is a timing chart at the time of the comparison operation of the sequential comparison type sub AD converter which constitutes the unit block of the first stage of the pipeline type AD converter which concerns on 4th Embodiment and the next stage. It is a figure which shows an example of the pipeline type AD converter of the related technology. It is a figure which shows the operation example of the pipeline type A / D converter using the sequential comparison type AD converter of the related technology. It is a figure which shows an example of the basic structure of the sequential comparison type AD converter of a related technique. It is a figure which shows an example of the specific structure of the sequential comparison type AD converter of a related technique. It is a timing chart of each signal of the sequential comparison type AD converter shown in FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the description of the drawings referred to in the following description, the same or similar parts are designated by the same or similar reference numerals.
Further, the embodiments shown below exemplify devices and methods for embodying the technical idea of the present invention, and the technical idea of the present invention describes the structure, arrangement, etc. of the components as follows. It is not specific to anything. The technical idea of the present invention may be modified in various ways within the technical scope specified by the claims stated in the claims.

In explaining each embodiment of the present invention, first, the related techniques of each embodiment of the present invention will be described with reference to FIGS. 17 to 21.
As shown in FIG. 17, the pipeline type A / D converter as a related technology has unit blocks 10-1 to 10-4, an A / D converter 11, and an encoder 12, and each unit block has a unit block. , Sub-A / D converter 13 (hereinafter referred to as "sub-A / D converter"), D / A converter 14, subtractor 15, and amplifier 16. The sub-A / D converter converts the analog signal Vin input to each unit block into a digital signal. As the sub-A / D converter of a general pipeline type A / D converter, a flash type A / D converter composed of a plurality of comparators having different threshold values is used. This is because the flash type A / D converter does not have a conversion delay unlike the sequential comparison type A / D converter and can perform high-speed conversion.

In the pipeline type A / D converter, the signal is sequentially propagated from the first unit block to the subsequent unit block in synchronization with the clock, so that the signal propagation process between the unit blocks is a conversion delay. Although the conversion delay can be shortened by reducing the number of unit blocks, it cannot be converted into a digital signal having a desired number of bits. Therefore, it is necessary to increase the bit resolution in each unit block by the amount that the unit block is reduced. However, if the bit width is increased by the flash type A / D converter, the number of comparators increases exponentially, and the power consumption and the cost increase. For example, a 2-bit flash A / D converter requires three comparators, but a three-bit flash A / D converter increases to seven. Specifically, an n-bit flash type A / D converter requires 2 ^n- 1 comparators.

On the other hand, the pipeline type A / D converter described in Patent Document 2 is a sequential comparison type A / D converter which is an A / D converter whose circuit area can be suppressed with low power consumption (Patent Document 2). A pipeline type A / D converter is constructed by using (called "SAR").
In this pipeline type A / D converter, as shown in FIG. 18, three processes of Sample (sample processing of the signal to be converted), SAR (sequential comparison), and Outputting (result output) are performed as sequential comparison processing. ing. Since the sequential comparison process must perform the above three processes, for example, as shown in the part surrounded by a square in FIG. 18, the OP-AMP Reset operation in the analog adder / subtractor is performed during the SAR operation period. Then, there is a period for waiting for the end of the SAR operation.

Further, conventionally, as a sequential comparison type A / D converter, for example, a configuration in which a sample hold function and a D / A conversion function are simultaneously realized is disclosed (see Patent Document 3).
Here, FIG. 19 is a circuit diagram showing an example of a conventional charge comparison type sequential comparison type A / D converter. Further, FIG. 20 is a diagram in which the circuit diagram of FIG. 19 is blocked for each function.
The sequential comparison type A / D converter shown in FIG. 19 converts the analog input signal Ain into a digital output Vout of n bits (n is a natural number of 3 or more). In FIG. 20, the S / H is a sample hold circuit, and the D / A converter is a circuit that converts a digital value into an analog value. As shown in the circuit diagram of FIG. 19, in general, the S / H and the D / A converter are often realized by sharing a capacitor. That is, after the analog input voltage is sampled in the capacitor, D / A conversion and addition / subtraction are performed using the capacitor.

In the sequential comparison type A / D converter of Patent Document 3, after the analog input signal Ain is sampled in advance, a sequential comparison operation is performed on the sampled Ain while changing the value of the D / A converter, and finally. Obtain the digital conversion result. Here, FIG. 21 is a diagram showing an example of time changes in the voltage to be determined, the clock signal waveform, and the determination result during the comparison operation of the sequential comparison type A / D converter of Patent Document 3 (FIG. 19). FIG. 21 shows an example of plotting the voltage to be determined, an example of the clock signal CLK, and an example of the value of the determination result DN.

That is, as shown in FIG. 19, the sequential comparison type A / D converter of Patent Document 3 has a D / A conversion function and a sample hold function realized by one circuit, and therefore must be processed in a time division manner. Must be. Therefore, as shown in the period of the double-headed arrow line in FIG. 21, from the time when the analog input signal Ain is sampled until the comparison operation with respect to the determined voltage generated based on the sampled analog input signal Ain is completed. Has a delay. That is, in the conventional successive approximation type A / D converter, from the time when the analog input signal Ain is sampled to the time when the A / D conversion result of the analog input signal Ain is output, the double arrow line in FIG. There is a delay for the indicated period. This also applies to the pipeline type A / D converter described in Patent Document 2, which uses a sequential comparison type A / D converter as the sub A / D converter, and the comparison operation is performed after the analog input voltage is sampled. There is a delay before it finishes.

On the other hand, the successive approximation type A / D converter and the pipeline type A / D converter according to each embodiment of the present invention have a configuration in which there is no delay due to sample hold.

[First Embodiment]
[Basic configuration]
First, the basic configuration of the successive approximation type AD converter according to the first embodiment of the present invention will be described with reference to FIG. FIG. 1A is a diagram showing a basic configuration of a single-ended sequential comparison type AD converter according to the first embodiment, and FIG. 1B is a diagram showing a sequential differential configuration according to the first embodiment. It is a figure which shows the basic structure of the comparative type AD converter.

As shown in FIG. 1A, the single-ended sequential comparison type AD converter 1 according to the first embodiment includes a control circuit 101, an output register 102, a comparator 104 and 114, and a switch for comparison. It includes capacitor circuits 108 and 118. Here, the control circuit 101 corresponds to the reference value calculation circuit described in the claims, the output register 102 corresponds to the output circuit described in the claims, and the comparators 104 and 114 correspond to the claims. Corresponds to the judgment circuit described in the range of.

The comparison switched capacitor circuit 108 includes a reception circuit 107, a subtractor 108a, and a DA converter 109, and the comparison switched capacitor circuit 118 includes a reception circuit 117, a subtractor 118a, and a DA converter 119. And. Note that DA0 and DA1 in FIG. 1A are control values generated by the control circuit 101 and are for controlling the DA converters 109 and 119. Here, the subtractors 108a and 118a correspond to the difference signal calculation circuit described in the claims, and the control values DA0 and DA1 correspond to the reference values described in the claims.

The receiving circuits 107 and 117 output a signal corresponding to the analog input signal Ain input to the signal input terminal Ain. For example, the analog input signal Ain can be adjusted to a desired amplitude, or the DA converter 109 and It is an adjustment circuit necessary for adding and subtracting from the output signal of 119. Hereinafter, the signal corresponding to the analog input signal Ain output from the receiving circuits 107 and 117 is referred to as “analog input signal AinO”. Here, the analog input signal Ain corresponds to the first analog input signal described in the claims, and the analog input signal AinO corresponds to the second analog input signal described in the claims.
In the first embodiment, assuming that the analog input signal Ain and the analog input signal AinO are equivalent, the analog input signal AinO output from the receiving circuits 107 and 117 is hereinafter referred to as "analog input signal Ain".

In the single-ended configuration, the subtractors 108a and 118a calculate the difference signal between the analog input signals Ain output from the receiving circuits 107 and 117 and the output signals of the DA converters 109 and 119. Then, the difference signals output from the subtractors 108a and 118a are input to the non-inverting input terminals of the comparators 104 and 114. Hereinafter, the signal voltage of the difference signal between the analog input signal Ain and the output signal of the DA converter 109 is referred to as "difference voltage SN0", and the signal of the difference signal between the analog input signal Ain and the output signal of the DA converter 119. The voltage is referred to as "difference voltage SN1".

The comparator 104 compares the differential voltage SN0 with the reference voltage VC, and the comparator 114 compares the differential voltage SN1 with the reference voltage VC. Here, the reference voltage VC corresponds to the first reference voltage described in the claims. Then, based on these comparison results, the magnitude relationship between the differential voltages SN0 and SN1 and the reference voltage VC is determined. Based on the comparison results DO0 and DO1, the control circuit 101 updates the control values DA0 and DA1 so that the output signals of the DA converters 109 and 119 approach the analog input signals Ain. Further, the output register 102 of the first embodiment corresponds to the analog input signal Ain based on the comparison results DO0_1 to DO0_n and DO1_1 to DO1_n of the high-low relationship performed n times (n is a natural number of 3 or more, the same applies hereinafter). The digital output signal Vout of n + 1) bits is calculated. Here, the comparison results DO0 and DO1 correspond to the determination results described in the claims.

On the other hand, as shown in FIG. 1 (b), the differentially configured successive approximation type AD converter 1A according to the first embodiment is a comparative switched capacitor in the single-ended configuration sequential comparison type AD converter 1. The configurations of the circuits 108 and 118 are partially different. That is, in the differential configuration, the comparative switched capacitor circuits 108A and 118A are provided in place of the comparative switched capacitor circuits 108 and 118. The comparative switched capacitor circuit 108A includes a receiving circuit 107A, subtractors 108a and 108b, and a DA converter 109A, and the comparative switched capacitor circuit 118A includes a receiving circuit 117A, subtractors 118a and 118b, and the like. It is equipped with a DA converter 119A.

The receiving circuits 107A and 117A adjust the analog input signals Ain_P and Ain_N, which are input to the signal input terminals Ain_P and Ain_N and have a mutually opposite phase relationship, to a desired amplitude, and the output of the DA converters 109A and 119A. It is an adjustment circuit required for addition and subtraction. Hereinafter, the signals corresponding to the analog input signals Ain_P and Ain_N output from the receiving circuits 107A and 117A will be referred to as "analog input signals AinO_P and AinO_N". Here, the analog input signals Ain_P and Ain_N correspond to the first analog input signal described in the claims, and the analog input signals AinO_P and AinO_N correspond to the second analog input signal described in the claims.

In the first embodiment, assuming that the analog input signals Ain_P and Ain_N and the analog input signals AinO_P and AinO_N are equivalent, the analog input signals AinO_P and AinO_N output from the receiving circuits 107A and 117A are hereinafter referred to as "analog input signals Ain_P and AinO_N. It is called "Ain_N".
In the differential configuration, the subtractors 108a and 118a calculate the difference signal between the analog input signals AinO_P output from the receiving circuits 107A and 117A and the output signals of the DA converters 109A and 119A. Further, the subtractors 108b and 118b calculate the difference signal between the analog input signals AinO_N output from the receiving circuits 107A and 117A and the output signals of the DA converters 109A and 119A.

Then, the difference signals output from the subtractors 108a and 118a and 108b and 118b are input to the non-inverting input terminals of the comparators 104 and 114. Hereinafter, the voltage of the difference signal between each of the analog input signals Ain_P and Ain_N and the output signal of the DA converter 109A will be referred to as "difference voltage SN0_P and SN0_N". Further, the voltage of the difference signal between each of the analog input signals Ain_P and Ain_N and the output signal of the DA converter 119A is referred to as "difference voltage SN1_P and SN1_N".

The comparator 104 compares the differential voltage SN0_P with the differential voltage SN0_N, and the comparator 114 compares the differential voltage SN1_P with the differential voltage SN1_N. Then, the high-low relationship between the differential voltage SN0_P and the differential voltage SN0_N and the high-low relationship between the differential voltage SN1_P and the differential voltage SN1_N are determined. Here, the differential voltage SN0_N and the differential voltage SN1_N correspond to the reference voltages described in the claims. It should be noted that this reference voltage is different from the reference voltage VC used in the single-ended configuration.
Note that the differential configuration provides higher resistance to common mode noise and external interference than the single-ended configuration.

Further, the sequential comparison type AD converters 1 and 1A according to the first embodiment are configured to include two sets of a comparator and a switched capacitor circuit for comparison, but the configuration is not limited to this. For example, the configuration may include only one set of the comparator and the switched capacitor circuit for comparison, or may include three or more sets.
In addition, the single-ended sequential comparison type AD converter 1 will be described in detail below.

[Specific configuration example of successive approximation type AD converter 1]
The successive approximation type AD converter 1 according to the first embodiment AD-converts an analog input signal Ain into a (n + 1) bit digital output signal Vout.
As shown in FIG. 2, the successive approximation type AD converter 1 includes a control circuit 101, an output register 102, comparators 104 and 114, and comparative switched capacitor circuits 108 and 118.

The comparative switched capacitor circuit 108 includes switches 103a to 103c, a receiving circuit 107, a storage node SN0, and a DA converter 109. Here, the switch 103c corresponds to the first switch circuit described in the claims.
In the first embodiment, the receiving circuit 107 is composed of a capacitor having a capacitance of Cin. The receiving circuit 107 has a role of transmitting (adding) the analog input signal Ain input to the signal input terminal Ain to the storage node SN0 which is an input node of the comparator 104. Here, the capacitor of the capacitance Cin constituting the receiving circuit 107 corresponds to the first capacitance element described in the claims.

The DA converter 109 includes a switch group 105_1 to 105_ (n + 1) and a capacitor 106_1 to 106_ (n + 1). Here, the switch group 105_1 to 105_ (n + 1) corresponds to the second switch circuit described in the claims, and the capacitors 106_1 to 106_ (n + 1) correspond to the second L (L) described in the claims. Corresponds to 3 or more natural numbers, the same applies hereinafter) capacitive elements.
The capacitor 106_1 is a capacitor whose capacitance is set to the reference capacitance C. Further, the capacitors 106_1 to 106_ (n + 1) are each set to a capacitance (C / 2, C / 4, ..., C / 2 ⁿ ) in which the reference capacitance C is weighted by the reciprocal of the power of 2. It is a capacitor.
For example, in the case of "n = 4", the capacitances of the capacitors 106_1 to 106_5 are "C, C / 2, C / 4, C / 8, C / 16," respectively.

Each of the switch groups 105_1 to 105_ (n + 1) includes three switches, a switch 103d_k (k is a natural number of 1 to (n + 1)), a switch 103e_k, and a switch 103f_k. Hereinafter, the switch 103d_k, the switch 103e_k, and the switch 103f_k may be abbreviated as "switch 103d_k-103f_k".
Specifically, the switch group 105_1 to 105_ (n + 1) includes switches 103d_k to 103f_k having the same number at the end (1 to (n + 1)) as each switch group.
For example, the switch group 105_1 includes three switches, a switch 103d_1, a switch 103e_1, and a switch 103f_1. Further, in the case of the switch group 105_ (n + 1), the switch 103d_ (n + 1), the switch 103e_ (n + 1), and the switch 103f_ (n + 1) are provided.

Further, the switch 103d_k to 103f_k is composed of a switching element such as a MOS transistor, and has a common terminal O to which the right end of each is connected.
A terminal C is formed at the left end of the switches 103d_1 to 103d_ (n + 1), a terminal P is formed at the left end of the switches 103e_1 to 103e_ (n + 1), and a terminal N is formed at the left end of the switches 103f_1 to 103f_ (n + 1). ing.
The common terminal O of the switches 103d_k to 103f_k is connected to the left end of the capacitor 106_k.

Specifically, the common terminal O of the switches 103d_1 to 103f_1 is located at the left end of the capacitor 106_1, the common terminal O of the switches 103d_1 to 103f_2 is located at the left end of the capacitor 106_2, ..., Switches 103d_ (n + 1) to 103f_ (n + 1). The common terminal O of is connected to the left end of the capacitor 106_ (n + 1).
The terminals C of the switches 103d_1 to 103d_ (n + 1) are connected to the first reference voltage terminal VC having the first reference voltage VC. The first reference voltage VC is set to, for example, 0 [V].

Further, the terminals P of the switches 103e_1 to 103e_ (n + 1) are connected to the second reference voltage terminal VRP having the second reference voltage VRP which is the full-scale reference voltage on the positive side with respect to the first reference voltage VC. ..
Further, the terminals N of the switches 103f_1 to 103f_ (n + 1) are connected to a third reference voltage terminal VRN having a third reference voltage VRN which is a full-scale reference voltage on the negative side with respect to the first reference voltage VC. ..
That is, in the present embodiment, the range from the negative side third reference voltage VRN to the positive side second reference voltage VRP is the range of the full-scale reference voltage with the first reference voltage VC as the reference (center).

Then, the switches 103d_1 to 103d_ (n + 1) switch the on / off state according to the control signal CTRL from the control circuit 101, and short-circuit the terminal C and the terminal O in the on state. As a result, the left end of the capacitors 106_1 to 106_ (n + 1) is connected to the first reference voltage terminal VC.
Further, the switches 103e_1 to 103e_ (n + 1) switch the on / off state according to the control signal CTRL from the control circuit 101, and short-circuit the terminal P and the terminal O in the on state. As a result, the left end of the capacitors 106_1 to 106_ (n + 1) is connected to the second reference voltage terminal VRP.

Further, the switches 103f_1 to 103f_ (n + 1) switch on / off according to the control signal CTRL from the control circuit 101, and when in the on state, short-circuit the terminal N and the terminal O. As a result, the left end of the capacitors 106_1 to 106_ (n + 1) is connected to the third reference voltage terminal VRN.
The storage node SN0 includes the right end of the capacitors 106_1 to 106_ (n + 1), the non-inverting input terminal of the comparator 104, the upper end of the switch 103a, and the capacitors constituting the receiving circuit 107 (hereinafter, the receiving circuit 107 is referred to as “capacitor 107””. It is a node that can store an electric charge, which is formed at the connection point with the right end of (also called).

By the connection configuration of the various capacitors 106 and 107 and the various switches 103a to 103f described above, when the switches 103a and 103b are turned off and the switch 103c is turned on, the same function as the subtractor 108a is exhibited. Will be done. That is, in this connected state, the holding voltage of the capacitor 107 (the voltage of the analog input signal Ain) and the holding voltage of the capacitors 106_1 to 106_ (n + 1) (the output voltage of the DA converter 109) are made polar in the storage node SN0. The differential voltage SN0, which is the voltage adjusted accordingly, is held.

The switch 103a is composed of a switching element such as a MOS transistor, its upper end is connected to the storage node SN0, and its lower end is connected to the first reference voltage terminal VC having the first reference voltage VC. Then, the on / off state is switched according to the control signal CTRL from the control circuit 101, and the storage node SN0 is connected to the first reference voltage terminal VC in the on state.
The switch 103b is composed of a switching element such as a MOS transistor, the right end of which is connected to the right end of the switch 103c and the left end of the receiving circuit 107, and the left end of which is connected to the first reference voltage terminal VC. Then, the on / off state is switched according to the control signal CTRL from the control circuit 101, and when the on / off state, the left end of the receiving circuit 107 is connected to the first reference voltage terminal VC.

The switch 103c is composed of a switching element such as a MOS transistor, and the right end is connected to the right end of the switch 103b and the left end of the receiving circuit 107, and the left end is connected to the signal input terminal Ain of the analog input signal Ain. Then, on / off is switched according to the control signal CTRL from the control circuit 101, and when it is in the on state, the left end of the receiving circuit 107 is connected to the signal input terminal Ain.
The switching operation is controlled (non-overlapping control) so that the switch 103b and the switch 103c are not turned on at the same time.

On the other hand, the comparative switched capacitor circuit 118 includes switches 113a to 113c, a receiving circuit 117, a storage node SN1, and a DA converter 119.
In the first embodiment, the receiving circuit 117 is composed of a capacitor having the same capacitance as the receiving circuit 107. With this configuration, the receiving circuit 117 has a role of transmitting (adding) the analog input signal Ain input to the signal input terminal Ain to the storage node SN1 which is an input node of the comparator 114.
The DA converter 119 includes a switch group 115_1 to 115_ (n + 1) and a capacitor 116_1 to 116_ (n + 1). Here, the switch group 115_1 to 115_ (n + 1) corresponds to the second switch circuit described in the claims, and the capacitors 116_1 to 116_ (n + 1) correspond to the second to nth capacitive elements described in the claims. Correspond.
Capacitors 116_1 to 116_ (n + 1) have the same configuration as the above capacitors 106_1 to 106_ (n + 1).

Each of the switch groups 115_1 to 115_ (n + 1) includes three switches, a switch 113d_k, a switch 113e_k, and a switch 113f_k. Hereinafter, the switch 113d_k, the switch 113e_k, and the switch 113f_k may be abbreviated as "switch 113d_k to 113f_k".
The switches 113d_k to 113f_k have the same configuration as the switches 103d_k to 103f_k. That is, a terminal C is formed at the left end of the switches 113d_1 to 113d_ (n + 1), a terminal P is formed at the left end of the switches 113e_1 to 113e_ (n + 1), and a terminal N is formed at the left end of the switches 113f_1 to 113f_ (n + 1). It is formed. Then, the common terminal O of the switches 113d_k to 113f_k is connected to the left end of the capacitor 116_k, the terminal C is connected to the first reference voltage terminal VC, the terminal P is connected to the second reference voltage terminal VRP, and the terminal N is the third. It is connected to the reference voltage terminal VRN.

Then, the switches 113d_1 to 113d_ (n + 1) switch the on / off state according to the control signal CTRL from the control circuit 101, and short-circuit the terminal C and the terminal O in the on state. As a result, the left end of the capacitors 116_1 to 116_ (n + 1) is connected to the first reference voltage terminal VC.
Further, the switches 113e_1 to 113e_ (n + 1) switch the on / off state according to the control signal CTRL from the control circuit 101, and short-circuit the terminal P and the terminal O when the switch 113e_1 to 113e_ (n + 1) is in the on state. As a result, the left end of the capacitors 116_1 to 116_ (n + 1) is connected to the second reference voltage terminal VRP.

Further, the switches 113f_1 to 113f_ (n + 1) switch the on / off state according to the control signal CTRL from the control circuit 101, and short-circuit the terminal N and the terminal O when the switch 113f_1 to 113f_ (n + 1) is in the on state. As a result, the left end of the capacitors 116_1 to 116_ (n + 1) is connected to the third reference voltage terminal VRN.
The storage node SN1 includes the right end of the capacitors 116_1 to 116_ (n + 1), the non-inverting input terminal of the comparator 114, the upper end of the switch 113a, and the capacitors constituting the receiving circuit 117 (hereinafter, the receiving circuit 117 is referred to as “capacitor 117””. It is a node that can store an electric charge, which is formed at the connection point with the right end of (also called).

According to the connection configuration of the various capacitors 116 and 117 and the various switches 113a to 113f described above, when the switches 113a and 113b are turned off and the switch 113c is turned on, the same function as the subtractor 118a is exhibited. Will be done. That is, in this connected state, the holding voltage of the capacitor 117 (the voltage of the analog input signal Ain) and the holding voltage of the capacitors 116_1 to 116_ (n + 1) (the output voltage of the DA converter 119) are made polar in the storage node SN1. The differential voltage SN1, which is a voltage adjusted accordingly, is held.

The switch 113a is composed of a switching element such as a MOS transistor, its upper end is connected to the storage node SN1, and its lower end is connected to the first reference voltage terminal VC. Then, the on / off state is switched according to the control signal CTRL from the control circuit 101, and the storage node SN1 is connected to the first reference voltage terminal VC in the on state.
The switch 113b is composed of a switching element such as a MOS transistor, and the right end is connected to the right end of the switch 113c and the left end of the receiving circuit 117, respectively, and the left end is connected to the first reference voltage terminal VC. Then, the on / off state is switched according to the control signal CTRL from the control circuit 101, and when the on / off state, the left end of the receiving circuit 117 is connected to the first reference voltage terminal VC.

The switch 113c is composed of a switching element such as a MOS transistor, and the right end is connected to the right end of the switch 113b and the left end of the receiving circuit 117, and the left end is connected to the signal input terminal Ain of the analog input signal Ain. Then, the on / off state is switched according to the control signal CTRL from the control circuit 101, and the left end of the receiving circuit 117 is connected to the signal input terminal Ain in the on state.
The switch 113b and the switch 113c are non-overlapping controlled.

The control circuit 101 controls the switching operation between the switches 103a to 103c and 113a to 113c and the switch groups 105_1 to 105_ (n + 1) and 115_1 to 115_ (n + 1) based on the comparison results DO0 and DO1 of the comparators 104 and 114. It has a function of generating a control signal CTRL.
The control signal CTRL includes the control values NEG and Di generated based on the control values DA0 and DA1. Note that i is a natural number from 1 to (n + 1). Further, NEG means the polarity of the signal, and Di means the absolute value of the signal. Specifically, NEG means "Negative", and "NEG = 0" indicates positive and "NEG = 1" indicates negative. Here, the control signal CTRL corresponds to the reference value described in the claims.

The output register 102 has a function of holding signal values (DO0-1 to DO0_n and DO1-1 to DO1_n) indicating the comparison results output by the comparators 104 and 114. In addition, it has a function of generating a (n + 1) bit digital output signal Vout and outputting the generated digital output signal Vout based on the retained comparison results DO0_1 to DO0_n and DO1_1 to DO1_n.
The comparator 104 has a difference voltage SN0 input to the non-inverting input terminal and a reference voltage VC (same as the first reference voltage VC) input to the inverting input terminal according to the rising edge of the clock signal DCLK from the control circuit 101. ) And compare. Then, when “SN0 ≧ VC”, a high level signal (“DO0_M = 1”) is output as the comparison result DO0_M (M is a natural number of 1 to n). When "SN0 <VC", a low-level signal ("DO0_M = 0") is output as the comparison result DO0_M.

The comparator 114 compares the differential voltage SN1 input to the non-inverting input terminal with the reference voltage VC input to the inverting input terminal according to the rising edge of the clock signal DCLK from the control circuit 101. Then, when “SN1 ≧ VC”, a high level signal (“DO1_M = 1”) is output as the comparison result DO1_M. Further, when "SN1 <VC", a low level signal ("DO1_M = 0") is output as the comparison result DO1_M.

[Outline of operation of successive approximation type AD converter 1]
Next, an outline of the operation of the successive approximation type AD converter 1 according to the first embodiment will be described.
The sequential comparison type AD converter 1 according to the first embodiment can obtain the digital output signal Vout which is the AD conversion result of the analog input signal Ain by performing the operations shown in the following (1) to (6). Is.

(1) The control circuit 101 turns on the switches 103a, 103b, 103d_1 to 103d_ (n + 1), and initializes the charges of the capacitors 106_1 to 106_ (n + 1). Similarly, the switches 113a, 113b, 113d_1 to 113d_ (n + 1) are turned on to initialize the charges of the capacitors 116_1 to 116_ (n + 1).

(2) The control circuit 101 turns off the switches 103a and 103b, turns on the switch 103c, and sends the analog input signal Ain input to the signal input terminal Ain to the input terminal of the comparator 104 via the receiving circuit 107. To be transmitted. At the same time, one of the switches inside the switch group 105_1 to 105_ (n + 1) is turned on so that the output voltage of the DA converter 109 becomes a desired comparison voltage (described later).
Similarly, the control circuit 101 turns off the switches 113a and 113b, turns on the switch 113c, and sends the analog input signal Ain input to the signal input terminal Ain to the input terminal of the comparator 114 via the receiving circuit 117. To be transmitted. At the same time, any switch inside the switch group 115_1 to 115_ (n + 1) is turned on so that the output voltage of the DA converter 119 becomes a desired comparison voltage (described later).

Here, the comparison voltage is a voltage for comparing the height of the analog input signal Ain with the signal voltage. The control circuit 101 updates the next comparison voltage to a higher voltage when the signal voltage of the analog input signal Ain is higher than the comparison voltage, and when the signal voltage of the analog input signal Ain is lower than the comparison voltage, the control circuit 101 updates the next comparison voltage to a higher voltage. Update the next comparison voltage to a lower voltage. Further, since the desired comparison voltages output from the DA converters 109 and 119 are different from each other, the switches at different positions are turned on.

(3) The comparator 104 compares the differential voltage SN0 held in the storage node SN0 with the reference voltage VC, and obtains a comparison result DO0_1. Similarly, the comparator 114 compares the differential voltage SN1 held in the storage node SN1 with the reference voltage VC, and obtains a comparison result DO1_1. Here, in the first embodiment, the analog input signal Ain is compared with the difference voltage SN0 and SN1 between the voltage of the analog input signal Ain and the comparison voltage and the reference voltage VC with the comparators 104 and 114. It is configured to compare the height of the voltage of the above and the comparison voltage.

(4) At the output register 102, a digital output code VO (M) is obtained based on the comparison results DO0_M and DO1_M of the comparators 104 and 114. For example, in the case of the first comparison operation, VO (1), which is the first digital output code, can be obtained based on the comparison results DO0_1 and DO1_1.

(5) The control circuit 101 updates the control values DA0 and DA1 to change the comparison voltage, and repeats the same processes from (2) to (4) above (n-1) times. As a result, VO (n) is obtained from the digital output code VO (2).

(6) In the output register 102, the digital output signal Vout, which is the AD conversion result of the analog input signal Ain, is calculated based on the values of the digital output codes VO (1) to VO (n). Then, the calculated digital output signal Vout is output. In the successive approximation type AD converter 1 according to the first embodiment, it is possible to obtain an AD conversion result of (n + 1) bits by n comparison operations.

[About the differential voltage SN0 of the storage node SN0]
During the processing from (2) to (4) above, the differential voltage SN0 changes depending on the on / off state of each switch of the switch group 105_1 to 105_ (n + 1). Further, this differential voltage SN0 can be expressed by the following equation (1), ignoring the influence of parasitic capacitance.

Here, in the above equation (1), Ctotal is the sum of the capacitance values of all the capacitors including the capacitor 107 and the capacitors 106_1 to 106_ (n + 1), and can be expressed by the following equation (2).

In the above equation (2), Ci is the capacitance value of the capacitor 106_i.
The control values NEG and Di and the switches 103d_i to 103f_i of the switch group 105_i to be turned on have the relationships shown in Table 1 below.

That is, as shown in Table 1 above, NEG and Di are set to "0 or 1" at the time of initialization, and the switch to be turned on is 103d_i. The voltage of the terminal O at this time is the first reference voltage VC. Further, in the comparison operation, when NEG is "0" and Di is "1", the switch to be turned on is 103f_i. The voltage of the terminal O at this time becomes the third reference voltage VRN. Further, in the comparison operation, when NEG is "0 or 1" and Di is "0", the switch to be turned on is 103d_i. The voltage of the terminal O at this time is the first reference voltage VC. Further, in the comparison operation, when NEG is "1" and Di is "1", the switch to be turned on is 103e_i. The voltage of the terminal O at this time becomes the second reference voltage VRP.
Further, assuming that the control value DA0 is the following equation (3), the above equations (1) and (2) can be expressed as the following equations (4) and (5).

The first term of the above equation (4) is proportional to the analog input signal Ain. Further, the second term of the above equation (4) is from − ((C / 2 ⁿ ) / Ctotal) · ((VRP-VRN) / 2) to + ((C / 2 ⁿ )).
It is an arbitrary voltage value within the range of / Ctotal) and ((VRP-VRN) / 2).
Here, FIG. 3 is a diagram showing the correspondence between the control values NEG, D1, D2, D3, D4, D5, DA0 and the value of the second term of the above equation (4) when "n = 4". is there. Further, FIG. 4 is a block diagram showing a comparative switched capacitor circuit in blocks for each function.

As shown in FIG. 3, for example, when "NEG = 0, D1 = D2 = D3 = D4 = D5 = 1, DA0 = 31", the second term of the above equation (4) is "(31/32).・ (C / Ctotal) ・ (VRP-VRN) ”. On the other hand, for example, when "NEG = 1, D1 = D2 = D3 = D4 = D5 = 1, DA0 = -31", the second term of the above equation (4) is "-(31/32) · (C). / Ctotal) ・ (VRP-VRN) ”.

That is, as shown in FIG. 4, the comparison switched capacitor circuit 108 is a circuit that outputs a voltage (difference voltage SN0) obtained by adding or subtracting the comparison voltage corresponding to the value of the control value DA0 from the analog input signal Ain to the storage node SN0. It can be said that. Since the control value DA0 is a digital value, the comparison switched capacitor circuit 108 generates an analog comparison signal by DA-converting the digital control value DA0 to an analog value, and converts this analog comparison signal into an analog input signal Ain. It can be rephrased as a circuit that outputs by adding or subtracting. Here, the analog comparison signal corresponds to the analog reference signal described in the claims.
Since the comparative switched capacitor circuit 118 has the same configuration as the comparative switched capacitor circuit 108, the description of the differential voltage SN1 of the storage node SN1 will be omitted.

[How to set the comparison voltage during comparison operation]
Here, FIG. 5 is a diagram showing an example of the relationship between the analog input signal Ain and the digital output signal Vout of the successive approximation type AD converter of the first embodiment. In FIG. 5, the horizontal axis is the signal voltage of the analog input signal Ain (hereinafter, referred to as “analog input voltage”), and the vertical axis is the digital output signal Vout.
As shown in FIG. 5, the method of setting the comparison voltage during the comparison operation is described by taking as an example the case where the sequential comparison type AD converter 1 having the first reference voltage VC as the center and ± VFS as the input range is configured. explain.

In the first embodiment, in order to obtain the (n + 1) bit digital output signal Vout, the comparators 104 and 114 perform n comparison operations, respectively. Hereinafter, the voltage output from the DA converter 109 is referred to as a "first comparison voltage", and the voltage output from the DA converter 119 is referred to as a "second comparison voltage".
In the first comparison, the control value DA0 is set so that the first comparison voltage is "VC + VFS / 4", and the control value DA1 is set so that the second comparison voltage is "VC-VFS / 4". .. For example, in the case of "n = 4", "DA0 = 8" and "DA1 = -8" are set.

The interval between the first comparison voltage and the second comparison voltage at this time is "(VC + VFS / 4)-(VC-VFS / 4) = VFS / 2".
Here, the comparison result DO0_1 between the analog input signal Ain and the first comparison voltage and the comparison result DO1_1 between the analog input signal Ain and the second comparison voltage are as shown in Table 2 below depending on the value of the analog input signal Ain. Become. Further, the digital output code at this point is defined as VO (1) and is defined as shown in Table 2 below according to the values of DO0_1 and DO1-1.

As shown in Table 2 above, when "Ain <(VC-VFS / 4)", both DO0_1 and DO1_1 are "0", and VO (1) at this time is defined as "-1". When "VC-VFS / 4 ≦ Ain <VC + VFS / 4", DO0_1 becomes "0" and DO1_1 becomes "1", and VO (1) at this time is defined as "0". When "Ain ≧ (VC + VFS / 4)", both DO0_1 and DO1_1 are set to "1", and VO (1) at this time is defined as "1".

Next, in the second comparison, the interval between the first and second comparison voltages is set to half the interval of the first comparison, and a finer judgment is made. Specifically, the first and second comparison voltages of the second time are set as follows according to the result of the first comparison.
If the result of the first comparison is "Ain <(VC-VFS / 4)", DA0 is set so that the first comparison voltage is "VC-VFS x 3/8" in the second comparison. DA1 is set so that the second comparison voltage is "VC-VFS x 5/8". For example, in the case of "n = 4", "DA0 = -12" and "DA1 = -20" are set.

If the first comparison result is "VC-VFS / 4 ≤ Ain <VC + VFS / 4", DA0 is set so that the first comparison voltage is "VC + VFS / 8" in the second comparison. DA1 is set so that the second comparison voltage is "VC-VFS / 8". For example, in the case of "n = 4", "DA0 = 4" and "DA1 = -4" are set.
If the result of the first comparison is "Ain ≥ (VC + VFS / 4)", DA0 is set so that the first comparison voltage is "VC + VFS x 5/8" in the second comparison, and the second comparison is performed. DA1 is set so that the comparison voltage is "VC + VFS x 3/8". For example, in the case of "n = 4", "DA0 = 20" and "DA1 = 12" are set.

The digital output code obtained from the second comparison result is defined as VO (2), and its value is defined in the same manner as in the first comparison (see Table 2 above).
Similarly, the interval between DA0 and DA1 is set to half of the previous time, and a finer judgment is made. In order to obtain the AD conversion result of (n + 1) bits, this comparison operation is repeated n times to obtain VO (n) from VO (1).
The final AD conversion result is obtained by the following equation (6).
Vout = VO (1) · (2 ^n-1 ) + VO (2) · (2 ^n-2 ) + ... + VO (n)
... (6)

Up to the second of the above comparison operations is shown in FIG. Here, FIG. 6 is a diagram showing an example of the relationship between the comparison voltage and the number of comparison operations during the comparison operation of the successive approximation type AD converter according to the first embodiment. In FIG. 6, the position of the first comparison voltage is indicated by a black triangle mark, and the position of the second comparison voltage is indicated by a white triangle mark. The distance between the two triangle marks is the minimum resolution at the time of comparison, and vertical arrow lines are drawn above and below the first and second comparison voltages so as to have a width corresponding to the minimum resolution. The range of this arrow line corresponds to the analog voltage range that can be determined at that time. Hereinafter, this voltage range is referred to as a "comparison range". Further, in this comparison range, the section between the maximum voltage and the first comparison voltage, the section between the first comparison voltage and the second comparison voltage, and the section between the second comparison voltage and the minimum voltage are respectively. Corresponds to the "judgment section" described in the scope of patent claims. Taking the first comparison operation as an example, the comparison range is the section between the maximum voltage "VC + VFS x 3/4" and the first comparison voltage "VC + VFS x 1/4" and the first comparison voltage "VC + VFS x". The section between "1/4" and the second comparison voltage "VC-VFS x 1/4", the second comparison voltage "VC-VFS x 1/4" and the minimum voltage "VC-VFS x 3/4" It has three determination sections with the section between and.

As shown in FIG. 6, it can be seen that the comparison range is halved in the second comparison operation as compared with the first comparison operation. Although three comparison ranges are shown in FIG. 6 as the comparison range of the second comparison operation, in reality, any one of the comparison ranges is set according to the result of the first comparison.

[Mechanism for responding to changes in analog input signal Ain during comparison operation]
Here, FIG. 7 is a diagram showing an example of the relationship between the comparison voltage and the analog input voltage when the analog input voltage of the sequential comparison type AD converter according to the first embodiment changes.
In the sequential comparison type AD converter 1 according to the first embodiment, when the analog input signal Ain changes during the comparison operation, the difference voltages SN0 and SN1 also change accordingly, so that an error occurs in the AD conversion result. There is. On the other hand, in the first embodiment, by setting the first comparison voltage and the second comparison voltage by the method of setting the comparison voltage described above, it is possible to reduce the occurrence of an error in the AD conversion result. The mechanism will be described below.

Assuming that the analog input voltage at the time of the first comparison is Ain (1) and the analog input voltage at the time of the second comparison is Ain (2), the digital output code obtained by the two comparisons is as shown in FIG. The first time is "VO (1) = 1" and the second time is "VO (2) = -1".
Here, when the final output Vout is calculated according to the above equation (6) at the time of the second comparison, it becomes “Vout = 1 × 2-1 = 1”.
On the other hand, if the analog input voltage at the time of the first comparison changes to Ain (2) at the time of the second comparison with Ain (1)'in FIG. 7, the digital output code obtained by the second comparison is the first. Is "VO (1) = 0", and the second time is "VO (2) = 1". That is, a result different from that when the first time is Ain (1) is obtained.

However, in this case as well, when the final output Vout is calculated according to the above equation (6) at the time of the second comparison, it becomes "Vout = 0 × 2 + 1 = 1", and the same result as when the first time is Ain (1) is obtained. can get.
This means that even if the analog input voltage in the first comparison is different, if the second input voltage is the same, the overall AD conversion result will be the result according to the input voltage at the second time. Shown.
That is, in the present invention, as shown in FIG. 7, the second comparison range when the analog input voltage is Ain (1) and the second comparison range when the analog input voltage is Ain (1)'partially overlap. The comparison range is set as follows. Therefore, when Ain (2) falls within this overlapping range, the final output Vout has the same result even if the first comparison result has a different value. More specifically, for example, in the first judgment section (the section between the maximum voltage "VC + VFS x 3/4" and the first comparison voltage "VC + VFS x 1/4") of the first three judgment sections. The comparison range at the time of the second judgment (the range between the maximum voltage "VC + VFS x 7/8" and the minimum voltage "VC + VFS x 1/8") set based on the judgment result is adjacent to the first judgment section. Comparison range at the time of the second judgment set based on the judgment result in the second judgment section (section between the first comparison voltage and the second comparison voltage) (maximum voltage "VC + VFS x 3/8" and minimum voltage " The voltage range overlaps between (the range between VC-VFS x 3/8) and at least a part of the range (the range between the voltage "VC + VFS x 3/8" and the voltage "VC + VFS 1/8").

The sequential comparison type AD converter 1 according to the first embodiment constitutes a circuit that performs n comparisons in order to obtain an AD conversion result of (n + 1) bits by utilizing this characteristic. Therefore, in the nth comparison operation, an AD conversion result corresponding to the analog input voltage at the time of the nth comparison can be obtained, and there is no problem even if the analog voltage at the time of comparison before that is slightly different.
On the other hand, as a comparison explanation, a comparison operation when the analog input voltage changes in the sequential comparison type A / D converter of the related technology will be described.
Here, FIG. 8 is a diagram showing an example of the relationship between the comparison voltage and the number of comparison operations during the comparison operation of the successive approximation type A / D converter of the related technology. Further, FIG. 9 is a diagram showing an example of the relationship between the comparison voltage and the analog input voltage when the analog input voltage of the sequential comparison type A / D converter of the related technology changes. In addition, in FIG. 8 and FIG. 9, the position of the comparison voltage is indicated by a white triangular mark. The comparison range is indicated by an arrow line in the vertical direction.

As shown in FIG. 8, the sequential comparison type A / D converter of the related technology has a configuration in which there is no overlapping range portion between the comparison ranges used for the second and subsequent comparison operations.
Therefore, in the conventional comparison operation shown in FIG. 8, when the analog input signal changes during the comparison operation, the operation is as shown in FIG.
That is, when the analog input voltage at the time of the first comparison changes from Ain (1) in FIG. 9 to Ain (2) in the same figure at the time of the second comparison, the digital output code obtained by the two comparisons is The first time is "VO (1) = 1" and the second time is "VO (2) = 0". Therefore, the final output Vout at the second time is "Vout = 1 × 2 + 0 = 2".

On the other hand, if the first analog input voltage is Ain (1)'in FIG. 9 and changes to Ain (2) in the same figure at the time of the second comparison, the digital output code obtained in the two comparisons is 1. The second time is "VO (1) = 0", and the second time is "VO (2) = 1". Therefore, the final output Vout at the second time is "Vout = 0 × 2 + 1 = 1".
That is, if the analog input voltage during the first and second comparison operations is different, the final output Vout will also be different, and the operation as an A / D converter cannot be performed. Therefore, in the sequential comparison type A / D converter of the related technology, the analog input voltage is temporarily sample-held before the comparison operation is started, and the comparison operation is performed based on the held voltage. That is, there is a delay corresponding to the comparison operation from the time of sampling until the digital output signal is output through the comparison operation.

On the other hand, the sequential comparison type AD converter 1 according to the first embodiment can immediately output the AD conversion result corresponding to the analog input voltage at the time of final comparison while following the change of the analog input signal Ain. Is. As a result, there is no conversion delay due to sample hold as in the successive approximation type A / D converter of the related technology.

[Operation example]
Next, an operation example of the successive approximation type AD converter 1 according to the first embodiment will be described with reference to FIG. 10A. Here, FIG. 10A shows an analog input signal waveform, a comparison voltage, and a clock signal waveform at the time of comparison operation when the sequential comparison type AD converter according to the first embodiment is configured to obtain a 5-bit output. , The comparison result and an example of the time change of the digital output code.
Hereinafter, the operation of the 5-bit successive approximation type AD converter 1 will be described with “n = 4”. The operation after the switches 103a, 103c, 113a and 113c are in the off state and the switches 103b and 113b are in the on state will be described.

The control circuit 101 first sets the control values DA0 and DA1 to "DA0 = 8" and "DA1 = -8" so that the first and second comparison voltages are "VC + VFS / 4" and "VC-VFS / 4". (See Fig. 3). Then, the control signal CTRL based on the control values DA0 and DA1 is supplied to the DA converters 109 and 119. In this case, the control values for the DA converter 109 are "0" for NEG, D1, D3, D4, and D5, "1" for D2, and the control values for the DA converter 119 are "1" for NEG and D2. , D1, D3, D4, D5 become "0".

Therefore, in the DA converter 109, the switches 103d_1, 103d_3, 103d_4, 103d_5 and 103f_2 are turned on, and in the DA converter 119, the switches 113d_1, 113d_3, 113d_4, 113d_5 and 113e_2 are turned on.
As a result, the storage node SN0 holds the differential voltage SN0 obtained by subtracting the first comparison voltage “VC + VFS / 4” by the DA converter 109 from the analog input voltage Ain, and the storage node SN1 holds the analog input voltage Ain to DA. The difference voltage SN1 obtained by subtracting the second comparison voltage “VC-VFS / 4” by the converter 119 is held.

Then, the differential voltage SN0 of the storage node SN0 and the reference voltage VC are compared and determined in the comparator 104 according to the rising edge of the clock signal DCLK. At the same time, the difference voltage SN1 of the storage node SN1 and the reference voltage VC are compared and determined in the comparator 114 according to the rising edge of the clock signal DCLK.
As shown in FIG. 10A, since both the first comparison voltage and the second comparison voltage are smaller than the analog input voltage Ain, the comparison results “DO0_1 = 1” and “DO1-1 = 1” are the control circuit 101 and Each is output to the output register 102 (see Table 2 above).
As a result, in the output register 102, "1" is set as the digital output code VO (1) from the comparison result of "DO0_1 = 1" and "DO1-1 = 1" (see Table 2 above).

Further, in the control circuit 101, the control value DA0 is set so that the first comparison voltage is "VC + VFS x 5/8" from the comparison result of "DO0_1 = 1" and "DO1-1 = 1", and the second comparison voltage is set. The control value DA1 is set so that is "VC + VFS x 3/8". Specifically, the control values DA0 and DA1 are set to "DA0 = 20" and "DA1 = 12" (see FIG. 3). Then, the control signal CTRL based on the control values DA0 and DA1 is supplied to the DA converters 109 and 119. In this case, the control values for the DA converter 109 are "0" for NEG and D2, D4 and D5, and "1" for D1 and D3, and the control values for the DA converter 119 are NEG and D1, D4 and D5. It becomes "0", and D2 and D3 become "1".

Therefore, in the DA converter 109, the switches 103d_2, 103d_4, 103d_5, 103f_1 and 103f_3 are turned on, and in the DA converter 119, the switches 113d_1, 113d_4, 113d_5, 113e_2 and 113e_3 are turned on.
As a result, the storage node SN0 holds the differential voltage SN0 obtained by subtracting the first comparison voltage “VC + VFS × 5/8” by the DA converter 109 from the analog input voltage Ain, and the storage node SN1 holds the analog input voltage Ain. The differential voltage SN1 obtained by subtracting the second comparison voltage “VC + VFS × 3/8” from the DA converter 119 is held.

Then, the differential voltage SN0 and the reference voltage VC are compared and determined in the comparator 104, and the differential voltage SN1 and the reference voltage VC are compared and determined in the comparator 114 according to the rising edge of the clock signal DCLK. As shown in FIG. 10A, since the analog input voltage Ain is smaller than the first comparison voltage and larger than the second comparison voltage, the comparison results “DO0_2 = 0” and “DO1-2 = 1” are the control circuit 101. And output to the output register 102, respectively.
As a result, in the output register 102, "0" is set as the digital output code VO (2) from the comparison result of "DO0_2 = 0" and "DO1-2 = 1".

After that, in the same manner as described above, the control values DA0 and DA1 are set based on the previous comparison result so that the interval between the first comparison voltage and the second comparison voltage is halved from the previous time, and the comparison determination process is performed. carry out.
As shown in FIG. 10A, "DO0_3 = 1" and "DO1_3 = 1" are obtained in the third comparison determination, and "1" is set as the digital output code VO (3) in the output register 102. Will be done. Finally, in the fourth comparison determination, "DO0_4 = 0" and "DO1_4 = 1" are obtained.
Then, from the digital output codes VO (1) to VO (4), the output register 102 sets the final output Vout according to the above equation (6) as “Vout = 1 × 2 ³ + 0 × 2 ² +1 × 2 ^1”.
+0 = 10 ”is calculated.
This final output Vout is the AD conversion result of the analog input signal Ain at the time of final comparison.

On the other hand, FIG. 10B shows an analog input signal waveform, a comparison voltage, and a clock signal waveform at the time of comparison operation when the sequential comparison type AD converter according to the first embodiment is configured to obtain a 6-bit output. It is a figure which shows the comparison result and an example of time change of a digital output code.
The content shown in FIG. 10B is adapted to the 6-bit output sequential comparison type A / D converter of the related technology shown in FIG. 21. The basic operation content is the same as that of the 5-bit sequential comparison type AD converter 1 described above.

In the 6-bit output sequential comparison type AD converter 1 according to the first embodiment, as shown in FIG. 10B, in the first comparison determination, "DO0_1 = DO1-1 = 1", "VO (1) =""1" is obtained, and "DO0_2 = 0", "DO1-2 = 1", and "VO (2) = 0" are obtained in the second comparison determination. In addition, "DO0_3 = DO1_3 = 1" and "VO (3) = 1" were obtained in the third comparison judgment, and "DO0_4 = 0", "DO1_4 = 1" and "DO1_4 = 1" were obtained in the fourth comparison judgment. VO (4) = 0 ”is obtained. Then, in the final fifth comparison determination, "DO0_5 = 1", "DO1_5 = 1", and "VO (5) = 1" are obtained.
As a result, as the final output Vout, "Vout = 1 × 2 ⁴ + 0 × 2 ³ + 1 × 2 ² + 0 × 2 ¹ + 1 = 21" is obtained according to the above equation (6).

On the other hand, in the 6-bit successive approximation type A / D converter of the related technology shown in FIG. 21, as the comparison result by the comparison operation of 6 times, "D1 = 1", "D2 = 1", "D3 = 0", “D4 = 1”, “D5 = 0”, and “D6 = 1” are obtained. That is, "010101" is obtained in binary notation. Note that "1" is inverted to "0" only in the most significant bit (D1) because of the two's complement representation.
Therefore, as the final output Vout, "Vout = 0 × 2 ⁵ + 1 × 2 ⁴ + 0 × 2 ³ + 1 × 2 ² + 0 × 2 ¹ + 1 = 21" is obtained.
In the example shown in FIG. 10B, the analog input voltage Ain at the time of final comparison is equal to the analog input voltage Ain at the time of the sample of the conventional configuration shown in FIG. 21, so that the final outputs of both are the same. ..

[Action and effect of the first embodiment]
In the sequential comparison type AD converter 1 according to the first embodiment, the receiving circuits 107 and 117 receive the analog input signal Ain and output the analog input signal AinO corresponding to the analog input signal Ain. The subtractors 108a and 118a use a difference signal (difference voltage) between the analog input signal AinO in each of the n successive conversions and the analog comparison signal (first and second comparison voltage) obtained by DA-converting the control values DA0 and DA1. SN0 and SN1) are calculated. The comparators 104 and 114 determine whether the voltages of the differential voltages SN0 and SN1 are higher than the reference voltage VC. The control circuit 101 calculates the digital output signal Vout corresponding to the analog input signal AinO based on the comparison results DO0 and DO1 of the comparators 104 and 114. Further, the control circuit 101 sets the control values DA0 and so that the analog comparison signals (first and second comparison voltages) approach the analog input signals AinO based on the comparison results DO0 and DO1 of the comparators 104 and 114 each time. Update DA1. The DA converters 109 and 119 convert the control values DA0 and DA1 into analog comparison signals (first and second comparison voltages). The output register 102 outputs a digital output signal based on the comparison results DO0 and DO1 of the comparators 104 and 114.

That is, the sequential comparison type AD converter 1 has the receiving circuits 107 and 117 of the first to mth (m = 2 in the present embodiment) and the first to mth (m = 2 in the present embodiment). The comparators 104 and 114, the first to m (m = 2 in this embodiment) DA converters 109 and 119, and the first to m (m = 2 in this embodiment) subtractors 108a. And 118a. The control circuit 101 updates the control values DA0 and DA1 corresponding to the DA converters 109 and 119, respectively, based on the comparison results DO0 and DO1 at the timing of sequential conversion of the comparators 104 and 114, and the output register 102 compares. The digital output signal Vout is calculated based on the comparison results DO0 and DO1 of the instruments 104 and 114.

Further, the sequential comparison type AD converter 1 according to the first embodiment includes a switch 103c to which an analog input signal Ain is input. In addition, the successive approximation type AD converter 1 has a first reference voltage terminal VC having a first reference voltage VC and a second reference voltage terminal having a second reference voltage VRP on the positive side with respect to the first reference voltage VC. It includes a VRP and a third reference voltage terminal VRN having a third reference voltage VRN on the negative side with respect to the first reference voltage VC. In addition, the receiving circuit 107 has a capacitor with a capacitance of Cin.

Further, in the sequential comparison type AD converter 1 according to the first embodiment, the DA converter 109 responds to the capacitors 106_1 to 106_ (n + 1) whose ends are connected to the storage node SN0 and the digital signal of the control value DA0. It has a switch group 105_1 to 105_ (n + 1) that connects the other ends of the capacitors 106_1 to 106_ (n + 1) to the first reference voltage terminal VC, the second reference voltage terminal VRP, or the third reference voltage terminal VRN. Further, the DA converter 119 first sets the other ends of the capacitors 116_1 to 116_ (n + 1), one end of which is connected to the storage node SN1, and the other ends of the capacitors 116_1 to 116_ (n + 1) according to the digital signal of the control value DA1. It has a reference voltage terminal VC, a second reference voltage terminal VRP, or a group of switches 115_1 to 115_ (n + 1) connected to the third reference voltage terminal VRN. Further, among the capacitors 106_1 to 106_ (n + 1) and 116_1 to 116_ (n + 1), the capacitance values of the capacitors 106_K and 116_K (K is a natural number of 1 ≦ K ≦ (n + 1)) are the capacitors 106_ (n + 1) and 116_ (n + 1). ) Is multiplied by 2 ((n + 1) -k) to obtain a value.

With this configuration, when the analog input signal Ain is received by the receiving circuits 107 and 117, the analog input signal AinO corresponding to the received analog input signal Ain can be output to the storage nodes SN0 and SN1. That is, the signal corresponding to the input signal is directly output to the storage nodes SN0 and SN1 without sample-holding the input signal. As a result, the comparators 104 and 114 can perform comparison processing on the analog input signal AinO that changes in real time. As a result, it is possible to eliminate the delay due to the sample hold as compared with the conventional case, and it is possible to improve the conversion speed.

Further, in the sequential comparison type AD converter 1 according to the first embodiment, the control circuit 101 further determines a plurality of analog input signals AinO based on the comparison results DO0 and DO1 of the DA converters 109 and 119. A comparison range having a judgment interval of is set. The control circuit 101 was set based on the comparison results DO0_j and DO1_j in the first determination section of the plurality of determination sections of the comparators 104 and 114 jth time (j is a natural number of 1 ≦ j ≦ n, the same applies hereinafter). (J + 1) The comparison range at the time of the first judgment is set based on the comparison results DO0 and DO1 in the second judgment section adjacent to the first judgment section, which is one of the judgment sections of the jth plurality of judgment sections. The control values DA0 and DA1 corresponding to the DA converters 109 and 119 are updated so that at least a part of the comparison range at the time of the (j + 1) th determination overlaps.

Specifically, the control circuit 101 sets the DA converters 109 and 119 so that the width of the comparison range at the time of the (j + 1) th determination is half the width of the comparison range at the time of the jth determination, respectively. The corresponding control values DA0 and DA1 are updated.

With this configuration, the comparison range of the analog input signal AinO in the j-th comparison operation of the comparators 104 and 114 and the comparison range of the analog input signal AinO in the (j + 1) th comparison judgment operation are partially divided. It is possible to set the comparison range so that they overlap. As a result, when the analog input signal AinO at the time of the (j + 1) th comparison operation falls within this overlapping range, the final output Vout can be the same even if the comparison results before the jth th are slightly different values. It will be possible. As a result, it is possible to reduce the occurrence of an error in the AD conversion result when the analog input voltage AinO changes.

[Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to FIGS. 11 and 12.
Here, FIG. 11 is a diagram showing a basic configuration of a single-ended sequential comparison AD converter according to the second embodiment, and FIG. 12 is a diagram showing a single-ended sequential comparison AD converter according to the second embodiment. It is a figure which shows the specific structure of a converter.

[Constitution]
In the first embodiment, two sets of a switched capacitor circuit for comparison and a comparator are provided, and these two sets perform a comparison operation in parallel. In the second embodiment, a set of a switched capacitor circuit for comparison and a comparator is set as one set, and the comparison operation performed in parallel in the first embodiment is time-divisioned into one set. Different from the form.
Hereinafter, the same components as those in the first embodiment will be designated by the same reference numerals, description thereof will be omitted as appropriate, and different points will be described in detail.

As shown in FIGS. 11 and 12, the sequential comparison type AD converter 1B according to the second embodiment is the comparison switched capacitor circuit 118 and the comparator in the sequential comparison type AD converter 1 of the first embodiment. The configuration excludes 114.
The control circuit 101 of the second embodiment first calculates the control value DA0, and supplies the control signal CTRL based on the calculated control value DA0 to the comparative switched capacitor circuit 108. As a result, the DA converter 109 generates a first comparison voltage obtained by DA-converting the control value DA0, and outputs the generated first comparison voltage to the storage node SN. Here, the calculation (setting) method of the control value DA0 is the same as that of the first embodiment.

The comparator 104 of the second embodiment is a differential voltage SN between the analog input voltage Ain output from the receiving circuit 107 to the storage node SN and the first comparison voltage output from the DA converter 109 to the storage node SN (the above-mentioned first). 1) The difference voltage SN0 of the embodiment) is compared with the reference voltage VC. Then, the comparison result DO (corresponding to DO0 of the first embodiment) is output to the control circuit 101 and the output register 102.
The control circuit 101 and the output register 102 of the second embodiment hold the comparison result DO input from the comparator 104. Hereinafter, the result of the first comparison in each comparison operation is referred to as "DO0".

Subsequently, the control circuit 101 calculates the control value DA1 and supplies the control signal CTRL based on the calculated control value DA1 to the comparative switched capacitor circuit 108. As a result, the DA converter 109 generates a second comparison voltage obtained by DA-converting the control value DA1 and outputs the generated second comparison voltage to the storage node SN. Here, the calculation (setting) method of the control value DA1 is the same as that of the first embodiment.
The comparator 104 is a differential voltage SN between the analog input voltage Ain output from the receiving circuit 107 to the storage node SN and the second comparative voltage output from the DA converter 109 to the storage node SN (difference in the first embodiment). The voltage SN1) is compared with the reference voltage VC. Then, the comparison result DO (corresponding to DO1 of the first embodiment) is output to the control circuit 101 and the output register 102. Hereinafter, the second comparison result DO in each comparison operation is referred to as "DO1".

The control circuit 101 of the second embodiment updates the control values DA0 and DA1 in the same manner as in the first embodiment based on the comparison results DO0 and DO1 sequentially input from the comparator 104.
Further, the output register 102 of the second embodiment calculates the digital output code VO by the same method as that of the first embodiment based on the comparison results DO0 and DO1 input from the comparator 104.

[Action and effect of the second embodiment]
The sequential comparison type AD converter 1B according to the second embodiment has a configuration in which the comparative switched capacitor circuit 118 and the comparator 114 are excluded from the sequential comparison type AD converter 1 of the first embodiment. Then, one set of the comparative switched capacitor circuit 108 and the comparator 104 is configured to perform each comparison operation performed in parallel in the first embodiment by dividing it into two time divisions.
With this configuration, the conversion operation becomes longer as compared with the first embodiment, but it is possible to eliminate the conversion delay due to the sample hold while suppressing the conversion error, and the conversion speed is improved as compared with the conventional case. It becomes possible. Further, the circuit scale can be reduced as compared with the successive approximation type AD converter 1 of the first embodiment.

[Third Embodiment]
Next, a third embodiment of the present invention will be described with reference to FIG.
Here, FIG. 13 is a diagram showing a specific configuration of the successive approximation type AD converter of the third embodiment.

[Constitution]
In the first embodiment, the DA converters 109 and 119 are configured to generate a comparative voltage by a plurality of capacitors. The third embodiment is different from the first embodiment in that the DA converter generates a comparative voltage by a plurality of resistors (resistor ladders) instead of the plurality of capacitors.
Hereinafter, the same components as those in the first embodiment will be designated by the same reference numerals, description thereof will be omitted as appropriate, and different points will be described in detail.

As shown in FIG. 13, the sequential comparison type AD converter 2 according to the third embodiment includes a control circuit 201, an output register 202, a comparator 204 and 214, and a comparison resistor ladder type DA conversion circuit 208 and 218. And.
The comparative resistor ladder type DA conversion circuit 208 includes switches 203a, 203b and 203c, a reception circuit 207, a storage node SN0, and a DA converter 209. Here, the switch 203c corresponds to the first switch circuit described in the claims.
The receiving circuit 207 has a capacitor whose capacitance is set to the capacitance value Cin, similarly to the receiving circuit 107 of the first embodiment.

The DA converter 209 includes a switch group 205 having a plurality of switches, a capacitor 206, and a resistance ladder 210 having a plurality of resistance elements connected in series. Here, the switch group 205 corresponds to the second switch circuit described in the claims, and the capacitor 206 corresponds to the second capacitance element described in the claims.
The capacitor 206 is a capacitor whose capacitance is set to the capacitance value C, and its right end is connected to a connection point between the storage node SN0, the right end of the receiving circuit 207, and the upper end of the switch 203a.

The switch group 205 includes a plurality of switches, and as shown in FIG. 13, the left end of the top switch in the figure is connected to the first reference voltage terminal VC. Further, the left end of each of the remaining switches corresponds to one of a plurality of terminals (hereinafter referred to as “resistor connection terminals”) formed at each connection portion between the elements of the plurality of resistance elements constituting the resistance ladder 210. Each is connected to one. The right end of each switch of the plurality of switches of the switch group 205 is connected to the right end of the other switch and the left end of the capacitor 206.
Of the plurality of resistance elements connected in series of the resistance ladder 210, the upper end of the top resistance element in FIG. 13 is connected to the second reference voltage terminal VRP, and the lower end of the bottom resistance element in FIG. 13 is It is connected to the third reference voltage terminal VRN.

In the third embodiment, the plurality of resistance elements of the resistance ladder 210 are all composed of elements having the same resistance value R, and the plurality of switches 203a to 203c and the switch group 205 are switching such as MOS transistors. It is composed of elements.
Further, the plurality of switches of the switch group 205 include a common terminal O to which the right end of each is connected, and a terminal C is formed at the left end of the top switch. Further, a terminal P is formed at the left end of each switch corresponding to the potentials from the second from the top to the first reference voltage VC, and at the left end of each switch corresponding to the potentials up to the third reference voltage VRN thereafter. The terminal N is formed.

The plurality of switches of the switch group 205 switch the on / off state according to the control signal CTRL from the control circuit 201, and either terminal C and terminal O, terminal P and terminal O, and terminal N and terminal O. Short one or more. As a result, the left end of the capacitor 206 is connected to either the first reference voltage terminal VC, the resistance connection terminal connected to the terminal P, or the resistance connection terminal connected to the terminal N. To.
The storage node SN0 is a connection point between the right end of the capacitor 206, the non-inverting input terminal of the comparator 204, the upper end of the switch 203a, and the right end of the capacitor (hereinafter, also referred to as “capacitor 207”) constituting the receiving circuit 207. It is a node that can store electric charge formed in.

According to the connection configurations of the various capacitors 206 and 207 and the various switches described above, when the switches 203a and 203b are turned off and the switch 203c is turned on, the functions equivalent to those of the subtractor 108a of the first embodiment are obtained. Is demonstrated. That is, in this connected state, the storage node SN0 is a voltage obtained by adding or subtracting the holding voltage of the capacitor 206 (the output voltage of the DA converter 209) to the holding voltage of the capacitor 207 (the voltage of the analog input signal Ain) according to the polarity. The differential voltage SN0 is held.

The switch 203a is composed of a switching element such as a MOS transistor, its upper end is connected to the storage node SN0, and its lower end is connected to the first reference voltage terminal VC. Then, the on / off state is switched according to the control signal CTRL from the control circuit 201, and the storage node SN0 is connected to the first reference voltage terminal VC in the on state.
The switch 203b is composed of a switching element such as a MOS transistor, the right end of which is connected to the right end of the switch 203c and the left end of the receiving circuit 207, and the left end of which is connected to the first reference voltage terminal VC. Then, the on / off state is switched according to the control signal CTRL from the control circuit 201, and when the on / off state, the left end of the receiving circuit 207 is connected to the first reference voltage terminal VC.

The switch 203c is composed of a switching element such as a MOS transistor, and the right end is connected to the right end of the switch 203b and the left end of the receiving circuit 207, and the left end is connected to the signal input terminal Ain of the analog input signal Ain. Then, on / off is switched according to the control signal CTRL from the control circuit 201, and when in the on state, the left end of the receiving circuit 207 is connected to the signal input terminal Ain.
The switching operation is non-overlapping controlled so that the switch 203b and the switch 203c are not turned on at the same time.

According to the configuration described above, the DA converter 209 divides the full-scale voltage with the resistor ladder 210, controls various switches on and off, and transfers the desired voltage dividing voltage from each resistance connection terminal to the capacitor 206. By taking it out, the first comparison voltage is generated.
On the other hand, the comparison resistor ladder type DA conversion circuit 218 includes switches 213a to 213c, a reception circuit 217, a storage node SN1, and a DA converter 219.
The receiving circuit 217 is composed of a capacitor having the same capacitance of Cin as the receiving circuit 207. With this configuration, the receiving circuit 217 has a role of transmitting (adding) the analog input signal Ain input to the signal input terminal Ain to the storage node SN1 which is an input node of the comparator 214.

The DA converter 219 includes a switch group 215, a capacitor 216, and a resistance ladder 220. Here, the switch group 215 corresponds to the second switch circuit described in the claims, and the capacitor 216 corresponds to the second capacitance element described in the claims.
The capacitor 216 has the same configuration as the capacitor 206 except for a part of the connection configuration, and the switch group 215 has the same configuration as the switch group 215 except for a part of the connection configuration. The resistance ladder 220 has the same configuration as the resistance ladder 210.

The common terminal O of the plurality of switches of the switch group 215 is connected to the left end of the capacitor 216, and the terminal C of the top switch is connected to the first reference voltage terminal VC. Further, the terminal P of each switch from the second to the top is any one of the resistance connection terminals corresponding to the potentials from the potential of the top resistance connection terminal connected to the resistance ladder 220 to the first reference voltage VC. It is connected to one. Further, the terminal N of each switch below the switch connected to the terminal P is one of the resistance connection terminals corresponding to the potentials up to the third reference voltage VRN on the negative side of the first reference voltage VC. It is connected.

Then, the plurality of switches of the switch group 215 switch the on / off state according to the control signal CTRL from the control circuit 201, and the terminal C and the terminal O, the terminal P and the terminal O, and the terminal N and the terminal O. Short one of them. As a result, the left end of the capacitor 216 is connected to either the first reference voltage terminal VC, the resistance connection terminal connected to the terminal P, or the resistance connection terminal connected to the terminal N. Will be done.
The storage node SN1 is a connection point between the right end of the capacitor 216, the non-inverting input terminal of the comparator 214, the upper end of the switch 213a, and the right end of the capacitor (hereinafter, also referred to as “capacitor 217”) constituting the receiving circuit 217. It is a charge-storable node formed in.

It should be noted that, according to the connection configurations of the various capacitors 216 and 217 and the various switches described above, when the switches 213a and 213b are turned off and the switch 213c is turned on, the functions equivalent to those of the subtractor 218a of the first embodiment are obtained. Is demonstrated. That is, in this connected state, the storage node SN1 has the holding voltage of the capacitor 217 (voltage of the analog input signal Ain) plus the holding voltage of the capacitor 216 (output voltage of the DA converter 219) according to the polarity. The differential voltage SN1 is held.

The switch 213a is composed of a switching element such as a MOS transistor, its upper end is connected to the storage node SN1, and its lower end is connected to the first reference voltage terminal VC. Then, the on / off state is switched according to the control signal CTRL from the control circuit 201, and the storage node SN1 is connected to the first reference voltage terminal VC in the on state.
The switch 213b is composed of a switching element such as a MOS transistor, and the right end is connected to the right end of the switch 213c and the left end of the receiving circuit 217, respectively, and the left end is connected to the first reference voltage terminal VC. Then, the on / off state is switched according to the control signal CTRL from the control circuit 201, and when the on / off state, the left end of the receiving circuit 217 is connected to the first reference voltage terminal VC.

The switch 213c is composed of a switching element such as a MOS transistor, and the right end is connected to the right end of the switch 213b and the left end of the receiving circuit 217, and the left end is connected to the signal input terminal Ain of the analog input signal Ain. Then, the on / off state is switched according to the control signal CTRL from the control circuit 201, and the left end of the receiving circuit 217 is connected to the signal input terminal Ain in the on state.
The switch 213b and the switch 213c are non-overlapping controlled.
According to the configuration described above, the DA converter 219 divides the full-scale voltage with the resistor ladder 220, controls various switches on and off, and transfers the desired voltage dividing voltage from each resistance connection terminal to the capacitor 216. By taking it out, a second comparison voltage is generated.

The control circuit 201 generates a control signal CTRL that controls the switching operation between the switches 203a to 203c and 213a to 213c and the switches of the switch groups 205 and 215 based on the comparison results DO0 and DO1 of the comparators 204 and 214. It has a function.
The output register 202 has a function of holding signal values (DO0_1 to DO0_n and DO1_1 to DO1_n) indicating the comparison results output by the comparators 204 and 214. In addition, it has a function of generating a (n + 1) bit digital output signal Vout and outputting the generated digital output signal Vout based on the retained comparison results DO0_1 to DO0_n and DO1_1 to DO1_n.

The comparator 204 compares the difference voltage SN0 input to the non-inverting input terminal with the reference voltage VC input to the inverting input terminal according to the rising edge of the clock signal DCLK from the control circuit 201. Then, when "SN0 <VC", a high level signal ("DO0_M = 1") is output as the comparison result DO0_M. Further, when “SN0 ≧ VC”, a low level signal (“DO0_M = 0”) is output as the comparison result DO0_M.
The comparator 214 compares the differential voltage SN1 input to the non-inverting input terminal with the reference voltage VC input to the inverting input terminal according to the rising edge of the clock signal DCLK from the control circuit 201. Then, when "SN1 <VC", a high level signal ("DO1_M = 1") is output as the comparison result DO1_M. When “SN1 ≧ VC”, a low-level signal (“DO1_M = 0”) is output as the comparison result DO1_M.

[About the differential voltage SN0 of the storage node SN0]
Here, the switches 203a and 203b are turned off, and the switch 203c is turned on so that the analog input signal Ain is transmitted to the non-inverting input terminal of the comparator 204.
The differential voltage SN0 at this time changes depending on the on / off state of each switch of the switch group 205. Further, this differential voltage SN0 can be expressed by the following equation (7), ignoring the influence of parasitic capacitance.
SN0 = (Cin / (Cin + C)), Ain + (Cin / (Cin + C)), (VR0-VC) + VC ... (7)

In the above equation (7), VR0 is the voltage of the terminal O of any one of the plurality of switches of the switch group 205 selected by the control value DA0. Further, Cin is the capacitance value of the capacitor 207, and C is the capacitance value of the capacitor 206.
Since the second term of the above equation (7) is determined by the control value DA0, the above equation (7) and the equation (4) of the first embodiment are equivalent. The difference voltage SN1 is the same as that of SN0.
Therefore, the sequential comparison type AD converter 2 according to the third embodiment can operate in the same manner as the sequential comparison type AD converter 1 of the first embodiment.

[Action and effect of the third embodiment]
In the sequential comparison type AD converter 2 according to the third embodiment, the receiving circuits 207 and 217 receive the analog input signal Ain and output the analog input signal AinO corresponding to the analog input signal Ain. By the subtraction operation by the divided voltage of the capacitors 206 and 207 provided in the comparison resistance ladder type DA conversion circuit 208 and the subtraction operation by the divided voltage of the capacitors 216 and 217 provided in the comparison resistance ladder type DA conversion circuit 218. , The difference signal (difference voltage SN0 and SN1) between the analog input signal AinO in each of the n sequential conversions and the DA-converted analog comparison signal (first and second comparison voltage) obtained by DA-converting the control values DA0 and DA1. ) Is calculated. The comparators 204 and 214 determine whether the differential voltages SN0 and SN1 are higher than the reference voltage VC. The control circuit 201 calculates the digital output signal Vout corresponding to the analog input signal AinO based on the comparison results DO0 and DO1 of the comparators 204 and 214. Further, the control circuit 201 sets the control values DA0 and DA1 so that the analog comparison signals (first and second comparison voltages) approach the analog input signals AinO based on the comparison results DO0 and DO1 of the comparators 204 and 214. Update. The DA converters 209 and 219 convert the control values DA0 and DA1 into analog comparison signals (first and second comparison voltages). The output register 202 outputs a digital output signal based on the comparison results DO0 and DO1 of the comparators 204 and 214.

Further, a first reference voltage terminal VC having a first reference voltage VC, a second reference voltage terminal VRP having a second reference voltage VRP on the positive side with reference to the first reference voltage VC, and a first reference voltage VC as a reference. A third reference voltage terminal VRN having a negative third reference voltage VRN is provided. Further, the receiving circuits 207 and 217 have a capacitor having a capacitance of Cin. Further, the DA converter 209 is connected to a resistor ladder 210 having a plurality of resistance elements connected in series between the second reference voltage terminal VRP and the third reference voltage terminal VRN, and one end of each resistor node SN0. One of a plurality of resistance connection terminals formed at each connection portion between the resistance elements of the plurality of resistance elements of the resistance ladder 210 at the other end of the capacitor 206 according to the digital signal of the capacitor 206 and the control value DA0. Connect to. Further, the DA converter 219 has a resistor ladder 220 having a plurality of resistance elements connected in series between the second reference voltage terminal VRP and the third reference voltage terminal VRN, and one end of each is connected to the storage node SN1. One of a plurality of resistance connection terminals formed at each connection portion between the resistance elements of the plurality of resistance elements of the resistance ladder 220 at the other end of the capacitor 216 according to the digital signal of the capacitor 216 and the control value DA1. Connect to.

With this configuration, when the analog input signal Ain is received by the receiving circuits 207 and 217, the analog input signal AinO corresponding to the received analog input signal Ain can be output to the storage nodes SN0 and SN1. As a result, the control circuit 201, the comparators 204 and 214, and the output register 202 can perform AD conversion processing such as comparison processing on the analog input signal AinO that changes in real time. As a result, it is possible to eliminate the delay due to the sample hold as compared with the configuration in which the fixed analog input signal sample-held is subjected to AD conversion processing, and the conversion speed can be improved.

[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described with reference to FIGS. 14 to 16.
Here, FIG. 14 is a block diagram showing a configuration example of the pipeline type AD converter according to the fourth embodiment, and FIG. 15 is a block diagram showing a specific configuration example of the unit block according to the fourth embodiment. It is a figure. Further, FIG. 16 is a timing chart at the time of comparison operation of the sequential comparison type sub-AD converter constituting the unit block of the first stage and the next stage of the pipeline type AD converter according to the fourth embodiment.

[Constitution]
In the fourth embodiment, in the pipeline type A / D converter, the sequential comparison type AD converter 1 of the first embodiment is applied to the final stage AD converter and the sub AD converter of each unit block. It has become. That is, it can be said that the fourth embodiment is a configuration in which the sequential comparison type AD converter 1 of the first embodiment is applied as the SAR (sequential comparison type AD converter) constituting the pipeline type AD converter.

As shown in FIG. 14, the pipeline type AD converter 30 according to the fourth embodiment includes unit blocks 3_1, 3_2, 3_3, and 3_4 which are sequentially connected in order from the first stage to the fourth stage. In addition, the final stage sequential comparison type sub-AD converter 4 and the encoder 5 are sequentially connected to the unit block 3_4. Here, the sequential comparison type sub-AD converter 4 has the same configuration as the sequential comparison type AD converter 1 of the first embodiment. Further, the unit blocks 3_1 to 3_4 correspond to a plurality of stages described in the claims, and the sequential comparison type sub-AD converter 4 corresponds to the final stage described in the claims.

Since the unit blocks 3_1 to 3_4 have the same configuration, the unit blocks 3_1 to 3_4 are simply referred to as "unit blocks 3" when it is not necessary to distinguish them.
As shown in FIG. 15, the unit block 3 includes a sequential comparison type sub-AD converter 6, a DA converter 7, a subtractor 8, and an amplifier 9.
The sequential comparison type sub-AD converter 6 has the same configuration as the sequential comparison type AD converter 1 of the first embodiment. The sequential comparison type sub-AD converter 6 AD-converts the analog input signal Ain or the analog difference signal (described later) input from the unit block 3 in the previous stage, and DA-converts the digital signal of the AD conversion result to the encoder 5. Output to the device 7 and each.

The DA converter 7 DA-converts the digital signal input from the sequential comparison type sub-AD converter 6 into an analog signal, and outputs the analog signal of the DA conversion result to the subtractor 8.
The subtractor 8 subtracts the analog signal input from the DA converter 7 from the analog input signal Ain input from the signal input terminal Ain, and outputs the analog difference signal of the subtraction result to the amplifier 9.
The amplifier 9 amplifies the analog difference signal input from the subtractor 8 and outputs the amplified difference signal to the unit block 3 in the next stage or the sequential comparison type sub-AD converter 4 in the final stage. Here, the amplifier 9 corresponds to the amplifier circuit described in the claims.

The encoder 5 adds the digital signals input from the unit blocks 3_1 to 3_4 and the successive approximation type sub-AD converter 4 to calculate the final digital output signal Vout, and outputs the calculated digital output signal Vout.
The sequential comparison type sub-AD converters 4 and 6 are not limited to the same configuration as the sequential comparison type AD converter 1 of the first embodiment, and the sequential comparison type AD converter 1A of the first embodiment and the above. It may have the same configuration as any one of the sequential comparison type AD converter 1B of the second embodiment and the sequential comparison type AD converter 2 of the third embodiment.

With such a configuration, the pipeline type AD converter 30 according to the fourth embodiment can perform the comparative operation shown in FIG.
That is, in the successive approximation type sub-AD converter 6 constituting the unit blocks 3_1 and 3_2, the comparison operation is performed while receiving the signal without holding the sample of the analog input signal. Therefore, as shown in FIG. 16, it is not necessary to sample the signal in the period corresponding to the “third time interval” of the pipeline type AD converter according to Patent Document 2 shown in FIG. That is, since there is no "third time interval", the conversion delay is shortened by that amount and high-speed operation is possible.

[Action and effect of the fourth embodiment]
The pipeline type AD converter 30 according to the fourth embodiment includes a unit block 3_1 to 3_4 connected in cascade and a sequential comparison type sub AD converter 4 in the final stage. Each of the unit blocks 3_1 to 3_4 converts the serial comparison type sub-AD converter 6 that converts the analog input signal into a digital output signal and the digital output signal output by the sequential comparison type sub-AD converter 6 into an analog output signal. It has a DA converter 7 and an amplifier 9 that amplifies the signal of the difference between the analog input signal and the analog output signal. Further, the sequential comparison type sub-AD converter 4 in the final stage converts the analog difference signal output by the unit block 3_4 into a digital signal. The sequential comparison type sub-AD converters 4 and 6 are composed of the sequential comparison type AD converter 1 of the first embodiment.

With this configuration, it is possible to realize a pipeline-type AD converter with low power consumption and suppressed increase in layout area while maintaining the same conversion delay time as when the sub-AD converter is configured with a flash-type AD converter. Can be done.

[Modification example]
In the second embodiment, the comparison operation performed in parallel by the two sets of comparative switched capacitor circuits and the comparator in the first embodiment is performed by one set of the comparative switched capacitor circuits and the comparator. However, the configuration is not limited to this configuration. For example, a set of comparative switched capacitor circuits and a comparator may be configured to perform the same comparison operation as the successive approximation type A / D converter of the related technology. Even with this configuration, it is possible to eliminate the conversion delay due to the sample hold as compared with the related technology as in the first embodiment. However, as compared with the first embodiment, since there is no range in which the comparison voltage partially overlaps in the Jth and (J + 1) th comparison operations, it is possible to reduce the conversion error when the analog input signal Ain changes. Can not. However, it is effective in an environment where there is little change in the analog input signal Ain.

Further, in the third embodiment, the comparison operation is performed in parallel in the same manner as in the first embodiment by the two sets of the comparison resistance ladder type DA conversion circuit and the comparator, but the configuration is not limited to this. For example, as in the second embodiment, a set of comparison resistance ladder type DA conversion circuit and a comparator may be configured to perform time division, or a set of comparison resistance ladder type DA conversion circuit and comparison. The device may be configured to perform the same comparison operation as the sequential comparison type A / D converter of the related technology.
Further, in the first and second embodiments, the comparative voltage is generated by using the comparative switched capacitor circuit, but the present invention is not limited to this configuration. For example, by connecting the output of the resistance ladder type DA conversion circuit as used in the third embodiment to the VRP and VRN terminals of the comparative switched capacitor circuit, the DA that combines the switched capacitor circuit and the resistance ladder circuit is combined. It may be configured as a conversion circuit.

The sequential comparison type AD conversion circuit according to the first and third embodiments includes two receiving circuits, two comparators, two DA converters, and two subtractors, but the present invention is not limited thereto. The sequential comparison type AD conversion circuit may include three or more receiving circuits, a comparator, a DA conversion circuit, and a subtractor. In this case, since three or more comparison voltages are set, AD conversion can be performed with higher accuracy.

1,1A, 1B, 2 ... Sequential comparison type AD converter, 3_1-3_4 ... Unit block, 4,6 ... Sequential comparison type sub AD converter, 5 ... Encoder, 7,109,109A, 119,119A, 209, 219 ... DA converter, 8,108a, 108b, 118a, 118b ... Subtractor, 9 ... Amplifier, 30 ... Pipeline type AD converter, 101, 201 ... Control circuit, 102, 202 ... Output register, 104, 114, 204, 214 ... Comparator, 103a-103c, 103d_1 to 103d_ (n + 1), 103e_1 to 103e_ (n + 1), 103f_1 to 103f_ (n + 1), 113a to 113c, 113d_1 to 113d_ (n + 1), 113e_1 to 113e_ (n + 1), 113f_1 to 113f_ (n + 1), 203a to 203c ... Switches, 105_1 to 105_ (n + 1), 115_1 to 115_ (n + 1), 205,215 ... Switch group, 107,107A, 117,117A, 207,217 ... Receiver circuit, 108 , 118 ... Comparison switched capacitor circuit, 208, 218 ... Comparison resistance ladder type DA conversion circuit, SN0, SN1 ... Storage node, VC ... First reference voltage terminal, VRP ... Second reference voltage terminal, VRN ... Third Reference voltage terminal

Claims (9)

A receiving circuit that receives the first analog input signal and continuously outputs the second analog input signal corresponding to the first analog input signal.
A difference signal calculation circuit that calculates a difference signal between the second analog input signal and the analog reference signal in each of n times (n is a natural number of 2 or more, the same applies hereinafter) sequential conversion.
A determination circuit that determines whether the voltage of the difference signal is higher than the reference voltage, and
A reference value calculation circuit that updates the reference value so that the analog reference signal approaches the second analog input signal based on the determination result of the determination circuit.
A DA converter that converts the reference value into the analog reference signal,
An output circuit that outputs a digital output signal based on the judgment result of the judgment circuit,
Sequential comparison type AD converter. The first to third m (m is a natural number of 2 or more, the same applies hereinafter) and the receiving circuit.
The first to mth determination circuits and
With the first to mth DA converters
The first to mth difference signal calculation circuits are provided.
The reference value calculation circuit is
Based on the determination result at the timing of the sequential conversion of the first to first m determination circuits, the reference value corresponding to each of the first to mth DA converters is updated.
The output circuit
The digital output signal is calculated based on the determination result of the first to first m determination circuits.
The sequential comparison type AD converter according to claim 1. The reference value calculation circuit is
Based on the determination results of the first to first m determination circuits, a voltage range having a plurality of determination sections when determining the second analog input signal is set.
The jth time (j is a natural number of 1 ≦ j ≦ (n-1), the same applies hereinafter) of the judgment circuit is set based on the judgment result in the first judgment section among the plurality of judgment sections. The voltage range at the time of determination overlaps with the voltage range at the time of the (j + 1) th determination set based on the determination result in the second determination section adjacent to the first determination section at least in a part. The sequential comparison type AD converter according to claim 2, wherein the reference value corresponding to each of the first to mth DA converters is updated. The reference value calculation circuit is
At the time of the (j + 1) th determination, the width of the voltage range corresponds to each of the first to mth DA converters so as to be half the width of the width of the voltage range at the time of the jth determination. The sequential comparison type AD converter according to claim 3, wherein the reference value is updated. The receiving circuit
The first switch circuit to which the first analog input signal is input and
The first capacitive element connected between the difference signal calculation circuit and
The sequential comparison type AD converter according to claim 1. The first reference voltage terminal having the first reference voltage and
A second reference voltage terminal having a second reference voltage on the positive side with reference to the first reference voltage,
A third reference voltage terminal having a third reference voltage on the negative side with respect to the first reference voltage is provided.
The DA converter
A second to third L (L is a natural number of 3 or more, the same applies hereinafter) capacitance element, each end of which is connected to the difference signal calculation circuit.
The other end of each of the second to second L capacitance elements is connected to any one of the first reference voltage terminal, the second reference voltage terminal, or the third reference voltage terminal according to the reference value. The sequential comparison type AD converter according to claim 5, which comprises a two-switch circuit. Among the first to first L capacitance elements, the capacitance value of the Kth capacitance element (K is a natural number of 2 ≦ K ≦ L) is
It is a value obtained by multiplying the capacitance value of the Lth capacitance element by 2 (LK).
The sequential comparison type AD converter according to claim 6. The first reference voltage terminal having the first reference voltage and
A second reference voltage terminal having a second reference voltage on the positive side with reference to the first reference voltage,
A third reference voltage terminal having a third reference voltage on the negative side with respect to the first reference voltage is provided.
The DA converter
A plurality of resistance elements connected in series between the second reference voltage terminal and the third reference voltage terminal, and
A second capacitive element whose one end is connected to the difference signal calculation circuit,
A second switch circuit that connects the other end of the second capacitance element to any one of a plurality of terminals formed at each connection portion between the resistance elements of the plurality of resistance elements according to the reference value. The sequential comparison type AD converter according to claim 1, wherein the device has. A pipeline-type AD converter having a plurality of vertically connected stages and a final stage.
Each of the plurality of stages
A first sequential comparison type sub-AD converter that converts an analog input signal to a digital output signal,
A DA converter that converts the digital output signal output by the first sequential comparison type sub-AD converter into an analog output signal, and
An amplifier circuit that amplifies the signal of the difference between the analog input signal and the analog output signal, and
Have,
The final stage is
It has a second sequential comparison type sub-AD converter that converts the difference signal output by the final stage of the plurality of stages into a digital output signal.
The first and second successive approximation type sub-AD converters are composed of the sequential comparison type AD converter according to any one of claims 1 to 8.
Pipeline type AD converter.

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