CN110572158A - successive approximation ADC (analog to digital converter) capacitor array circuit and capacitor switch control method thereof - Google Patents
successive approximation ADC (analog to digital converter) capacitor array circuit and capacitor switch control method thereof Download PDFInfo
- Publication number
- CN110572158A CN110572158A CN201910984729.XA CN201910984729A CN110572158A CN 110572158 A CN110572158 A CN 110572158A CN 201910984729 A CN201910984729 A CN 201910984729A CN 110572158 A CN110572158 A CN 110572158A
- Authority
- CN
- China
- Prior art keywords
- capacitor
- capacitors
- external
- weight
- capacitor array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/462—Details of the control circuitry, e.g. of the successive approximation register
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
the invention discloses a capacitor array circuit of a successive approximation ADC and a capacitor switch control method thereof. The invention can effectively reduce the dynamic power consumption of the capacitor array circuit and the establishment time of the capacitor in the switching process of the capacitor switch, thereby realizing high-speed and low-power consumption analog-to-digital conversion.
Description
Technical Field
The invention belongs to the field of successive approximation type ADCs (analog to digital converters) in mixed signal circuit design, and particularly relates to a capacitor array circuit applied to the successive approximation type ADCs and a capacitor switch control method thereof.
background
In modern information technology, an Analog-to-Digital Converter (ADC) is used as an important bridge for connecting an Analog signal and a Digital signal, and the performance of the ADC directly affects the performance of the whole signal processing system. Now, with the rise of 5G mobile communication and the wide application of wearable devices, higher requirements are put on performances such as conversion speed and overall power consumption of the ADC. Therefore, the research on the ADC with high speed and low power consumption has great significance and value.
the successive approximation ADC has a simple overall structure, only contains a small number of analog modules compared with other types of ADCs, can well match the progress of the process and is suitable for occasions with low power consumption, and therefore the successive approximation ADC is widely concerned. However, the conversion speed of the conventional successive approximation ADC is not high due to the conventional binary conversion algorithm. In addition, in the successive approximation ADC, the power consumption of the capacitor array circuit and the comparator occupies most of the overall power consumption of the ADC, and cannot be reduced as the process advances. The two-bit per-cycle quantization structure can theoretically improve the conversion speed of the traditional successive approximation type ADC by two times, but at the same time, the power consumption of the whole ADC is increased, and the speed improvement is seriously limited in turn.
Disclosure of Invention
Aiming at the defects of low conversion speed and high power consumption of a capacitor array circuit of the traditional successive approximation ADC, the invention designs the capacitor array circuit of the successive approximation ADC and a capacitor switch control method thereof, so as to reduce the dynamic power consumption in the switching process of a capacitor switch by reasonably designing the weight of each capacitor in a capacitor array while effectively improving the overall conversion speed, thereby achieving the purpose of reducing the power consumption of the whole ADC.
The invention adopts the following technical scheme for solving the technical problems:
The invention relates to a capacitor array circuit of a successive approximation ADC (analog to digital converter), which is characterized by consisting of a capacitor array module and a capacitor switch module;
The capacitor array module comprises two capacitor arrays, namely a first capacitor array and a second capacitor array, wherein each capacitor array is composed of a positive end and a negative end, the two capacitor arrays are connected with three external comparators, the positive ends of the two capacitor arrays are respectively connected with the positive input ends of the first external comparator and the third external comparator, the negative ends of the two capacitor arrays are respectively connected with the negative input ends of the first external comparator and the third external comparator, the positive input end of the second external comparator is connected with the positive input end of the first external comparator, and the negative input end of the second comparator is connected with the negative input end of the third external comparator;
The capacitance switch module is composed of 4m capacitance switches, one end of each capacitance switch is a free end, the other end of each capacitance switch is a fixed end, wherein m is 2N-2, N is the resolution digit of the ADC and is an even number;
the positive end and the negative end of each capacitor array are respectively composed of m capacitors with weights, and the weights of the m capacitors are respectively (3 multiplied by 2)0)C、(1×20)C、(4×20)C、(4×20)C、(3×22)C、(1×22)C、(4×22)C、(4×22)C、…、(3×2i)C、(1×2i)C、(4×2i)C、(4×2i)C、…、(3×2N-6)C、(1×2N-6)C、(4×2N-6)C、(4×2N-6)C、(3×2N -4)C、(1×2N-4)C、(4×2N-4)C、(4×2N-4) C, 3C, 1C, wherein C is a unit capacitance, i ═ 0, 2, 4, 6, 8, …, N-6, N-4;
One ends of m capacitors in the positive end are connected with a positive input end of an external comparator and a common-mode voltage end, and the other ends of the m capacitors are correspondingly connected with fixed ends of m capacitor switches respectively;
One ends of m capacitors in the negative end are connected with the negative input end of the external comparator and the common-mode voltage end, and the other ends of the m capacitors are correspondingly connected with the fixed ends of the m capacitor switches respectively;
Taking a polar plate at one end of each capacitor connected with the external comparator as a top polar plate, and taking one end connected with the fixed end of the capacitor switch as a bottom polar plate;
The free ends of the capacitance switches corresponding to the capacitances with the weights of 3C and 1C are switched between the analog input signal end and the reference voltage end or switched between the analog input signal end and the ground end;
The free ends of the capacitance switches corresponding to the other m-2 capacitances are switched among the analog input signal end, the reference voltage end and the ground end;
Under the control of different digital output signals of an external comparator, the capacitance switch module switches the connection state of the free end of the corresponding capacitance switch, so that the bottom plate of the capacitor is connected to different voltages.
the invention relates to a capacitance switch control method of a capacitance array circuit of a successive approximation ADC, which is characterized by comprising the following steps of:
Step 1, connecting bottom plates of all capacitors in a capacitor array module with an analog input signal end, connecting a top plate with a common mode voltage end, and completing sampling of analog input signals by the bottom plates of the capacitors;
step 2, in a first quantization period, firstly disconnecting the positive and negative ends of the two capacitor arrays from the common-mode voltage end, and carrying out switching operation aiming at all the capacitor switches, wherein the operation comprises the following steps: the weights in the positive terminals of the first capacitor array are respectively (1 multiplied by 2)0)C、(4×20)C、(4×20)C、(1×22)C、(4×22)C、(4×22)C、…、(1×2i)C、(4×2i)C、(4×2i)C、…、(1×2N-6)C、(4×2N-6)C、(4×2N-6)C、(1×2N-4)C、(4×2N-4)C、(4×2N-4) The bottom plates of the capacitors C and 3C are all connected with a reference voltage end, and the bottom plates of the other capacitors are all connected with a ground end, wherein i is 0, 2, 4, 6, 8, …, N-6 and N-4;
the weights of the negative terminals of the first capacitor array are (1 × 2)0)C、(4×20)C、(4×20)C、(1×22)C、(4×22)C、(4×22)C、…、(1×2i)C、(4×2i)C、(4×2i)C、…、(1×2N-6)C、(4×2N-6)C、(4×2N-6)C、(1×2N-4)C、(4×2N-4)C、(4×2N-4) The bottom plates of the capacitors C and 3C are all grounded, and the bottom plates of the rest capacitors are all connected with a reference voltage terminal, wherein i is 0, 2, 4, 6, 8, …, N-6,N-4;
the weights in the positive terminals of the second capacitor arrays are respectively (3 multiplied by 2)0)C、(3×22)C、…、(3×2i)C、…、(3×2N -6)C、(3×2N-4) The bottom plates of the capacitors C and 1C are all connected with a reference voltage end, and the bottom plates of the other capacitors are all connected with a ground end, wherein i is 0, 2, 4, 6, 8, …, N-6 and N-4;
The weights of the negative terminals of the second capacitor array are (3 x 2)0)C、(3×22)C、…、(3×2i)C、…、(3×2N -6)C、(3×2N-4) The bottom plates of the capacitors C and 1C are all grounded, and the bottom plates of the other capacitors are all connected with a reference voltage end, wherein i is 0, 2, 4, 6, 8, …, N-6 and N-4;
and 3, after the switching is finished, comparing the voltage of the capacitor top plate with the quantization threshold value generated in the first quantization period by using three external comparators respectively, so as to generate and output two groups of complementary three-position thermometer codes in the first quantization period, wherein the complementary outputs of the three external comparators are respectively CP2/CN2、CP1/CN1、CP0/CN0;
step 4, in the second quantization period, aiming at the weight of (3 multiplied by 2)N-4)C、(1×2N-4)C、(4×2N-4)C、(4×2N-4) C, the capacitance switch corresponding to the capacitor is switched, and the capacitance switch module is controlled according to four possible situations of the generated three-position thermometer code in the first quantization period;
Step 4.1, if the three-digit thermometer code CP generated in step 42CP1CP0to "000", an output CP of the first external comparator is used2The weight in the positive end of the first capacitor array is controlled to be (3 multiplied by 2)N-4) The capacitor switch corresponding to the capacitor C has its bottom plate connected to the reference voltage terminal and the other output CN of the first external comparator2The weight of the negative terminal of the first capacitor array is controlled to be (3 multiplied by 2)N-4) The bottom pole plate of the capacitor switch corresponding to the capacitor C is connected with the ground end;
using a set of outputs CP of three comparators simultaneously2、CP1、CP0Respectively controlling the weight of the positive end of the second capacitor array to be (1 multiplied by 2)N-4)C、(4×2N-4)C、(4×2N-4) The capacitor switch corresponding to the capacitor C has its bottom plate connected to the reference voltage terminal and the other group of three comparators outputs CN2、CN1、CN0Respectively controlling the weight of the negative terminal of the second capacitor array to be (1 x 2)N-4)C、(4×2N-4)C、(4×2N-4) The bottom pole plate of the capacitor switch corresponding to the capacitor C is connected with the ground end; and the connection state of the bottom plates of the other capacitors is kept unchanged;
Step 4.2, if the three-digit thermometer code CP generated in step 42CP1CP0to "100", an output CP of the first external comparator is used2The weight in the positive end of the first capacitor array is controlled to be (1 multiplied by 2)N-4) The capacitor switch corresponding to the capacitor C has its bottom plate connected to ground and the other output CN of the first external comparator2The weight of the negative terminal of the first capacitor array is controlled to be (1 multiplied by 2)N-4) C, the capacitor switch corresponding to the capacitor makes the bottom plate connected with the reference voltage end;
Using a set of outputs CP of second and third external comparators simultaneously1、CP0respectively controlling the weight of the positive end of the second capacitor array to be (1 multiplied by 2)N-4)C、(4×2N-4) The capacitor switch corresponding to the capacitor C has its bottom plate connected to the reference voltage terminal and the other group of the second and third external comparators outputs CN1、CN0Respectively controlling the weight of the negative terminal of the second capacitor array to be (1 x 2)N-4)C、(4×2N-4) The bottom pole plate of the capacitor switch corresponding to the capacitor C is connected with the ground end; and the connection state of the bottom plates of the other capacitors is kept unchanged;
Step 4.3, if the three-digit thermometer code CP generated in step 42CP1CP0To "110", a set of outputs CP of the first and second external comparators is used2、CP1respectively controlling the weight of the positive end of the first capacitor array to be (1 multiplied by 2)N-4)C、(4×2N-4) The capacitor switch corresponding to the capacitor C has its bottom plate connected to ground and the other group of the first and second external comparators outputs CN2、CN1respectively controlling the weight of the negative terminal of the first capacitor array to be (1 x 2)N-4)C、(4×2N-4) C, the capacitor switch corresponding to the capacitor makes the bottom plate connected with the reference voltage end;
Using simultaneously an output CP of a third external comparator0The weight in the positive end of the second capacitor array is controlled to be (1 multiplied by 2)N -4) The capacitor switch corresponding to the capacitor C has its bottom plate connected to the reference voltage terminal and the other output CN of the third external comparator0the weight of the negative terminal of the second capacitor array is controlled to be (1 multiplied by 2)N-4) The bottom pole plate of the capacitor switch corresponding to the capacitor C is connected with the ground end; and the connection state of the bottom plates of the other capacitors is kept unchanged;
Step 4.4, if the three-digit thermometer code CP generated in step 42CP1CP0To "111", a set of outputs CP of three external comparators is used2、CP1、CP0Respectively controlling the weight of the positive end of the first capacitor array to be (1 multiplied by 2)N-4)C、(4×2N-4)C、(4×2N-4) The capacitor switch corresponding to the capacitor C has its bottom plate connected to ground and the other group of three external comparators outputs CN2、CN1、CN0Respectively controlling the weight of the negative terminal of the first capacitor array to be (1 x 2)N-4)C、(4×2N-4)C、(4×2N-4) C, the capacitor switch corresponding to the capacitor makes the bottom plate connected with the reference voltage end;
using simultaneously an output CP of a third external comparator0the weight in the positive end of the second capacitor array is controlled to be (3 multiplied by 2)N -4) The bottom plate of the capacitor switch corresponding to the capacitor C is connected with the ground end, and the other output CN of the third external comparator is used0The weight of the negative terminal of the second capacitor array is controlled to be (3 multiplied by 2)N-4) C, the capacitor switch corresponding to the capacitor makes the bottom plate connected with the reference voltage end; and the connection state of the bottom plates of the other capacitors is kept unchanged;
Step 5, after the switching is finished, comparing the voltage of the capacitor top plate with a quantization threshold value generated in a second quantization period by using three external comparators respectively, so as to generate and output two groups of complementary three-position thermometer codes in the second quantization period;
Step 6, in the third quantization period and each subsequent quantization period, the relationship between the capacitor switch performing the switching operation and the capacitor switch performing the switching operation in the previous quantization period is as follows: the weight of the capacitor corresponding to the capacitor switch which is switched in the current quantization period is 1/4 of the weight of the capacitor corresponding to the capacitor switch which is switched in the previous quantization period, and the connection state of the capacitor switches which are switched in all quantization periods before the current quantization period is kept unchanged;
And then according to four possible situations of the generated three-position thermometer code in the previous quantization period, continuously controlling other capacitance switches in the capacitance switch module according to the modes from the step 4.1 to the step 4.4 until the switching operation of the capacitance switch in the Nth/2 th quantization period is completed.
compared with the prior art, the invention has the beneficial effects that:
1. based on the principle of quantizing two bits per cycle, the invention adopts the structure of split capacitors, achieves the purpose of improving the conversion speed of successive approximation ADC by reasonably designing the weight of each capacitor in the capacitor array module and combining the designed capacitor switch control method, and simultaneously reduces the dynamic power consumption in the capacitor array circuit and improves the performance of the whole ADC.
2. The capacitor array circuit and the capacitor switch control method designed by the invention meet the actual requirement of quantizing two bits per period, and greatly improve the overall conversion speed of the ADC compared with the traditional structure.
3. The invention adopts the structure of the split capacitor, realizes the direct control of the capacitor switch module through the output of the comparator, avoids redundant operation, simplifies the design of a control logic circuit, further improves the overall conversion speed and reduces the power consumption of the ADC.
Drawings
FIG. 1 is a schematic diagram of a capacitor array circuit of the present invention with a resolution of 6 bits;
FIG. 2a is a schematic illustration of a sampling phase of the present invention;
FIG. 2b is a schematic diagram of the present invention during a first quantization period;
FIG. 2c shows the CP in the first quantization period according to the present invention2CP1CP0At "000", during the second quantization period;
FIG. 2d shows the CP in the first quantization period according to the present invention2CP1CP0a schematic diagram during a second quantization period at "100";
FIG. 2e shows the CP in the first quantization period according to the present invention2CP1CP0A plot during the second quantization period at "110";
FIG. 2f shows the CP in the first quantization period according to the present invention2CP1CP0A plot during the second quantization period at "111";
FIG. 3 shows the present invention when the CP is in the first and second quantization periods2CP1CP0All of which are "000", the third quantization period is the capacitance switch diagram requiring the switching operation.
Detailed Description
In this embodiment, as shown in fig. 1, a successive approximation ADC capacitor array circuit is characterized by comprising a capacitor array module and a capacitor switch module;
the capacitor array module comprises two capacitor arrays which are respectively a first capacitor array (a capacitor array 1) and a second capacitor array (a capacitor array 2), each capacitor array is composed of a positive end and a negative end, the two capacitor arrays are connected with three external comparators (a comparator 1, a comparator 2 and a comparator 3), wherein the positive ends of the two capacitor arrays are respectively connected with the positive input ends of the first external comparator (the comparator 1) and the third external comparator (the comparator 3), the negative ends of the two capacitor arrays are respectively connected with the negative input ends of the first external comparator and the third external comparator, the positive input end of the second external comparator (the comparator 2) is connected with the positive input end of the first external comparator, and the negative input end of the second comparator is connected with the negative input end of the third external comparator;
The capacitance switch module is composed of 4m capacitance switches, one end of each capacitance switch is a free end, and the other end of each capacitance switch is a fixed end, wherein m is 2N-2, N is the resolution digit of the ADC and is an even number, in this embodiment, N is 6, and m is 10;
The positive end and the negative end of each capacitor array are respectively composed of m capacitors with weights, and the weights of the m capacitors are respectively (3 multiplied by 2)0)C、(1×20)C、(4×20)C、(4×20)C、(3×22)C、(1×22)C、(4×22)C、(4×22)C、…、(3×2i)C、(1×2i)C、(4×2i)C、(4×2i)C、…、(3×2N-6)C、(1×2N-6)C、(4×2N-6)C、(4×2N-6)C、(3×2N -4)C、(1×2N-4)C、(4×2N-4)C、(4×2N-4) C, 3C, and 1C, where C is a unit capacitance, i is 0, 2, 4, 6, 8, …, N-6, and N-4, and the weight of each capacitor in this embodiment is 3C, 1C, 4C, 12C, 4C, 16C, 3C, and 1C;
one end of each of m capacitors in the positive terminal is connected with the positive input end of the external comparator and the common mode voltage terminal, and the other end is correspondingly connected with the fixed ends of the m capacitor switches, wherein the common mode voltage terminal is V in the embodimentcma terminal;
One ends of m capacitors in the negative end are connected with the negative input end of the external comparator and the common-mode voltage end, and the other ends of the m capacitors are correspondingly connected with the fixed ends of the m capacitor switches respectively;
taking a polar plate at one end of each capacitor connected with the external comparator as a top polar plate, and taking one end connected with the fixed end of the capacitor switch as a bottom polar plate;
the free end of the capacitor switch corresponding to the capacitor with the weight of 3C and 1C is switched between the analog input signal end and the reference voltage end or between the analog input signal end and the ground endThe analog input signal end is a differential signal VipTerminal and Vinterminal, reference voltage terminal is VrefA terminal;
the free ends of the capacitance switches corresponding to the other m-2 capacitances are switched among the analog input signal end, the reference voltage end and the ground end;
Under the control of different digital output signals (CP2/CN2, CP1/CN1, CP0/CN0) of an external comparator, the capacitance switch module switches the connection state of the free end of the corresponding capacitance switch, so that the bottom plate of the capacitance is connected to different voltages.
In this embodiment, as shown in fig. 2a to fig. 2f, the method for controlling a capacitance switch of a capacitor array circuit of a successive approximation ADC according to the present invention is illustrated with a resolution of 6 bits, and the method for controlling a capacitance switch of a capacitor array circuit of a successive approximation ADC is performed as follows:
step 1, as shown in fig. 2a, connecting the bottom plates of all capacitors in the capacitor array module to an analog input signal end, connecting the top plate to a common mode voltage end, and completing sampling of the analog input signal by the bottom plates of the capacitors;
Step 2, as shown in fig. 2b, in the first quantization period, first disconnecting the positive and negative terminals of the two capacitor arrays from the common mode voltage terminal, and performing a switching operation for all the capacitor switches, including: the weights in the positive terminals of the first capacitor array are respectively (1 multiplied by 2)0)C、(4×20)C、(4×20)C、(1×22)C、(4×22)C、(4×22)C、…、(1×2i)C、(4×2i)C、(4×2i)C、…、(1×2N-6)C、(4×2N-6)C、(4×2N-6)C、(1×2N-4)C、(4×2N-4)C、(4×2N-4) The bottom plates of the capacitors C and 3C are all connected to the reference voltage terminal, and the bottom plates of the other capacitors are all connected to the ground terminal, where i is 0, 2, 4, 6, 8, …, N-6, and N-4, and the weights of the capacitors in this embodiment are 1C, 4C, 16C, and 3C, respectively;
The weights of the negative terminals of the first capacitor array are (1 × 2)0)C、(4×20)C、(4×20)C、(1×22)C、(4×22)C、(4×22)C、…、(1×2i)C、(4×2i)C、(4×2i)C、…、(1×2N-6)C、(4×2N-6)C、(4×2N-6)C、(1×2N-4)C、(4×2N-4)C、(4×2N-4) All the bottom plates of the capacitors of C and 3C are grounded, and all the bottom plates of the other capacitors are grounded, wherein i is 0, 2, 4, 6, 8, …, N-6, and N-4, and the weights of the capacitors in this embodiment are 1C, 4C, 16C, and 3C, respectively;
The weights in the positive terminals of the second capacitor arrays are respectively (3 multiplied by 2)0)C、(3×22)C、…、(3×2i)C、…、(3×2N -6)C、(3×2N-4) The bottom plates of the capacitors C and 1C are all connected to the reference voltage terminal, and the bottom plates of the other capacitors are all connected to the ground terminal, where i is 0, 2, 4, 6, 8, …, N-6, and N-4, and the weights of the capacitors in this embodiment are 3C, 12C, and 1C, respectively;
the weights of the negative terminals of the second capacitor array are (3 x 2)0)C、(3×22)C、…、(3×2i)C、…、(3×2N -6)C、(3×2N-4) All the bottom plates of the capacitors of C and 1C are grounded, and all the bottom plates of the other capacitors are grounded, wherein i is 0, 2, 4, 6, 8, …, N-6, and N-4, and the weights of the capacitors are 3C, 12C, and 1C, respectively;
And 3, after the switching is finished, comparing the voltage of the capacitor top plate with the quantization threshold value generated in the first quantization period by using three external comparators respectively, so as to generate and output two groups of complementary three-position thermometer codes in the first quantization period, wherein the complementary outputs of the three external comparators are respectively CP2/CN2、CP1/CN1、CP0/CN0;
Step 4, in the second quantization period, aiming at the weight of (3 multiplied by 2)N-4)C、(1×2N-4)C、(4×2N-4)C、(4×2N-4) C, the capacitance switch corresponding to the capacitance is switched, and the capacitance switch module is controlled according to four possible situations of the three-bit thermometer code generated in the first quantization periodIn this embodiment, the capacitance weights are 12C, 4C, 16C, and 16C, respectively;
Step 4.1, as shown in the dashed box of FIG. 2c, if the three-digit thermometer code CP generated in step 42CP1CP0To "000", an output CP of the first external comparator is used2The weight in the positive end of the first capacitor array is controlled to be (3 multiplied by 2)N-4) The capacitor switch corresponding to the capacitor C has its bottom plate connected to the reference voltage terminal and the other output CN of the first external comparator2The weight of the negative terminal of the first capacitor array is controlled to be (3 multiplied by 2)N-4) The capacitor switch corresponding to the capacitor C has its bottom plate connected to ground, and the weight of the capacitor is 12C in this embodiment;
using a set of outputs CP of three comparators simultaneously2、CP1、CP0Respectively controlling the weight of the positive end of the second capacitor array to be (1 multiplied by 2)N-4)C、(4×2N-4)C、(4×2N-4) The capacitor switch corresponding to the capacitor C has its bottom plate connected to the reference voltage terminal and the other group of three comparators outputs CN2、CN1、CN0Respectively controlling the weight of the negative terminal of the second capacitor array to be (1 x 2)N-4)C、(4×2N-4)C、(4×2N-4) The bottom pole plate of the capacitor switch corresponding to the capacitor C is connected with the ground end; the connection state of the bottom plates of the other capacitors is kept unchanged, and the weights of the capacitors are respectively 4C, 16C and 16C in the embodiment;
Step 4.2, shown in the dashed box of FIG. 2d, if the three-digit thermometer code CP generated in step 4 is present2CP1CP0to "100", an output CP of the first external comparator is used2The weight in the positive end of the first capacitor array is controlled to be (1 multiplied by 2)N-4) The capacitor switch corresponding to the capacitor C has its bottom plate connected to ground and the other output CN of the first external comparator2The weight of the negative terminal of the first capacitor array is controlled to be (1 multiplied by 2)N-4) The capacitor switch corresponding to the capacitor of C has its bottom plate connected to the reference voltage terminal, and the weight of the capacitor is 4C in this embodiment;
Using the second and third external ratios simultaneouslya set of outputs CP of the comparator1、CP0Respectively controlling the weight of the positive end of the second capacitor array to be (1 multiplied by 2)N-4)C、(4×2N-4) The capacitor switch corresponding to the capacitor C has its bottom plate connected to the reference voltage terminal and the other group of the second and third external comparators outputs CN1、CN0Respectively controlling the weight of the negative terminal of the second capacitor array to be (1 x 2)N-4)C、(4×2N-4) The bottom pole plate of the capacitor switch corresponding to the capacitor C is connected with the ground end; the connection state of the bottom plates of the other capacitors is kept unchanged, and the weights of the capacitors are respectively 4C and 16C in the embodiment;
step 4.3, as shown in the dashed box of FIG. 2e, if the three-digit thermometer code CP generated in step 42CP1CP0To "110", a set of outputs CP of the first and second external comparators is used2、CP1respectively controlling the weight of the positive end of the first capacitor array to be (1 multiplied by 2)N-4)C、(4×2N-4) The capacitor switch corresponding to the capacitor C has its bottom plate connected to ground and the other group of the first and second external comparators outputs CN2、CN1Respectively controlling the weight of the negative terminal of the first capacitor array to be (1 x 2)N-4)C、(4×2N-4) The capacitor switch corresponding to the capacitor of C has its bottom plate connected to the reference voltage terminal, and the weights of the capacitors are 4C and 16C, respectively;
Using simultaneously an output CP of a third external comparator0The weight in the positive end of the second capacitor array is controlled to be (1 multiplied by 2)N -4) The capacitor switch corresponding to the capacitor C has its bottom plate connected to the reference voltage terminal and the other output CN of the third external comparator0the weight of the negative terminal of the second capacitor array is controlled to be (1 multiplied by 2)N-4) The bottom pole plate of the capacitor switch corresponding to the capacitor C is connected with the ground end; the connection state of the bottom plates of the other capacitors is kept unchanged, and the weight of the capacitor is 4C in the embodiment;
step 4.4, as shown in the dashed box of FIG. 2f, if the three-digit thermometer code CP generated in step 4 is present2CP1CP0to "111", one of three external comparators is usedgroup output CP2、CP1、CP0Respectively controlling the weight of the positive end of the first capacitor array to be (1 multiplied by 2)N-4)C、(4×2N-4)C、(4×2N-4) The capacitor switch corresponding to the capacitor C has its bottom plate connected to ground and the other group of three external comparators outputs CN2、CN1、CN0Respectively controlling the weight of the negative terminal of the first capacitor array to be (1 x 2)N-4)C、(4×2N-4)C、(4×2N-4) The capacitor switch corresponding to the capacitor of C has its bottom plate connected to the reference voltage terminal, and the weights of the capacitors are 4C, 16C, and 16C, respectively;
Using simultaneously an output CP of a third external comparator0the weight in the positive end of the second capacitor array is controlled to be (3 multiplied by 2)N -4) The bottom plate of the capacitor switch corresponding to the capacitor C is connected with the ground end, and the other output CN of the third external comparator is used0the weight of the negative terminal of the second capacitor array is controlled to be (3 multiplied by 2)N-4) C, the capacitor switch corresponding to the capacitor makes the bottom plate connected with the reference voltage end; the connection state of the bottom plates of the other capacitors is kept unchanged, and the weight of the capacitor is 12C in the embodiment;
Step 5, after the switching is finished, comparing the voltage of the capacitor top plate with a quantization threshold value generated in a second quantization period by using three external comparators respectively, so as to generate and output two groups of complementary three-position thermometer codes in the second quantization period;
Step 6, in the third quantization period and each subsequent quantization period, the relationship between the capacitor switch performing the switching operation and the capacitor switch performing the switching operation in the previous quantization period is as follows: the weights of the capacitances corresponding to the capacitance switches performing the switching operation in the current quantization period are all 1/4 of the weights of the capacitances corresponding to the capacitance switches performing the switching operation in the previous quantization period, that is, the weights are sequentially: (3X 2)N-6)C、(1×2N-6)C、(4×2N-6)C、(4×2N-6)C,(3×2N-8)C、(1×2N-8)C、(4×2N-8)C、(4×2N-8)C,(3×2N-10)C、(1×2N-10)C、(4×2N-10)C、(4×2N-10)C,…,(3×2N-j)C、(1×2N-j)C、(4×2N-j)C、(4×2N-j)C,…,(3×20)C、(1×20)C、(4×20)C、(4×20) C, wherein j is 6, 8, 10, 12, …, N-2, N; simultaneously keeping the connection state of the capacitance switches which are switched in all the quantization periods before the current quantization period unchanged; in this embodiment, the three-bit thermometer code CP is generated during the first and second quantization periods2CP1CP0When the values are all "000", the capacitance weights corresponding to the capacitance switches which need to be switched in the third quantization period are (3 × 2)N-6)C、(1×2N-6)C、(4×2N-6)C、(4×2N-6) C, i.e., 3C, 1C, 4C, as shown in the dashed box of fig. 3.
and then according to four possible situations of the generated three-position thermometer code in the previous quantization period, continuously controlling other capacitance switches in the capacitance switch module according to the modes from the step 4.1 to the step 4.4 until the switching operation of the capacitance switch in the Nth/2 th quantization period is completed.
Claims (2)
1. A capacitor array circuit of successive approximation ADC is characterized by comprising a capacitor array module and a capacitor switch module;
the capacitor array module comprises two capacitor arrays, namely a first capacitor array and a second capacitor array, wherein each capacitor array is composed of a positive end and a negative end, the two capacitor arrays are connected with three external comparators, the positive ends of the two capacitor arrays are respectively connected with the positive input ends of the first external comparator and the third external comparator, the negative ends of the two capacitor arrays are respectively connected with the negative input ends of the first external comparator and the third external comparator, the positive input end of the second external comparator is connected with the positive input end of the first external comparator, and the negative input end of the second comparator is connected with the negative input end of the third external comparator;
The capacitance switch module is composed of 4m capacitance switches, one end of each capacitance switch is a free end, the other end of each capacitance switch is a fixed end, wherein m is 2N-2, N is the resolution digit of the ADC and is an even number;
the positive end and the negative end of each capacitor array are respectively composed of m capacitors with weights, and the weights of the m capacitors are respectively (3 multiplied by 2)0)C、(1×20)C、(4×20)C、(4×20)C、(3×22)C、(1×22)C、(4×22)C、(4×22)C、…、(3×2i)C、(1×2i)C、(4×2i)C、(4×2i)C、…、(3×2N-6)C、(1×2N-6)C、(4×2N-6)C、(4×2N-6)C、(3×2N-4)C、(1×2N-4)C、(4×2N-4)C、(4×2N-4) C, 3C, 1C, wherein C is a unit capacitance, i ═ 0, 2, 4, 6, 8, …, N-6, N-4;
One ends of m capacitors in the positive end are connected with a positive input end of an external comparator and a common-mode voltage end, and the other ends of the m capacitors are correspondingly connected with fixed ends of m capacitor switches respectively;
One ends of m capacitors in the negative end are connected with the negative input end of the external comparator and the common-mode voltage end, and the other ends of the m capacitors are correspondingly connected with the fixed ends of the m capacitor switches respectively;
Taking a polar plate at one end of each capacitor connected with the external comparator as a top polar plate, and taking one end connected with the fixed end of the capacitor switch as a bottom polar plate;
The free ends of the capacitance switches corresponding to the capacitances with the weights of 3C and 1C are switched between the analog input signal end and the reference voltage end or switched between the analog input signal end and the ground end;
The free ends of the capacitance switches corresponding to the other m-2 capacitances are switched among the analog input signal end, the reference voltage end and the ground end;
Under the control of different digital output signals of an external comparator, the capacitance switch module switches the connection state of the free end of the corresponding capacitance switch, so that the bottom plate of the capacitor is connected to different voltages.
2. the method of claim 1, comprising the steps of:
Step 1, connecting bottom plates of all capacitors in a capacitor array module with an analog input signal end, connecting a top plate with a common mode voltage end, and completing sampling of analog input signals by the bottom plates of the capacitors;
step 2, in a first quantization period, firstly disconnecting the positive and negative ends of the two capacitor arrays from the common-mode voltage end, and carrying out switching operation aiming at all the capacitor switches, wherein the operation comprises the following steps: the weights in the positive terminals of the first capacitor array are respectively (1 multiplied by 2)0)C、(4×20)C、(4×20)C、(1×22)C、(4×22)C、(4×22)C、…、(1×2i)C、(4×2i)C、(4×2i)C、…、(1×2N-6)C、(4×2N-6)C、(4×2N-6)C、(1×2N-4)C、(4×2N-4)C、(4×2N-4) The bottom plates of the capacitors C and 3C are all connected with a reference voltage end, and the bottom plates of the other capacitors are all connected with a ground end, wherein i is 0, 2, 4, 6, 8, …, N-6 and N-4;
The weights of the negative terminals of the first capacitor array are (1 × 2)0)C、(4×20)C、(4×20)C、(1×22)C、(4×22)C、(4×22)C、…、(1×2i)C、(4×2i)C、(4×2i)C、…、(1×2N-6)C、(4×2N-6)C、(4×2N-6)C、(1×2N -4)C、(4×2N-4)C、(4×2N-4) The bottom plates of the capacitors C and 3C are all grounded, and the bottom plates of the other capacitors are all connected with a reference voltage end, wherein i is 0, 2, 4, 6, 8, …, N-6 and N-4;
The weights in the positive terminals of the second capacitor arrays are respectively (3 multiplied by 2)0)C、(3×22)C、…、(3×2i)C、…、(3×2N-6)C、(3×2N-4) The bottom plates of the capacitors C and 1C are all connected with a reference voltage end, and the bottom plates of the other capacitors are all connected with a ground end, wherein i is 0, 2, 4, 6, 8, …, N-6 and N-4;
The weights of the negative terminals of the second capacitor array are (3 x 2)0)C、(3×22)C、…、(3×2i)C、…、(3×2N-6)C、(3×2N-4) The bottom plates of the capacitors C and 1C are all grounded, and the bottom plates of the other capacitors are all connected with a reference voltage end, wherein i is 0, 2, 4, 6, 8, …, N-6 and N-4;
And 3, after the switching is finished, comparing the voltage of the capacitor top plate with the quantization threshold value generated in the first quantization period by using three external comparators respectively, so as to generate and output two groups of complementary three-position thermometer codes in the first quantization period, wherein the complementary outputs of the three external comparators are respectively CP2/CN2、CP1/CN1、CP0/CN0;
Step 4, in the second quantization period, aiming at the weight of (3 multiplied by 2)N-4)C、(1×2N-4)C、(4×2N-4)C、(4×2N-4) C, the capacitance switch corresponding to the capacitor is switched, and the capacitance switch module is controlled according to four possible situations of the generated three-position thermometer code in the first quantization period;
Step 4.1, if the three-digit thermometer code CP generated in step 42CP1CP0To "000", an output CP of the first external comparator is used2the weight in the positive end of the first capacitor array is controlled to be (3 multiplied by 2)N-4) The capacitor switch corresponding to the capacitor C has its bottom plate connected to the reference voltage terminal and the other output CN of the first external comparator2the weight of the negative terminal of the first capacitor array is controlled to be (3 multiplied by 2)N-4) The bottom pole plate of the capacitor switch corresponding to the capacitor C is connected with the ground end;
Using a set of outputs CP of three comparators simultaneously2、CP1、CP0Respectively controlling the weight of the positive end of the second capacitor array to be (1 multiplied by 2)N-4)C、(4×2N-4)C、(4×2N-4) The capacitor switch corresponding to the capacitor C has its bottom plate connected to the reference voltage terminal and the other group of three comparators outputs CN2、CN1、CN0Respectively controlling the weight of the negative terminal of the second capacitor array to be (1 x 2)N-4)C、(4×2N-4)C、(4×2N-4) The bottom pole plate of the capacitor switch corresponding to the capacitor C is connected with the ground end; and the connection state of the bottom plates of the other capacitors is kept unchanged;
step 4.2, if the three-digit thermometer code CP generated in step 42CP1CP0to "100", an output CP of the first external comparator is used2the weight in the positive end of the first capacitor array is controlled to be (1 multiplied by 2)N-4) The capacitor switch corresponding to the capacitor C has its bottom plate connected to ground and the other output CN of the first external comparator2the weight of the negative terminal of the first capacitor array is controlled to be (1 multiplied by 2)N-4) C, the capacitor switch corresponding to the capacitor makes the bottom plate connected with the reference voltage end;
Using a set of outputs CP of second and third external comparators simultaneously1、CP0Respectively controlling the weight of the positive end of the second capacitor array to be (1 multiplied by 2)N-4)C、(4×2N-4) The capacitor switch corresponding to the capacitor C has its bottom plate connected to the reference voltage terminal and the other group of the second and third external comparators outputs CN1、CN0respectively controlling the weight of the negative terminal of the second capacitor array to be (1 x 2)N-4)C、(4×2N-4) The bottom pole plate of the capacitor switch corresponding to the capacitor C is connected with the ground end; and the connection state of the bottom plates of the other capacitors is kept unchanged;
Step 4.3, if the three-digit thermometer code CP generated in step 42CP1CP0To "110", a set of outputs CP of the first and second external comparators is used2、CP1Respectively controlling the weight of the positive end of the first capacitor array to be (1 multiplied by 2)N-4)C、(4×2N-4) The capacitor switch corresponding to the capacitor C has its bottom plate connected to ground and the other group of the first and second external comparators outputs CN2、CN1Respectively controlling the weight of the negative terminal of the first capacitor array to be (1 x 2)N-4)C、(4×2N-4) C, the capacitor switch corresponding to the capacitor makes the bottom plate connected with the reference voltage end;
Using simultaneously an output CP of a third external comparator0controlling the second capacitor array positive terminalthe medium weight is (1 × 2)N-4) The capacitor switch corresponding to the capacitor C has its bottom plate connected to the reference voltage terminal and the other output CN of the third external comparator0the weight of the negative terminal of the second capacitor array is controlled to be (1 multiplied by 2)N-4) The bottom pole plate of the capacitor switch corresponding to the capacitor C is connected with the ground end; and the connection state of the bottom plates of the other capacitors is kept unchanged;
step 4.4, if the three-digit thermometer code CP generated in step 42CP1CP0To "111", a set of outputs CP of three external comparators is used2、CP1、CP0Respectively controlling the weight of the positive end of the first capacitor array to be (1 multiplied by 2)N-4)C、(4×2N-4)C、(4×2N-4) The capacitor switch corresponding to the capacitor C has its bottom plate connected to ground and the other group of three external comparators outputs CN2、CN1、CN0respectively controlling the weight of the negative terminal of the first capacitor array to be (1 x 2)N-4)C、(4×2N-4)C、(4×2N-4) C, the capacitor switch corresponding to the capacitor makes the bottom plate connected with the reference voltage end;
Using simultaneously an output CP of a third external comparator0The weight in the positive end of the second capacitor array is controlled to be (3 multiplied by 2)N-4) The bottom plate of the capacitor switch corresponding to the capacitor C is connected with the ground end, and the other output CN of the third external comparator is used0the weight of the negative terminal of the second capacitor array is controlled to be (3 multiplied by 2)N-4) C, the capacitor switch corresponding to the capacitor makes the bottom plate connected with the reference voltage end; and the connection state of the bottom plates of the other capacitors is kept unchanged;
Step 5, after the switching is finished, comparing the voltage of the capacitor top plate with a quantization threshold value generated in a second quantization period by using three external comparators respectively, so as to generate and output two groups of complementary three-position thermometer codes in the second quantization period;
Step 6, in the third quantization period and each subsequent quantization period, the relationship between the capacitor switch performing the switching operation and the capacitor switch performing the switching operation in the previous quantization period is as follows: the weight of the capacitor corresponding to the capacitor switch which is switched in the current quantization period is 1/4 of the weight of the capacitor corresponding to the capacitor switch which is switched in the previous quantization period, and the connection state of the capacitor switches which are switched in all quantization periods before the current quantization period is kept unchanged;
and then according to four possible situations of the generated three-position thermometer code in the previous quantization period, continuously controlling other capacitance switches in the capacitance switch module according to the modes from the step 4.1 to the step 4.4 until the switching operation of the capacitance switch in the Nth/2 th quantization period is completed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201910984729.XA CN110572158B (en) | 2019-10-16 | 2019-10-16 | Successive approximation ADC (analog to digital converter) capacitor array circuit and capacitor switch control method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201910984729.XA CN110572158B (en) | 2019-10-16 | 2019-10-16 | Successive approximation ADC (analog to digital converter) capacitor array circuit and capacitor switch control method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
CN110572158A true CN110572158A (en) | 2019-12-13 |
CN110572158B CN110572158B (en) | 2022-08-30 |
Family
ID=68785242
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201910984729.XA Active CN110572158B (en) | 2019-10-16 | 2019-10-16 | Successive approximation ADC (analog to digital converter) capacitor array circuit and capacitor switch control method thereof |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN110572158B (en) |
Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120326900A1 (en) * | 2011-06-24 | 2012-12-27 | Mediatek Inc. | Successive approximation register analog to digital converter and conversion method thereof |
US20130076554A1 (en) * | 2011-09-22 | 2013-03-28 | Himax Technologies Limited | Successive approximation analog to digital converter |
US20140097975A1 (en) * | 2012-10-05 | 2014-04-10 | National Chiao Tung University | Method for estimating capacitance weight errors and successive approximation analog to digital converter using the same |
CN104467856A (en) * | 2014-11-21 | 2015-03-25 | 华南理工大学 | High-energy-efficiency capacitor array successive approximation type analog-digital converter and converting method thereof |
WO2015154671A1 (en) * | 2014-04-09 | 2015-10-15 | 华为技术有限公司 | Self-calibration method and device for pipeline successive approximation type analogue to digital convertor |
CN105187067A (en) * | 2015-09-28 | 2015-12-23 | 中国电子科技集团公司第三十八研究所 | Capacitor array type digital to analog converter circuit of high-speed successive approximation type analog to digital converter |
CN105391451A (en) * | 2015-11-30 | 2016-03-09 | 江苏芯力特电子科技有限公司 | Successive approximation register analog to digital converter (SAR ADC) and switching method during analog-digital conversion thereof |
WO2016127824A1 (en) * | 2015-02-10 | 2016-08-18 | 东南大学 | Binary capacitor array applied to single-terminal sar adc and redundancy calibrating method therefor |
CN106209102A (en) * | 2016-06-27 | 2016-12-07 | 合肥工业大学 | Mixed type two-layer configuration for full parellel successive approximation analog-digital converter |
US20170331486A1 (en) * | 2015-05-19 | 2017-11-16 | China Electronic Technology Corporation, 24Th Research Institute | High-Speed Successive Approximation Analog-to-Digital Converter of Two Bits per Circle |
US20180091163A1 (en) * | 2016-09-23 | 2018-03-29 | Shenzhen Goodix Technology Co. , Ltd. | Dac capacitor array, sar analog-to-digital converter and method for reducing power consumption thereof |
CN108055037A (en) * | 2017-12-27 | 2018-05-18 | 湘潭芯力特电子科技有限公司 | A kind of gradual approaching A/D converter and its Switching method |
-
2019
- 2019-10-16 CN CN201910984729.XA patent/CN110572158B/en active Active
Patent Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120326900A1 (en) * | 2011-06-24 | 2012-12-27 | Mediatek Inc. | Successive approximation register analog to digital converter and conversion method thereof |
US20130076554A1 (en) * | 2011-09-22 | 2013-03-28 | Himax Technologies Limited | Successive approximation analog to digital converter |
US20140097975A1 (en) * | 2012-10-05 | 2014-04-10 | National Chiao Tung University | Method for estimating capacitance weight errors and successive approximation analog to digital converter using the same |
WO2015154671A1 (en) * | 2014-04-09 | 2015-10-15 | 华为技术有限公司 | Self-calibration method and device for pipeline successive approximation type analogue to digital convertor |
CN104467856A (en) * | 2014-11-21 | 2015-03-25 | 华南理工大学 | High-energy-efficiency capacitor array successive approximation type analog-digital converter and converting method thereof |
WO2016127824A1 (en) * | 2015-02-10 | 2016-08-18 | 东南大学 | Binary capacitor array applied to single-terminal sar adc and redundancy calibrating method therefor |
US20170331486A1 (en) * | 2015-05-19 | 2017-11-16 | China Electronic Technology Corporation, 24Th Research Institute | High-Speed Successive Approximation Analog-to-Digital Converter of Two Bits per Circle |
CN105187067A (en) * | 2015-09-28 | 2015-12-23 | 中国电子科技集团公司第三十八研究所 | Capacitor array type digital to analog converter circuit of high-speed successive approximation type analog to digital converter |
CN105391451A (en) * | 2015-11-30 | 2016-03-09 | 江苏芯力特电子科技有限公司 | Successive approximation register analog to digital converter (SAR ADC) and switching method during analog-digital conversion thereof |
CN106209102A (en) * | 2016-06-27 | 2016-12-07 | 合肥工业大学 | Mixed type two-layer configuration for full parellel successive approximation analog-digital converter |
US20180091163A1 (en) * | 2016-09-23 | 2018-03-29 | Shenzhen Goodix Technology Co. , Ltd. | Dac capacitor array, sar analog-to-digital converter and method for reducing power consumption thereof |
CN108055037A (en) * | 2017-12-27 | 2018-05-18 | 湘潭芯力特电子科技有限公司 | A kind of gradual approaching A/D converter and its Switching method |
Non-Patent Citations (5)
Title |
---|
HONGHUI DENG等: ""A 8-bit 10MS/s asynchronous SAR ADC with resistor-capacitor array DAC"", 《2014 INTERNATIONAL CONFERENCE ON ANTI-COUNTERFEITING, SECURITY AND IDENTIFICATION (ASID)》 * |
HONGYI WANG等: ""Low power consumption and low area capacitor array for 16-bit 1-MS/s SAR ADC"", 《2018 IEEE 3RD ADVANCED INFORMATION TECHNOLOGY, ELECTRONIC AND AUTOMATION CONTROL CONFERENCE (IAEAC)》 * |
WEI TUNG等: ""An Energy-Efficient 11-bit 10-MS/s SAR ADC with Monotonie Switching Split Capacitor Array"", 《2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)》 * |
王克柔等: ""一款12位5 kS/s逐次逼近型模数转换器的设计"", 《固体电子学研究与进展》 * |
邓红辉等: ""一种基于65 nm CMOS工艺的10位10 MS/s SAR ADC"", 《微电子学》 * |
Also Published As
Publication number | Publication date |
---|---|
CN110572158B (en) | 2022-08-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN109039332B (en) | Successive approximation type analog-to-digital converter and low-power-consumption switching algorithm thereof | |
CN105391451A (en) | Successive approximation register analog to digital converter (SAR ADC) and switching method during analog-digital conversion thereof | |
CN111371457B (en) | Analog-to-digital converter and three-level switching method applied to SAR ADC | |
CN108306644B (en) | Front-end circuit based on 10-bit ultra-low power consumption successive approximation type analog-to-digital converter | |
CN104967451A (en) | Successive approximation type analog-to-digital converter | |
CN110380730B (en) | Capacitor array switching method applied to low-voltage SAR ADC | |
CN112367084B (en) | Successive approximation type analog-to-digital converter quantization method based on terminal capacitance multiplexing | |
CN110190854B (en) | Two-step SAR ADC-oriented shared reference voltage realization circuit and method | |
CN105049049A (en) | Capacitor exchange method for improving DNL (Differential Nonlinearity)/INL (Integral Nonlinearity) of successive approximation analog to digital converter | |
CN108880553B (en) | Low-power-consumption self-adaptive alternative successive approximation type analog-to-digital converter and control method | |
CN111641413B (en) | Capacitor array switching method of high-energy-efficiency SAR ADC | |
CN111756380A (en) | Two-step successive approximation type analog-to-digital converter sharing bridge capacitor array | |
CN112583409A (en) | Successive approximation type analog-to-digital converter and three-level switching method thereof | |
CN212435677U (en) | Novel one-way switch switching circuit for SAR ADC capacitor array | |
CN107395205B (en) | Successive approximation type analog-digital converter based on asymmetric differential capacitor array | |
CN112272027A (en) | Successive approximation analog-digital converter and capacitance switch switching method | |
CN110572158B (en) | Successive approximation ADC (analog to digital converter) capacitor array circuit and capacitor switch control method thereof | |
CN111585577A (en) | Capacitor array switching method for successive approximation type analog-to-digital converter | |
CN109450449B (en) | Reference voltage control circuit and analog-to-digital converter | |
CN113612480B (en) | Successive approximation type analog-to-digital converter based on segmented differential capacitor array | |
CN112968704B (en) | Successive approximation type analog-to-digital converter quantization method based on transient capacitance switching mode | |
CN113014263B (en) | Capacitor array and switch logic circuit of successive approximation type ADC | |
CN109039338B (en) | Differential capacitor array and switch switching method thereof | |
CN109936370B (en) | Low-power-consumption switching algorithm applied to SAR ADC | |
CN109802679B (en) | Ultra-low power consumption successive approximation analog-to-digital converter based on power supply voltage |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |