CN111585577A - Capacitor array switching method for successive approximation type analog-to-digital converter - Google Patents

Capacitor array switching method for successive approximation type analog-to-digital converter Download PDF

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CN111585577A
CN111585577A CN202010626144.3A CN202010626144A CN111585577A CN 111585577 A CN111585577 A CN 111585577A CN 202010626144 A CN202010626144 A CN 202010626144A CN 111585577 A CN111585577 A CN 111585577A
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capacitor
bit
comparator
weighted
phase input
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李泽宏
杨耀杰
王其鹤
胡任任
蔡景宜
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University of Electronic Science and Technology of China
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    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type

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Abstract

A capacitor array switching method for a successive approximation type analog-to-digital converter belongs to the technical field of electronic circuits. The weighted capacitor array in the successive approximation type analog-to-digital converter comprises a one-bit positive phase end redundant capacitor, a one-bit reverse phase end redundant capacitor, an N-2-bit positive phase end weighted capacitor and an N-2-bit reverse phase end weighted capacitor, each bit weighted capacitor is divided into two divided weighted capacitors with equal capacitance values, the redundant capacitors are added into charge redistribution operation, a monotonous switching mode is used on the redundant capacitors, and the N-bit conversion precision only needs 2N‑1Compared with a common-mode level VCM-based switching scheme, the unit capacitor saves half of the capacitor, and saves the circuit area and the cost; meanwhile, the invention basically reserves the characteristic that the common mode level of the comparator in the common mode level VCM-based switching scheme is not changed, and the common mode level has the common mode level only in the last comparison

Description

Capacitor array switching method for successive approximation type analog-to-digital converter
Technical Field
The invention belongs to the technical field of electronic circuits, and particularly relates to a capacitor array switching method for a successive approximation type analog-to-digital converter.
Background
An analog-to-digital converter (ADC) is one of the core modules of various electronic terminal devices, and realizes the conversion from an analog signal to a digital signal. Among analog-to-digital converters with various structures, a successive approximation analog-to-digital converter (SAR ADC) is very suitable for low-power consumption application due to simple structure and few analog modules. The capacitor array type SAR ADC realizes a successive approximation algorithm according to a charge redistribution principle, the used capacitor array is multiplied along with the increase of the number of bits of the ADC, and for the ADC with higher conversion precision, the capacitor array consumes a large amount of layout area and increases the circuit cost.
In the current commonly used switching scheme, the monotone structure switching scheme needs 2 capacitor arrays to realize N bit conversion precisionNThe unit capacitors, and in the conversion process, the common mode level changes greatly, so that the design requirement on the comparator is high; common mode level VCMThe base switching scheme, while keeping the comparator common mode level stable, also consumes 2NUnit capacitance.
Disclosure of Invention
Aiming at the large change of the common mode level and the common mode level V in the traditional monotone structure switch schemeCMThe disadvantage of large capacitance area consumption of the base switching scheme is that the invention provides a capacitor array switching method for a successive approximation analog-to-digital converter, and the switching scheme can enable the common mode level to have the effect only when the LSB of the lowest bit is compared
Figure BDA0002566592530000011
And the ADC of N-bit resolution only needs to consume 2N-1The unit capacitor is suitable for application with higher resolution, and can greatly save circuit area and reduce cost.
The technical scheme adopted by the invention is as follows:
a capacitor array switching method for a successive approximation type analog-to-digital converter comprises a positive phase input signal switch, an inverse phase input signal switch, a weighted capacitor array, a comparator and a successive approximation logic control module, wherein a positive phase input voltage is connected with a positive phase input end of the comparator through the positive phase input signal switch, and an inverse phase input voltage is connected with an inverse phase input end of the comparator through the inverse phase input signal switch;
the weighted capacitor array comprises a normal phase weighted capacitor array and an inverse phase weighted capacitor array, the normal phase weighted capacitor array comprises a normal phase end redundant capacitor and an N-2 bit normal phase end weighted capacitor, the inverse phase weighted capacitor array comprises an inverse phase end redundant capacitor and an N-2 bit inverse phase end weighted capacitor, and the capacitance values of the N-i bit normal phase end weighted capacitor and the N-i bit inverse phase end weighted capacitor are 2N-1-iC, wherein C is a unit capacitance value, N is the conversion precision of the successive approximation type analog-to-digital converter, i is a positive integer and i ∈ [2, N-1 ]]；
Splitting each weighted capacitor of the N-2 bit positive phase end weighted capacitor and the N-2 bit negative phase end weighted capacitor into two split weighted capacitors with equal capacitance values, wherein the capacitance value of the split weighted capacitor corresponding to the split weighted capacitor after the N-i bit positive phase end weighted capacitor and the N-i bit negative phase end weighted capacitor are split is 2N-1-iC；
The upper polar plate of each split weighted capacitor in the normal phase weighted capacitor array is connected with the normal phase input end of the comparator, and the lower polar plate of the split weighted capacitor array is connected with a reference level or a ground level after passing through a switch; the upper polar plate of each split weighting capacitor in the inverse weighting capacitor array is connected with the inverse input end of the comparator, and the lower polar plate of each split weighting capacitor in the inverse weighting capacitor array is connected with a reference level or a ground level after passing through a switch;
the upper polar plate of the positive phase end redundant capacitor is connected with the positive phase input end of the comparator, and the lower polar plate of the positive phase end redundant capacitor is connected with a common mode level or a ground level after passing through a switch; the upper pole plate of the inverted terminal redundant capacitor is connected with the inverted terminal of the comparator, and the lower pole plate of the inverted terminal redundant capacitor is connected with a common mode level or a ground level after passing through a switch;
the output signal of the comparator passes through the successive approximation logic control module and then generates a control signal for controlling the switch in the weighted capacitor array;
the capacitor array switching method comprises the following steps:
step one, a sampling stage;
connecting the lower polar plates of the positive-phase end redundant capacitor and the negative-phase end redundant capacitor with the common mode level;
in the two split weighted capacitors corresponding to each bit positive phase end weighted capacitor and each bit negative phase end weighted capacitor, the lower pole plate of one split weighted capacitor is connected with a reference level, and the lower pole plate of the other split weighted capacitor is connected with a ground level;
closing the normal phase input signal switch and the reverse phase input signal switch to enable the normal phase input voltage to be connected to the normal phase input end of the comparator, the reverse phase input voltage to be connected to the reverse phase input end of the comparator, and the successive approximation type analog-to-digital converter performs sampling;
disconnecting the input signal switch at the positive phase end and the input signal switch at the negative phase end after sampling is finished;
step two, comparing;
sequentially determining the highest-order output code to the lowest-order output code of the successive approximation type analog-to-digital converter through N times of comparison, and obtaining the N-order output code of the successive approximation type analog-to-digital converter to complete analog-to-digital conversion, wherein the highest-order output code of the successive approximation type analog-to-digital converter is the first-order output code, and the lowest-order output code of the successive approximation type analog-to-digital converter is the Nth-order output code;
the specific method for making the jth comparison is as follows, j ∈ [1, N-2 ]:
comparing the signal of the positive phase input end of the comparator with the signal of the negative phase input end of the comparator, wherein when the signal of the positive phase input end of the comparator is greater than the signal of the negative phase input end of the comparator, the j-th bit output code of the successive approximation type analog-to-digital converter is 1, the lower pole plates of two splitting weighting capacitors corresponding to the N-j-1-th bit positive phase end weighting capacitor are both connected with a ground level, and the lower pole plates of two splitting weighting capacitors corresponding to the N-j-1-th bit negative phase end weighting capacitor are both connected with a reference level;
when the signal of the positive phase input end of the comparator is smaller than the signal of the negative phase input end of the comparator, the j bit output code of the successive approximation type analog-to-digital converter is 0, the lower pole plates of the two splitting weighting capacitors corresponding to the N-j-1 bit positive phase end weighting capacitor are both connected with a reference level, and the lower pole plates of the two splitting weighting capacitors corresponding to the N-j-1 bit negative phase end weighting capacitor are both connected with a ground level;
when the comparison is carried out for the (N-1) th time, comparing the signal of the positive phase input end of the comparator with the signal of the negative phase input end of the comparator, when the signal of the positive phase input end of the comparator is greater than the signal of the negative phase input end of the comparator, the output code of the (N-1) th bit of the successive approximation type analog-to-digital converter is 1, and connecting the lower polar plate of the redundant capacitor of the positive phase end with the ground level; when the signal of the positive phase input end of the comparator is smaller than the signal of the negative phase input end of the comparator, the output code of the N-1 bit of the successive approximation type analog-to-digital converter is 0, and the lower electrode plate of the negative phase end redundant capacitor is connected with the ground level;
and when the signal of the positive phase input end of the comparator is smaller than the signal of the reverse phase input end of the comparator, the Nth bit output code of the successive approximation type analog-to-digital converter is 0.
Specifically, the split weighting capacitor corresponding to the 1 st-phase positive phase end weighting capacitor is formed by connecting two unit capacitors with capacitance values of unit capacitance value C in series.
The invention has the beneficial effects that: the switch method provided by the invention adds the redundant capacitor in the weighted capacitor array into the operation of charge redistribution, and uses a monotonous switch mode on the redundant capacitor to connect the ground level Gnd or the common mode level VCMSo that only 2 is needed to realize the N-bit conversion precisionN-1Unit capacitance, with a conventional common mode level VCMCompared with a base switching mode, half of capacitance is saved, and circuit area and cost are saved; meanwhile, the invention basically reserves the characteristic that the common mode level of the comparator in the common mode level VCM-based switching scheme is not changed, and the common mode level can be changed only by the last comparison
Figure BDA0002566592530000031
Variations in
Figure BDA0002566592530000032
The problem of the design requirement of great contrast comparator of common mode level change is high is solved.
Drawings
FIG. 1 is a common mode level VCM-circuit architecture diagram of SAR ADC in base switching scheme.
Fig. 2 is a schematic diagram of a split capacitor array switching scheme in a capacitor array switching method for a successive approximation analog-to-digital converter according to the present invention.
Fig. 3 is a circuit structure diagram of a four-bit SAR ADC designed by applying the capacitor array switching method for a successive approximation type analog-to-digital converter according to the present invention.
Fig. 4 is a sampling conversion voltage waveform diagram of a four-bit SAR ADC designed by applying the capacitor array switching method for a successive approximation type analog-to-digital converter according to the present invention.
Fig. 5 is a conversion process diagram of a capacitor array DAC in a four-bit SAR ADC using a capacitor array switching method for a successive approximation type analog-to-digital converter according to the present invention.
Detailed Description
The technical solution of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.
Shown in FIG. 1 is a common mode level VCMCircuit schematic of a based switching scheme, fig. 2 is a schematic of a split capacitor array switching scheme according to the present invention, and it can be seen that the common mode level V in fig. 1 is referred toCMIn the switching scheme shown in fig. 1, the weighted capacitor array comprises a 4-bit positive phase end weighted potential and a 4-bit negative phase end weighted capacitor, and 2 bits of conversion precision is required for realizing 4 bits of conversion precision4Unit capacitance. The novel switching method provided by the invention adds the redundant capacitor into the operation of charge redistributionThe redundancy capacitor is connected with the ground level Gnd or the common mode level V through a switch in a monotonous switching modeCMTherefore, the switching method of the invention only needs 2-bit positive phase end weighted potential, 2-bit negative phase end weighted capacitance, one-bit positive phase end redundant capacitance and one-bit negative phase end redundant capacitance to realize 4-bit resolution, and only 2-bit positive phase end weighted potential, 2-bit negative phase end weighted capacitance, one-bit positive phase end redundant capacitance and one-bit negative phase end redundant capacitance are needed to realize 4-bit resolution3And half of the capacitance is saved by the unit capacitance. And the common mode level changes only in the last comparison during the conversion period
Figure BDA0002566592530000041
Substantially retaining the common mode level VCMThe characteristic that the common mode level is not changed in the switching period of the base switching scheme.
The successive approximation analog-to-digital converter applicable to the switching method of the present invention is described below by taking a 4-bit successive approximation analog-to-digital converter SAR ADC as an example, and it is worth to be noted that the capacitance switch switching method of the present invention is not limited to be used in a four-bit SAR ADC circuit, and the capacitance switch switching method of the present invention can be used according to the needs of designers, for example, in other-bit SAR ADC circuits such as 8-bit SAR ADC circuits and 10-bit SAR ADC circuits, and the advantage of saving the capacitance area of the present invention is more obvious as the number of bits is larger.
As shown in FIG. 3, the 4-bit successive approximation type analog-to-digital converter includes a weighted capacitor array, a comparator and a successive approximation LOGIC control module (SAR LOGIC), and the positive phase input voltage VipBy inputting signal switch S at positive phase terminalw1A positive phase input terminal connected to the comparator and a negative phase input voltage VinBy inputting signal switches S at inverting terminalsw2The inverting input terminal of the comparator is connected.
The weighted capacitor array comprises a positive phase weighted capacitor array and a negative phase weighted capacitor array, wherein the positive phase weighted capacitor array comprises a positive phase end redundant capacitor C0pAnd 2 bit positive phase end weighting capacitors, each bit positive phase end weighting capacitor is divided into two division weighting capacitors with capacitance value being one half of that of the original weighting capacitor, and the two division weighting capacitors of the first bit positive phase end weighting capacitor are C1paAnd C1pbTwo split weighted capacitors of the second normal phase end weighted capacitor are C2paAnd C2pb. The inverse weighted capacitor array comprises an inverse end redundant capacitor C0nAnd two-bit inversion end weighting capacitors, wherein two split weighting capacitors of the first inversion end weighting capacitor are C1naAnd C1nbTwo split weighting capacitors of the second bit inverting terminal weighting capacitor are C2naAnd C2nb。
Inverting terminal redundant capacitor C0nAnd positive phase end redundant capacitor C0pThe capacitance value of (C) is the unit capacitance C. The capacitance of the first bit positive phase end weighting capacitor is the unit capacitor C, so the two split weighting capacitors C of the first bit positive phase end weighting capacitor1paAnd C1pbThe capacitance value of (2) is 0.5C, and the capacitance value of 0.5C can be obtained by connecting two unit capacitors with the capacitance value of C in series. Two split weighted capacitors C of the second normal phase end weighted capacitor2paAnd C2pbThe capacitance value of the capacitor is C. Similarly, two split weighting capacitors C of the first bit inverting terminal weighting capacitor1naAnd C1nbThe capacitance value of the first bit inverting terminal is 0.5C, and two split weighting capacitors C of the second bit inverting terminal weighting capacitor2na、C2nbThe capacitance value of the capacitor is C. Two split weighted capacitors C after splitting1paAnd C1pb、C2paAnd C2pbThe two equivalent capacitors are connected in parallel after being split corresponding to the first bit-weighted capacitor C1 and the second bit-weighted capacitor C2, so that C1pa、C1pbThe first bit positive phase end weighted capacitance and C1na、C1nbThe first bit inversion end weighted capacitance values are all C, C2pa、C2pbSecond bit positive phase terminal weighted capacitance and C2na、C2nbAnd the formed weighted capacitance values of the second bit inverting terminals are all 2C, and the two capacitors together form a binary capacitor array.
Normal phase input signal switch Sw1And inverting terminal input signal switch Sw2Controlling a positive phase input voltage VipAnd an inverted input voltage VinConnection to a comparator. Positive phase end redundant capacitance switch S0pAnd inverting terminal redundant capacitance switch S0nIs a two-way switch, and controls the redundant capacitor C at the positive phase end0pAnd an inverting terminal redundant capacitor C0nLower pole plate connectionCommon mode level VcmOr ground level Gnd. Switch S1paAnd S1pbTwo split weighting capacitors C for controlling the first bit normal phase end weighting capacitor as an alternative switch1paAnd C1pbThe lower polar plate is connected with a reference level VrefOr ground level Gnd. Switch S1naAnd S1nbTwo split weighting capacitors C for controlling the first bit inverting terminal weighting capacitor as an alternative switch1naAnd C1nbThe lower polar plate is connected with a reference level VrefOr ground level Gnd. Switch S2paAnd S2pbTwo split weighting capacitors C for controlling the second bit/positive phase end weighting capacitor as an alternative switch2paAnd C2pbThe lower polar plate is connected with a reference level VrefOr ground level Gnd. Switch S2naAnd S2nbTwo split weighting capacitors C for controlling the weighting capacitor of the second bit inverting terminal as an alternative switch2naAnd C2nbThe lower polar plate is connected with a reference level VrefOr ground level Gnd.
And the successive approximation LOGIC control module SAR LOGIC generates a control signal according to the output signal of the comparator, and the control signal is used for controlling each switch in the weighted capacitor array.
The working process of the four-bit SAR ADC using the switching method of the present invention is described in detail below, and fig. 5 is a diagram of a conversion process of the capacitor array DAC in the four-bit SAR ADC using the switching method of the present invention.
FIG. 1 of FIG. 5 (a) shows the sampling phase of the SAR ADC with the redundant capacitor C at the inverting terminaln0And positive phase end redundant capacitor Cp0Connected to a common mode level V by switchescmOne split weighting capacitor C of the two split weighting capacitors corresponding to the first positive phase end weighting capacitor1paConnected to a reference level V by means of a gating switchrefAnd another split weighting capacitor C1pbConnected to ground Gnd through the gate switch. One split weighting capacitor C of the two split weighting capacitors corresponding to the first bit inverting terminal weighting capacitor1naConnected to a reference level V by means of a gating switchrefAnd another split weighting capacitor C1nbConnected to ground Gnd through the gate switch. Second positive phaseOne split weighting capacitor C of two split weighting capacitors corresponding to the end weighting capacitor2paConnected to a reference level V by means of a gating switchrefAnd another split weighting capacitor C2pbConnected to ground Gnd through the gate switch. One split weighting capacitor C in two split weighting capacitors corresponding to the second bit inverting terminal weighting capacitor2naConnected to a reference level V by means of a gating switchrefAnd another split weighting capacitor C2nbConnected to ground Gnd through the gate switch. Normal phase input signal switch Sw1And inverting terminal input signal switch Sw2Connected, the positive phase input end of the comparator is connected with the positive phase input signal VipThe inverting input terminal of the comparator is connected with the inverting input signal VinAnd the SAR ADC performs sampling.
After the sampling is completed, as shown in fig. 5 (a) and fig. 2 (b), the non-inverting input signal switch Sw1And inverting terminal input signal switch Sw2Disconnecting the voltage at the positive input end of the comparator
Figure BDA0002566592530000061
The voltage at the inverting input of the comparator is
Figure BDA0002566592530000062
A first comparison is started.
When the first comparison is made, the comparator judges VipWhether or not it is greater than Vin。
If Vip＞VinIf the output of the comparator is "1", the most significant bit of the SAR ADC outputs the code D0Setting the value as 1, and then controlling the switch in the weighted capacitor array according to the output of the comparator, as shown in (1) of (b) in fig. 5, the output of the comparator is fed back to the weighted capacitor array through the successive approximation logic control module, and the gating switch of the most significant MSB weighted capacitor is changed, and this embodiment includes a 2-bit weighted capacitor, so that the split weighted capacitor C connected to the ground level Gnd corresponding to the weighted capacitor at the second bit inverting terminal is used here2nbConnected to a reference level VrefSo that the two split weighted circuits corresponding to the weighted capacitor at the inverting terminal of the second bitContainer C2na、C2nbAre all connected to a reference level Vref(ii) a Simultaneously correspondingly connecting the weighted capacitor at the positive phase end of the second bit to the reference level VrefThe split weighting capacitor C of2paTwo split weighting capacitors C connected to ground level Gnd for making the second bit positive phase terminal weighting capacitor correspond to2paAnd C2pbAre connected to ground level Gnd.
If Vip＜VinIf the output of the comparator is '0', the most significant bit of the SAR ADC outputs the code D0Setting the output value to 0, and controlling the switch in the weighted capacitor array according to the output of the comparator, as shown in (b) and (2) in fig. 5, the output of the comparator is fed back to the weighted capacitor array through the successive approximation logic control module, the gating switch of the MSB capacitor at the highest bit is changed, and the connection reference level V corresponding to the weighted capacitor at the second bit inverting terminal is connectedrefThe split weighting capacitor C of2naTwo split weighting capacitors C connected to ground level Gnd for making the second bit inverting terminal weighting capacitor correspond to2na、C2nbAre both connected to ground level Gnd; the split weighting capacitor C corresponding to the second bit positive phase end weighting capacitor and connected to the ground level Gnd2pbConnected to a reference level VrefSo that the two split weighting capacitors C corresponding to the second positive phase end weighting capacitor2paAnd C2pbAre all connected to a reference level Vref。
A second comparison is then made. If it is compared for the first time Vip＞Vin(D01), the voltage at the positive input terminal of the comparator becomes
Figure BDA0002566592530000063
Voltage at inverting input terminal becomes
Figure BDA0002566592530000064
Second comparison and judgment Vip-VinWhether or not greater than
Figure BDA0002566592530000065
If it is compared for the first time Vip＜Vin(D0＝0)Then the voltage at the positive input terminal of the comparator becomes
Figure BDA0002566592530000066
Voltage at inverting input terminal becomes
Figure BDA0002566592530000067
Second comparison and judgment Vip-VinWhether or not greater than
Figure BDA0002566592530000071
If it is
Figure BDA0002566592530000072
Or
Figure BDA0002566592530000073
The comparator output is '1', and the second bit output code D output by the SAR ADC1Setting as 1, as shown in fig. 5(C) and (2), the feedback signal of the successive approximation logic control module is fed back to the weighted capacitor array, the gating switch of the second high-order weighted capacitor (i.e. the first-order weighted capacitor) is changed, and the split weighted capacitor C connected to the ground level Gnd corresponding to the first-order inverting-end weighted capacitor is used1nbConnected to a reference level VrefSo that the two split weighting capacitors C corresponding to the first bit inverting terminal weighting capacitor1na、C1nbAre all connected to a reference level Vref(ii) a Connecting reference level V corresponding to the first bit positive phase end weighting capacitorrefThe split weighting capacitor C of1paTwo split weighting capacitors C connected to ground level Gnd for making the first bit positive phase end weighting capacitor correspond to1pa、C1pbAre connected to ground level Gnd.
If it is
Figure BDA0002566592530000074
Or
Figure BDA0002566592530000075
The comparator output is '0', and the second bit output code D output by the SAR ADC1Set to 0, and at the same time, as shown in (3) and (4) of fig. 5(c), the feedback signal of the successive approximation logic control module connects the reference level V corresponding to the first bit inverting terminal weighting capacitorrefThe split weighting capacitor C of1naTwo split weighting capacitors C connected to ground level Gnd to make the first bit inverting terminal weighting capacitor correspond to1na、C1nbAre both connected to ground level Gnd; the split weighting capacitor C connected with the ground level Gnd corresponding to the first bit positive phase end weighting capacitor1pbConnected to a reference level VrefSo that the two split weighting capacitors C corresponding to the first bit positive phase end weighting capacitor1pa、C1pbAre all connected to a reference level Vref。
A third comparison is then made. The second comparison is if
Figure BDA0002566592530000076
At this time, the voltage at the positive input terminal of the comparator becomes
Figure BDA0002566592530000077
Voltage at inverting input terminal becomes
Figure BDA0002566592530000078
Figure BDA0002566592530000079
Third comparison and judgment Vip-VinWhether or not greater than
Figure BDA00025665925300000710
The second comparison is if
Figure BDA00025665925300000711
Figure BDA00025665925300000712
At this time, the voltage at the positive input terminal of the comparator becomes
Figure BDA00025665925300000713
Voltage at inverting input terminal becomes
Figure BDA00025665925300000714
Third comparison and judgment Vip-VinWhether or not greater than
Figure BDA00025665925300000715
The second comparison is if
Figure BDA00025665925300000716
At this time, the voltage at the positive input terminal of the comparator becomes
Figure BDA00025665925300000717
Figure BDA00025665925300000718
Voltage at inverting input terminal becomes
Figure BDA00025665925300000719
Third comparison and judgment Vip-VinWhether or not greater than
Figure BDA00025665925300000720
The second comparison is if
Figure BDA00025665925300000721
At this time, the voltage at the positive input terminal of the comparator becomes
Figure BDA00025665925300000722
Voltage at inverting input terminal becomes
Figure BDA00025665925300000723
Figure BDA0002566592530000081
Third comparison and judgment Vip-VinWhether or not greater than
Figure BDA0002566592530000082
If it is
Figure BDA0002566592530000083
Or
Figure BDA0002566592530000084
Or
Figure BDA0002566592530000085
Figure BDA0002566592530000086
Or
Figure BDA0002566592530000087
The comparator output is '1', and the third bit output code D of SAR ADC output2Set to 1, and as shown in (1), (3), (5) and (7) of fig. 5(d), the feedback signal of the successive approximation logic control module will adjust the redundant capacitor C at the non-inverting input terminalp0Connected to ground level Gnd.
If it is
Figure BDA0002566592530000088
Or
Figure BDA0002566592530000089
Or
Figure BDA00025665925300000810
Figure BDA00025665925300000811
Or
Figure BDA00025665925300000812
The comparator output is '0', and the third bit output code D of SAR ADC output2At the same time, as shown in (2), (4), (6) and (8) of fig. 5(d), the feedback signal of the successive approximation logic control module will set the redundant capacitor C at the inverting input terminaln0Connected to ground level Gnd.
Then, a fourth comparison is started, if V is the first comparisonip＞VinAt the time of the second comparison
Figure BDA00025665925300000813
At the time of the third comparison
Figure BDA00025665925300000814
As a result of the switching, as shown in fig. 5(D) and (1), when the output code of the high 3-bit is D0D1D2 is 111, the voltage at the non-inverting input terminal of the comparator at the fourth comparison time becomes 111
Figure BDA00025665925300000815
The voltage at the inverting input is still
Figure BDA00025665925300000816
Fourth comparison and judgment Vip-VinWhether or not greater than
Figure BDA00025665925300000817
If it is
Figure BDA00025665925300000818
The lowest order output code D of the SAR ADC3Setting to be 1, wherein the output of the SAR ADC is 1111; otherwise, the lowest order bit of the SAR ADC outputs a code D3Set to 0, the SAR ADC output is 1110.
If it is compared for the first time Vip＞VinAt the time of the second comparison
Figure BDA00025665925300000819
At the time of the third comparison
Figure BDA00025665925300000820
Figure BDA00025665925300000821
As shown in fig. 5(D) and (2), if the high 3-bit output code is D0D1D2 being 110, the voltage at the non-inverting input of the comparator is still at the voltage level of the fourth comparison
Figure BDA00025665925300000822
Voltage at inverting input terminal becomes
Figure BDA00025665925300000823
Judgment Vip-VinWhether or not greater than
Figure BDA00025665925300000824
If it is
Figure BDA00025665925300000825
The lowest order output code D of the SAR ADC3Setting to be 1, wherein the output of the SAR ADC is 1101; otherwise, the lowest order bit of the SAR ADC outputs a code D3Set to 0, the SAR ADC output is 1100.
If it is compared for the first time Vip＞VinAt the time of the second comparison
Figure BDA00025665925300000826
At the time of the third comparison
Figure BDA00025665925300000827
As a result of the switching, as shown in fig. 3 of fig. 5D, when the high 3-bit output code is D0D1D2 being 101, the voltage at the non-inverting input terminal of the comparator at the fourth comparison time becomes 101
Figure BDA00025665925300000828
The voltage at the inverting input is still
Figure BDA00025665925300000829
Judgment Vip-VinWhether or not greater than
Figure BDA00025665925300000830
If it is
Figure BDA00025665925300000831
The lowest order output code D of the SAR ADC3Setting to be 1, and enabling the SAR ADC output to be 1011; otherwise, the lowest order bit of the SAR ADC outputs a code D3Set to 0, the SAR ADC output is 1010.
If it is compared for the first time Vip＞VinAt the time of the second comparison
Figure BDA0002566592530000091
Third stepAt the time of the second comparison
Figure BDA0002566592530000092
As shown in fig. 4 of fig. 5D, if the high 3-bit output code is D0D1D2 equals 100, the voltage at the non-inverting input of the comparator is still equal to 100 during the fourth comparison
Figure BDA0002566592530000093
Voltage at inverting input terminal becomes
Figure BDA0002566592530000094
Judgment Vip-VinWhether or not greater than
Figure BDA0002566592530000095
If it is
Figure BDA0002566592530000096
The lowest order output code D of the SAR ADC3Setting to be 1, and setting SAR ADC output to be 1001; otherwise, the lowest order bit of the SAR ADC outputs a code D3Set to 0, the SAR ADC output is 1000.
If it is compared for the first time Vip＜VinAt the time of the second comparison
Figure BDA0002566592530000097
At the time of the third comparison
Figure BDA0002566592530000098
Figure BDA0002566592530000099
As a result of the switching, as shown in fig. 5(D) and fig. 5 (5), when the high 3-bit output code is D0D1D2 being 011, the voltage at the non-inverting input terminal of the comparator at the fourth comparison time becomes 011
Figure BDA00025665925300000910
The voltage at the inverting input is still
Figure BDA00025665925300000911
Judgment Vip-VinWhether or not greater than
Figure BDA00025665925300000912
If it is
Figure BDA00025665925300000913
Figure BDA00025665925300000914
The lowest order output code D of the SAR ADC3Setting to be 1, wherein the output of the SAR ADC is 0111; otherwise, the lowest order bit of the SAR ADC outputs a code D3Set to 0, the SAR ADC output is 0110.
If it is compared for the first time Vip＜VinAt the time of the second comparison
Figure BDA00025665925300000915
At the time of the third comparison
Figure BDA00025665925300000916
Figure BDA00025665925300000917
As shown in fig. 6 of fig. 5D, if the high 3-bit output code is D0D1D2 being 010, the voltage at the non-inverting input of the comparator is still at the voltage at the fourth comparison
Figure BDA00025665925300000918
Voltage at inverting input terminal becomes
Figure BDA00025665925300000919
Judgment Vip-VinWhether or not greater than
Figure BDA00025665925300000920
If it is
Figure BDA00025665925300000921
Figure BDA00025665925300000922
The lowest order output code D of the SAR ADC3Setting to be 1, and outputting 0101 by the SAR ADC; otherwise SAR ADC lowest order bit output code D3Set to 0, SAR ADC output is 0100.
If it is compared for the first time Vip＜VinAt the time of the second comparison
Figure BDA00025665925300000923
At the time of the third comparison
Figure BDA00025665925300000924
Figure BDA00025665925300000925
As a result of the switching, as shown in fig. 7 of fig. 5D, when the high 3-bit output code is D0D1D2 being 001, the voltage at the non-inverting input terminal of the comparator at the fourth comparison time becomes 001
Figure BDA00025665925300000926
The voltage at the inverting input is still
Figure BDA00025665925300000927
Judgment Vip-VinWhether or not greater than
Figure BDA00025665925300000928
If it is
Figure BDA00025665925300000929
Figure BDA00025665925300000930
The lowest order output code D of the SAR ADC3Setting the SAR ADC to be 1, wherein the output of the SAR ADC is 0011; otherwise, the lowest order bit of the SAR ADC outputs a code D3Set to 0, SAR ADC output is 0010.
If it is compared for the first time Vip＜VinAt the time of the second comparison
Figure BDA0002566592530000101
At the time of the third comparison
Figure BDA0002566592530000102
Figure BDA0002566592530000103
As shown in fig. 8 of fig. 5D, if the high 3-bit output code is D0D1D2 being 000, the voltage at the non-inverting input of the comparator is still equal to 000 during the fourth comparison
Figure BDA0002566592530000104
Voltage at inverting input terminal becomes
Figure BDA0002566592530000105
Judgment Vip-VinWhether or not greater than
Figure BDA0002566592530000106
If it is
Figure BDA0002566592530000107
Figure BDA0002566592530000108
The lowest order output code D of the SAR ADC3Setting to be 1, and setting the output of the SAR ADC to be 0001; otherwise, the lowest order bit of the SAR ADC outputs a code D3Set to 0, the SAR ADC output is 0000.
The conversion of SAR ADC is completed, and 2 times of comparison can be obtained according to different results of 4 times of comparison4The final 4 bits of the different results output the codeword.
Fig. 4 is a sampling conversion diagram of the 4-bit SAR ADC of fig. 3, and it can be seen that the common mode level of the novel common mode switching scheme of the present invention changes only at the last conversion
Figure BDA0002566592530000109
In summary, the invention divides each weighted capacitor into two equivalent capacitors connected in parallel, introduces charge redistribution calculation by combining with the redundant capacitor, and the redundant capacitor is connected with the common-mode level V through the alternative switchcmOr ground level GND, so that the redundant capacitor also participates in the charge redistribution algorithm, and only 2 is neededN-1The unit capacitor saves the circuit area. The invention is in the whole conversion period, except the lastIn addition to the first comparison, the positive phase input voltage V of the comparatoripAnd an inverted input terminal voltage VinThe voltage changing in opposite direction maintains the stability of common mode level, and the last comparison adopts monotonic switching scheme to make the common mode level stable
Figure BDA00025665925300001010
The problem of high design requirements on the comparator caused by large common mode level change is solved.
While the example is illustrated with a 4-bit SAR ADC, other SAR ADCs with different accuracies may be controlled according to the method of the present invention, and those skilled in the art can make various other specific modifications and combinations without departing from the spirit of the present invention, and such modifications and combinations are still within the scope of the present invention.

Claims (2)

1. A capacitor array switching method for a successive approximation type analog-to-digital converter comprises a positive phase input signal switch, an inverse phase input signal switch, a weighted capacitor array, a comparator and a successive approximation logic control module, wherein a positive phase input voltage is connected with a positive phase input end of the comparator through the positive phase input signal switch, and an inverse phase input voltage is connected with an inverse phase input end of the comparator through the inverse phase input signal switch;
the weighted capacitor array comprises a normal phase weighted capacitor array and a reverse phase weighted capacitor array, wherein the normal phase weighted capacitor array comprises a normal phase end redundant capacitor and an N-2 bit normal phase end weighted capacitor, the reverse phase weighted capacitor array comprises a reverse phase end redundant capacitor and an N-2 bit reverse phase end weighted capacitor, and the capacitance values of the N-i bit normal phase end weighted capacitor and the N-i bit reverse phase end weighted capacitor are 2N-1-iC, wherein C is a unit capacitance value, N is the conversion precision of the successive approximation type analog-to-digital converter, i is a positive integer and i ∈ [2, N-1 ]]；
Splitting each weighted capacitor in the N-2 bit positive phase end weighted capacitor and the N-2 bit negative phase end weighted capacitor into two parallel-connected weighted capacitorsSplitting weighting capacitors with equal capacitance values, wherein the capacitance values of the splitting weighting capacitors corresponding to the splitting of the N-i bit positive phase end weighting capacitor and the N-i bit negative phase end weighting capacitor are 2N-1-iC；
The upper polar plate of each split weighted capacitor in the normal phase weighted capacitor array is connected with the normal phase input end of the comparator, and the lower polar plate of the split weighted capacitor array is connected with a reference level or a ground level after passing through a switch; the upper polar plate of each split weighting capacitor in the inverse weighting capacitor array is connected with the inverse input end of the comparator, and the lower polar plate of each split weighting capacitor in the inverse weighting capacitor array is connected with a reference level or a ground level after passing through a switch;
the upper polar plate of the positive phase end redundant capacitor is connected with the positive phase input end of the comparator, and the lower polar plate of the positive phase end redundant capacitor is connected with a common mode level or a ground level after passing through a switch; the upper pole plate of the inverted terminal redundant capacitor is connected with the inverted terminal of the comparator, and the lower pole plate of the inverted terminal redundant capacitor is connected with a common mode level or a ground level after passing through a switch;
the output signal of the comparator passes through the successive approximation logic control module and then generates a control signal for controlling the switch in the weighted capacitor array;
the capacitor array switching method comprises the following steps:
step one, a sampling stage;
connecting the lower polar plates of the positive-phase end redundant capacitor and the negative-phase end redundant capacitor with the common mode level;
in the two split weighted capacitors corresponding to each bit positive phase end weighted capacitor and each bit negative phase end weighted capacitor, the lower pole plate of one split weighted capacitor is connected with a reference level, and the lower pole plate of the other split weighted capacitor is connected with a ground level;
closing the normal phase input signal switch and the reverse phase input signal switch to enable the normal phase input voltage to be connected to the normal phase input end of the comparator, the reverse phase input voltage to be connected to the reverse phase input end of the comparator, and the successive approximation type analog-to-digital converter performs sampling;
disconnecting the input signal switch at the positive phase end and the input signal switch at the negative phase end after sampling is finished;
step two, comparing;
sequentially determining the highest-order output code to the lowest-order output code of the successive approximation type analog-to-digital converter through N times of comparison, and obtaining the N-order output code of the successive approximation type analog-to-digital converter to complete analog-to-digital conversion, wherein the highest-order output code of the successive approximation type analog-to-digital converter is the first-order output code, and the lowest-order output code of the successive approximation type analog-to-digital converter is the Nth-order output code;
the specific method for making the jth comparison is as follows, j ∈ [1, N-2 ]:
comparing the signal of the positive phase input end of the comparator with the signal of the negative phase input end of the comparator, wherein when the signal of the positive phase input end of the comparator is greater than the signal of the negative phase input end of the comparator, the j-th bit output code of the successive approximation type analog-to-digital converter is 1, the lower pole plates of two splitting weighting capacitors corresponding to the N-j-1-th bit positive phase end weighting capacitor are both connected with a ground level, and the lower pole plates of two splitting weighting capacitors corresponding to the N-j-1-th bit negative phase end weighting capacitor are both connected with a reference level;
when the signal of the positive phase input end of the comparator is smaller than the signal of the negative phase input end of the comparator, the j bit output code of the successive approximation type analog-to-digital converter is 0, the lower pole plates of the two splitting weighting capacitors corresponding to the N-j-1 bit positive phase end weighting capacitor are both connected with a reference level, and the lower pole plates of the two splitting weighting capacitors corresponding to the N-j-1 bit negative phase end weighting capacitor are both connected with a ground level;
when the comparison is carried out for the (N-1) th time, comparing the signal of the positive phase input end of the comparator with the signal of the negative phase input end of the comparator, when the signal of the positive phase input end of the comparator is greater than the signal of the negative phase input end of the comparator, the output code of the (N-1) th bit of the successive approximation type analog-to-digital converter is 1, and connecting the lower polar plate of the redundant capacitor of the positive phase end with the ground level; when the signal of the positive phase input end of the comparator is smaller than the signal of the negative phase input end of the comparator, the output code of the N-1 bit of the successive approximation type analog-to-digital converter is 0, and the lower electrode plate of the negative phase end redundant capacitor is connected with the ground level;
and when the signal of the positive phase input end of the comparator is smaller than the signal of the reverse phase input end of the comparator, the Nth bit output code of the successive approximation type analog-to-digital converter is 0.
2. The method as claimed in claim 1, wherein the splitting weight capacitor corresponding to the 1 st bit positive phase end weight capacitor is formed by two unit capacitors connected in series, and the capacitance value of the splitting weight capacitor is a unit capacitance value C.
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CN113922819A (en) * 2021-12-14 2022-01-11 之江实验室 One-step two-bit successive approximation type analog-to-digital converter based on background calibration

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CN110071723A (en) * 2019-04-29 2019-07-30 电子科技大学 A kind of pseudo- common mode switch method for gradual approaching A/D converter

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