CN109995368A - A kind of analog-digital converter of successive approximation - Google Patents
A kind of analog-digital converter of successive approximation Download PDFInfo
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- CN109995368A CN109995368A CN201711489618.9A CN201711489618A CN109995368A CN 109995368 A CN109995368 A CN 109995368A CN 201711489618 A CN201711489618 A CN 201711489618A CN 109995368 A CN109995368 A CN 109995368A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
Abstract
The present invention relates to communication technique field more particularly to a kind of analog-digital converters of successive approximation, are packaged in a chip；It include: sample-and-hold circuit；Comparator；Digital analog converter；Capacitor array includes the multiple conversion capacitors for being separately connected each input terminal of comparator, multiple redundant capacitors and the switch for being separately connected each conversion capacitor and redundant capacitor；Control logic circuit；The size for the weight that the conversion capacitor of each input terminal of connection comparator has is arranged according to a preset order, and the every two weight of adjacent size forms weight ratio；At least there is the of different sizes of two weight ratios；The output end of sample-and-hold circuit is also connected with a buffer, and buffer is for buffering the analog signal of sampling；Buffer is packaged in chip；The formation requirement that under the premise of not reducing digital-to-analogue conversion precision, can form lower reference buffer saves the chip area of reference buffer occupancy.
Description
Technical field
The present invention relates to communication technique field more particularly to a kind of analog-digital converters of successive approximation.
Background technique
Traditional SARADC (successive approximation register analog to digital
The analog-digital converter of converter successive approximation, abbreviation SAR ADC) it is converted using binary capacitor array, simulation letter
Number and conversion digital code correspond, in order to meet 12bit or more high-order requirement, to the mismatch and ginseng of capacitor array
The foundation for examining buffer is proposed very high requirement, and specific capacitance value is bigger to be just able to satisfy matching requirement, reference buffer
The foundation of device requires to establish to enough precision during each bits switch of SAR ADC.Big capacitor array and height
The reference buffer of precision consumes a large amount of area and power consumption.
In order to solve this problem, the framework that existing technology uses is proposed, the change-over period of conversion N+B bit has come
At the numeral output of N number of bit, high speed and high-precision can be thus realized using the method for small capacitor and digital calibration
SAR ADC, but such framework is not well solved there are two problem, and one is for reference buffer
The tolerance for establishing error is limited, and is established precision in order to improve referring generally to buffer and all used decoupling outside piece, but
When frequency applications, the inductance in the parasitic capacitance and connecting line of big weld pad together constitutes with LC oscillation network, and the frequency of oscillation isWill cause SAR ADC with reference to upper fluctuation can not correct transformed error, to influence the precision of ADC.
Summary of the invention
In view of the above-mentioned problems, being packaged in a chip the invention proposes a kind of analog-digital converter of successive approximation；Its
In, comprising:
Sample-and-hold circuit, for being sampled to an externally input analog signal；
Comparator；
Digital analog converter, including the capacitor array being connect with the input terminal of the comparator；
The capacitor array includes the multiple conversion capacitors for being separately connected each input terminal of the comparator, multiple redundancies
Capacitor and the three-dimensional gating switch for being separately connected each the conversion capacitor and the redundant capacitor；
Control logic circuit is separately connected the output end and the digital analog converter of the comparator, according to the ratio
Compared with each three-dimensional gating switch of comparison result Signal Regulation of device output, the electricity of two input terminals of the comparator is realized
Pressure constantly approaches and exports a digital signal；
Wherein, the three-dimensional gating switch, which is adjusted to, connects the sampling holding by a sampling end for the conversion capacitor
When circuit, the conversion capacitor receives the analog signal of the sample-and-hold circuit sampling, and the redundant capacitor passes through company
It is connected to a corresponding solid model signal of the reception from the solid model end in a solid model end；
The three-dimensional gating switch makes the port of the conversion capacitor and redundant capacitor gating further include a ground connection
End and a reference signal receiving end；
Connect the weight that the conversion capacitor of each input terminal of the comparator has size preset according to one it is suitable
The every two weight of sequence arrangement, adjacent size forms weight ratio；
At least there is the of different sizes of two weight ratios；
The weight that each redundant capacitor has is identical as the conversion weight of capacitor described at least one, and each described
The weighted of redundant capacitor；
The output end of the sample-and-hold circuit is also connected with a buffer, and the buffer is used for the mould to sampling
Quasi- signal is buffered；
The buffer is packaged in the chip.
Above-mentioned analog-digital converter, wherein the conversion capacitor for being separately connected each input terminal of the comparator is
13；
The redundant capacitor for being separately connected each input terminal of the comparator is 2.
Above-mentioned analog-digital converter, wherein the preset order is ascending sequence.
Above-mentioned analog-digital converter, wherein the weight of 13 conversion capacitors is arranged by the preset order is respectively
1,2,4,6,12,20,36,64,120,200,360,650,1200；
The weight of 2 redundant capacitors is respectively 20 and 64.
Above-mentioned analog-digital converter, wherein the digital signal of the control logic circuit output is 16.
The utility model has the advantages that a kind of analog-digital converter of successive approximation proposed by the present invention, can not reduce digital-to-analogue conversion
Under the premise of precision, the formation requirement of lower reference buffer is formed, saves the chip area of reference buffer occupancy.
Detailed description of the invention
Fig. 1 is the structure principle chart of the analog-digital converter of successive approximation in one embodiment of the invention.
Specific embodiment
Invention is further explained with reference to the accompanying drawings and examples.
In a preferred embodiment, as shown in Figure 1, proposing a kind of analog-digital converter of successive approximation, encapsulation
In in a chip；Wherein, comprising:
Sample-and-hold circuit (is not shown) in attached drawing, for sampling to externally input analog signal Vin；
Comparator 10；
Digital analog converter, the capacitor array being connect including the input terminal with comparator；
Capacitor array include the multiple conversion capacitors for being separately connected each input terminal of comparator 10, multiple redundant capacitors with
And it is separately connected the three-dimensional gating switch of each conversion capacitor and redundant capacitor；
Control logic circuit 20 is separately connected the output end and digital analog converter of comparator 10, to export according to comparator
The each three-dimensional gating switch of comparison result Signal Regulation, realize that the voltage of two input terminals of comparator 10 constantly approaches and defeated
A digital signal out；
Wherein, three-dimensional gating switch three-dimensional gating switch, which is adjusted to, passes through a sampling end for three-dimensional gating switch conversion capacitor
When connecting three-dimensional gating switch sample-and-hold circuit, three-dimensional gating switch converts capacitor and receives three-dimensional gating switch sampling holding electricity
The three-dimensional gating switch analog signal Vin of road sampling, three-dimensional gating switch redundant capacitor are connect by being connected to solid model end correspondence
Receive the solid model signal Vcm from three-dimensional gating switch solid model end；
Three-dimensional gating switch three-dimensional gating switch makes three-dimensional gating switch conversion capacitor and three-dimensional gating switch redundant electric
The port for holding gating further includes a ground terminal and a reference signal receiving end；
The size for the weight that the conversion capacitor of each input terminal of connection comparator 10 has is arranged according to a preset order,
The every two weight of adjacent size forms weight ratio；
At least there is the of different sizes of two weight ratios；
The weight that each redundant capacitor has is identical as at least one conversion weight of capacitor, and the power of each redundant capacitor
Weight is different；
The output end of sample-and-hold circuit is also connected with a buffer, buffer be used for the analog signal Vin of sampling into
Row buffering；
Buffer is packaged in chip.
In above-mentioned technical proposal, the three-dimensional gating switch that control logic circuit 20 controls is also possible that conversion capacitor and power
Weight capacitor receives signal Vrefp, or receives signal Vrefn, wherein signal Vrefn is the ground signalling of ground terminal, signal
Vrefp is reference voltage signal；Capacitor is converted in Fig. 1 as C0~C12, redundant capacitor is C5r and C7r；Due to using redundancy
Capacitor, such as cooperation least mean square algorithm, can make built in reference buffer, set to save for external reference buffer
Set pad and related electric connection structure the space occupied；The input terminal of comparator 10 may include that a normal phase input end and one are anti-
Phase input terminal, one group of conversion capacitor C0~C12 connects the normal phase input end, identical one group of conversion capacitance connection reverse phase at this time
Input terminal；Similarly, one group of redundant capacitor C5r connects the normal phase input end with C7r, and it is anti-that identical one group of redundant capacitor connects this
Phase input terminal；The connection type of sample-and-hold circuit.
In a preferred embodiment, be separately connected each input terminal of comparator 10 converts capacitor as 13；
The redundant capacitor for being separately connected each input terminal of comparator 10 is 2.
In above-described embodiment, it is preferable that preset order is ascending sequence.
In above-described embodiment, it is preferable that the weight of 13 conversion capacitors is respectively 1,2,4,6,12 by preset order arrangement,
20,36,64,120,200,360,650,1200；
The weight of 2 redundant capacitors is respectively 20 and 64.
In above-mentioned technical proposal, compensating electric capacity C if it existsOS, then the weight for converting the capacitor of capacitor and redundancy is double.
In a preferred embodiment, the three-dimensional gating switch digital signal that control logic circuit 20 exports is 16,
The sum for the capacitor connecting at this time with the same input terminal of comparator 10 is 15.
In conclusion a kind of analog-digital converter of successive approximation proposed by the present invention, is packaged in a chip；Include:
Sample-and-hold circuit, for being sampled to an externally input analog signal；Comparator；Digital analog converter, including compared with
The capacitor array of the input terminal connection of device；Capacitor array includes the multiple conversions electricity for being separately connected each input terminal of comparator
Appearance, multiple redundant capacitors and the three-dimensional gating switch for being separately connected each conversion capacitor and redundant capacitor；Control logic circuit,
It is separately connected the output end and digital analog converter of comparator, with each three-dimensional of comparison result Signal Regulation exported according to comparator
Gating switch realizes that the voltage of two input terminals of comparator constantly approaches and exports a digital signal；Wherein, three-dimensional gating is opened
Pass three-dimensional gating switch, which is adjusted to, connects three-dimensional gating switch sampling guarantor by a sampling end for three-dimensional gating switch conversion capacitor
When holding circuit, three-dimensional gating switch converts the three-dimensional gating switch mould that capacitor receives the sampling of three-dimensional gating switch sample-and-hold circuit
Quasi- signal, by being connected to, a solid model end is corresponding to receive the solid model signal from solid model end to three-dimensional gating switch redundant capacitor；
The size for the weight that the conversion capacitor of each input terminal of connection comparator has is arranged according to a preset order, adjacent size
Every two weight forms weight ratio；At least there is the of different sizes of two weight ratios；The weight that each redundant capacitor has
It is identical as at least one conversion weight of capacitor, and the weighted of each redundant capacitor；The output end of sample-and-hold circuit is also
It is connected with a buffer, buffer is for buffering the analog signal of sampling；Buffer is packaged in chip；It can be not
Under the premise of reducing digital-to-analogue conversion precision, the formation requirement of lower reference buffer is formed, saves reference buffer occupancy
Chip area.
By description and accompanying drawings, the exemplary embodiments of the specific structure of specific embodiment are given, based on present invention essence
Mind can also make other conversions.Although foregoing invention proposes existing preferred embodiment, however, these contents are not intended as
Limitation.
For a person skilled in the art, after reading above description, various changes and modifications undoubtedly be will be evident.
Therefore, appended claims should regard the whole variations and modifications for covering true intention and range of the invention as.It is weighing
The range and content of any and all equivalences, are all considered as still belonging to the intent and scope of the invention within the scope of sharp claim.
Claims (5)
1. a kind of analog-digital converter of successive approximation, is packaged in a chip；It is characterised by comprising:
Sample-and-hold circuit, for being sampled to an externally input analog signal；
Comparator；
Digital analog converter, including the capacitor array being connect with the input terminal of the comparator；
The capacitor array includes the multiple conversion capacitors for being separately connected each input terminal of the comparator, multiple redundant capacitors
And it is separately connected the three-dimensional gating switch of each the conversion capacitor and the redundant capacitor；
Control logic circuit is separately connected the output end and the digital analog converter of the comparator, according to the comparator
The each three-dimensional gating switch of the comparison result Signal Regulation of output, realizes the voltage of two input terminals of the comparator not
It is disconnected to approach and export a digital signal；
Wherein, the three-dimensional gating switch, which is adjusted to, connects the sample-and-hold circuit by a sampling end for the conversion capacitor
When, the conversion capacitor receives the analog signal of the sample-and-hold circuit sampling, and the redundant capacitor is by being connected to
One solid model end is corresponding to receive the solid model signal from the solid model end；
The three-dimensional gating switch make it is described conversion capacitor and the redundant capacitor gating port further include a ground terminal and
One reference signal receiving end；
The size for connecting the weight that the conversion capacitor of each input terminal of the comparator has is arranged according to a preset order
The every two weight of column, adjacent size forms weight ratio；
At least there is the of different sizes of two weight ratios；
The weight that each redundant capacitor has is identical as the conversion weight of capacitor described at least one, and each redundancy
The weighted of capacitor；
The output end of the sample-and-hold circuit is also connected with a buffer, and the buffer, which is used for the simulation to sampling, to be believed
It number is buffered；
The buffer is packaged in the chip.
2. analog-digital converter according to claim 1, which is characterized in that be separately connected each input terminal of the comparator
The capacitor of converting into 13；
The redundant capacitor for being separately connected each input terminal of the comparator is 2.
3. analog-digital converter according to claim 2, which is characterized in that the preset order is ascending sequence.
4. analog-digital converter according to claim 3, which is characterized in that the weight of 13 conversion capacitors is by described pre-
If sequence arrangement is respectively 1,2,4,6,12,20,36,64,120,200,360,650,1200；
The weight of 2 redundant capacitors is respectively 20 and 64.
5. analog-digital converter according to claim 1, which is characterized in that the number of the control logic circuit output
Signal is 16.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711489618.9A CN109995368B (en) | 2017-12-29 | 2017-12-29 | Successive approximation type analog-to-digital converter |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711489618.9A CN109995368B (en) | 2017-12-29 | 2017-12-29 | Successive approximation type analog-to-digital converter |
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| CN109995368B CN109995368B (en) | 2023-06-02 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111510144A (en) * | 2020-04-16 | 2020-08-07 | 芯海科技（深圳）股份有限公司 | Analog-to-digital converter and analog-to-digital conversion method |
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| US6906657B1 (en) * | 2003-12-31 | 2005-06-14 | Intel Corporation | Successive approximation analog-to-digital converter with sample and hold element |
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| US6906657B1 (en) * | 2003-12-31 | 2005-06-14 | Intel Corporation | Successive approximation analog-to-digital converter with sample and hold element |
| US20080316080A1 (en) * | 2007-06-22 | 2008-12-25 | Nec Electronics Corporation | Successive approximation type A/D converter |
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| CN111510144A (en) * | 2020-04-16 | 2020-08-07 | 芯海科技（深圳）股份有限公司 | Analog-to-digital converter and analog-to-digital conversion method |
| CN111510144B (en) * | 2020-04-16 | 2023-03-31 | 芯海科技（深圳）股份有限公司 | Analog-to-digital converter and analog-to-digital conversion method |
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| CN109995368B (en) | 2023-06-02 |
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